JP2004063530A - Circuit board and electronic device using the same - Google Patents

Circuit board and electronic device using the same Download PDF

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Publication number
JP2004063530A
JP2004063530A JP2002216140A JP2002216140A JP2004063530A JP 2004063530 A JP2004063530 A JP 2004063530A JP 2002216140 A JP2002216140 A JP 2002216140A JP 2002216140 A JP2002216140 A JP 2002216140A JP 2004063530 A JP2004063530 A JP 2004063530A
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Prior art keywords
electrode pads
conductor
row
wiring
mounting portion
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JP2002216140A
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Japanese (ja)
Inventor
Hideki Fukunaga
福永 英樹
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Kyocera Corp
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Kyocera Corp
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Priority to JP2002216140A priority Critical patent/JP2004063530A/en
Publication of JP2004063530A publication Critical patent/JP2004063530A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board of a high density wiring pattern which mostly does not have a transmission loss of a signal even when an interval between electrode pads is narrowed and which can obtain desired electrical characteristics. <P>SOLUTION: The circuit board 6 includes a placing part 7a of an electronic component 7 provided on a predetermined region on a main surface of an insulating board 1 formed by laminating a plurality of insulating layers 1a, 1b, electrode pads 4 of a plurality of rows at a substantially equal interval corresponding to connecting terminals of the component 7 at a peripheral side of the part 7a, and lead lines 5 covered from the part 7a toward the peripheral side of the board 1 and connected to the pads 4 and led to an outside region of the pad 4a of a first row arranged on an outermost peripheral side from the pads 4b of a central side of the part 7a. The lines 5 are connected and led to wiring conductors 2a of a lower layer via through conductors 3a at the outside region of the pads 4a of a first row directly under the pads 4b of the central side of the part 7a. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は、シングルチップパッケージ(SCP)、マルチチップパッケージ(MCP)等の高密度配線用の電子部品収納用パッケージとしての配線基板およびこれを用いた電子装置に関する。
【0002】
【従来の技術】
現在の電子機器は、移動体通信機器に代表されるように小型・薄型・軽量・高性能・高機能・高品質・高信頼性が要求されてきており、このような電子機器に搭載される電子装置も小型・高密度化が要求されるようになってきている。そのため、電子装置を構成する配線基板にも小型化・薄型化・多端子化が求められてきており、それを実現するために配線導体層等の導体層の幅を細くするとともにその間隔を狭くし、さらに導体層の多層化・導体層間を接続する貫通導体の小径化により高密度配線化が図られている。
【0003】
このような高密度配線が可能な配線基板として、ビルドアップ法を採用して製作された配線基板が知られている。ビルドアップ法とは、例えば、ガラスクロスやアラミド不布織等の補強材に耐熱性や耐薬品性を有するエポキシ樹脂に代表される熱硬化性樹脂を含浸させて複合化した絶縁基板上に、間に配線導体層を挟んでエポキシ樹脂等の熱硬化性樹脂から成る接着材を塗布して絶縁層を形成するとともに絶縁層を加熱硬化させた後、配線導体層上部の絶縁層にレーザで径が30〜200μm程度の貫通孔を穿設し、しかる後、絶縁層表面を化学粗化し、さらに無電解銅めっき法および電解銅めっき法を用いて貫通孔側面および貫通孔底面の配線導体層上に導体膜を被着して貫通導体を形成するとともに絶縁層表面に貫通導体と接続する配線導体層を形成し、さらに、絶縁層や貫通導体・配線導体層の形成を複数回繰り返すことにより配線基板を製作する方法である。
【0004】
そしてこのような配線基板は、表面の半導体素子等の電子部品の搭載部に導出する、配線基板を貫通して形成された貫通導体上に設けられた電極パッドに、電子部品の下面に形成された各電極を半田バンプ等の導電性接合材を介して接続することにより電子装置となる。
【0005】
しかしながら、電子部品が高密度化してその電極数が増加するにつれて、配線基板表面の電子部品の搭載部に導出する、配線基板を貫通して形成された貫通導体を形成することが困難となってきている。このため、貫通導体をその表面が配線基板表面の電子部品の搭載部の外側に導出するように形成するとともに、電子部品の搭載部に形成された電極パッドと貫通導体とを引き出し線で接続することが行なわれている。
【0006】
しかしながら、このような配線基板においても、電子部品のより高密度化・多端子化にともない、それに接続される電極パッドも複数列に等間隔で配列された多点格子状となり、その結果、全ての電極パッドに引き出し線を接続することが困難であるという問題点を有していた。これは、多点格子状に形成された電極パッドのうち中央側に位置する電極パッド用の引き出し線を、外側に位置する電極パッド間の隙間を通して電子部品の搭載部の外側に導出するためであり、電極パッドの配列数が増加すると最も外側の電極パッド間の隙間に多数の引き出し線を通すことができなくなることによるものである。
【0007】
このような問題点を解決するために、特開2001−127192号公報には、中央側に位置する電極パッドの引き出し線のうち電極パッド間のギャップに形成される部分のみを細線化することが提案されている。
【0008】
【発明が解決しようとする課題】
しかしながら、特開2001−127192号公報に記載された配線基板では、電子部品の高密度化・多端子化がさらに進み、引き出し線をより細線化・微細化した場合には、引き出し線の電気抵抗が大きくなり信号の伝送損失が増大して、所望の電気特性が得られなくなってしまうという問題点を有していた。また、逆に電気的特性を優先して配線幅を太くすると、前述したように電極パッド間に通すことのできる引き出し線本数が減少し、配線が不可能になるという問題点を有していた。
さらに、引き出し線を最も外側の電極パッド間を通してこの外側に引き出す場合、引き出し線を一旦最も外側の電極パッド間の近傍の領域まで引き出し、さらにこの近傍の領域から電極パッド間を通してこの外側の領域へ引き出すために、引き出し線の長さが長くなり、引き出し線の電気抵抗がさらに大きくなってしまうという問題点を有していた。
【0009】
本発明は、上記従来技術における問題点に鑑み完成されたものであり、その目的は、電極パッド数が増加しても電極パッドの引き出し線幅を細くすることなく、従って、信号の伝送損失が少ない高密度配線パターンの配線基板およびこれを用いた電子装置を提供することにある。
【0010】
【課題を解決するための手段】
本発明の配線基板は、複数の絶縁層を積層して成る絶縁基板の主面上の所定領域に設けられた電子部品の搭載部と、この搭載部内の周辺側に電子部品の接続端子に対応して複数列に略等間隔で配列された電極パッドと、搭載部より絶縁基板の周辺側に向かって形成され、各電極パッドに接続されるとともに搭載部の中央側の電極パッドからはこの電極パッドの直下および最も周辺側に配列された第1列の電極パッドの外側の領域でそれぞれ貫通導体を介して下層の配線導体に接続されて、この配線導体の一部が平面視で第1列の電極パッドと重なるようにして第1列の電極パッドの外側の領域へ引き出されている引き出し線とを具備することを特徴とするものである。
【0011】
また本発明の配線基板は、上記構成において、下層の配線導体の幅を第1列の電極パッドから絶縁基板の周辺側における引き出し線の幅以上としていることを特徴とするものである。
【0012】
さらに本発明の電子装置は、上記の配線基板の搭載部に電子部品を搭載し、この電子部品の各接続端子とこれに対応する各電極パッドとを電気的に接続していることを特徴とするものである。
【0013】
本発明の配線基板によれば、引き出し線が搭載部より絶縁基板の周辺側に向かって形成され、各電極パッドに接続されるとともに搭載部の中央側の電極パッドからはこの電極パッドの直下および最も周辺側に配列された第1列の電極パッドの外側の領域でそれぞれ貫通導体を介して下層の配線導体に接続されて、第1列の電極パッドの外側の領域へ引き出されていることから、引き出し線を第1列の電極パッド間の間隔とは関係なく第1列の電極パッドの外側の領域へ引き出すことができ、その結果、電極パッドが高密度に形成されて最も周辺側に配列された第1列の電極パッド間の間隔が狭くなった場合においても、引き出し線の引き出しが不可能となったり、引き出し線の幅が細線化・微細化して引き出し線の電気抵抗が大きくなり信号の伝送損失が増大してしまうことはない。また、引き出し線が下層の配線導体の一部を平面視で第1列の電極パッドと重なるようにして第1列の電極パッドの外側の領域へ引き出されていることから、第1列の電極パッド間の間隔よりも幅の広い引き出し線を搭載部の中央側の電極パッドから第1列の電極パッドの外側へ直線的に引き出すことができ、その結果、引き出し線の電気抵抗が大きくなり信号の伝送損失が増大してしまうこともない。
【0014】
また、本発明の配線基板によれば、下層の配線導体の幅を第1列の電極パッドから絶縁基板の周辺側における引き出し線の幅以上としたことから、配線基板の表面で引き出し線を電極パッド間を通るように細線化して引き出す場合に較べて、引き出し線の電気抵抗を大きく低減することができ、その結果、信号の伝送損失が小さい配線基板とすることができる。
【0015】
本発明の電子装置によれば、上記の配線基板の搭載部に電子部品を搭載し、この電子部品の各接続端子とこれに対応する各電極パッドとを電気的に接続したことから、配線が高密度であるとともに、信号の伝送特性に優れた電子装置とすることができる。
【0016】
【発明の実施の形態】
次に、本発明の配線基板およびこれを用いた電子装置を添付の図面に基づいて詳細に説明する。
【0017】
図1は、本発明の配線基板に半導体素子等の電子部品を搭載して成る電子装置の断面図であり、図2は、本発明の配線基板の要部拡大平面図である。
これらの図において、1は絶縁基板、2は配線導体、3は貫通導体、4は電極パッド、5は引き出し線であり、主にこれらで本発明の配線基板6が構成される。また、この配線基板6に電子部品7を実装することにより本発明の電子装置8と成る。
【0018】
絶縁基板1は、電子部品7を支持する支持部材としての機能を有し、縦・横の長さが5〜50mmであり、この図の例では、板状の芯体絶縁層1aと、この上下面に被着した絶縁層1bとから形成されている。
【0019】
芯体絶縁層1aは、絶縁基板1に強度を付与するとともにそりを防止する機能を有し、その厚みが0.3〜1.5mm程度であり、ガラス繊維を縦横に織り込んだガラスクロスにエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させて成り、その上下面には銅・ニッケル・金等の薄膜からなる配線導体2が被着形成されている。また、芯体絶縁層1aは、その上面から下面にかけて直径が0.1〜1.0mmの複数のスルーホール11を有しており、そして、そのスルーホール11の内壁には銅膜から成るスルーホール導体12が被着形成されており、上下面の配線導体2がスルーホール導体12を介して電気的に接続されている。
【0020】
このような芯体絶縁層1aは、ガラスクロスに未硬化の熱硬化性樹脂を含浸させたシートを熱硬化させた後、これに上面から下面にかけてドリル加工を施すことにより製作される。また、配線導体2は、芯体絶縁層1a用の未硬化シートの上下全面に厚みが3〜50μmの銅膜を被着しておくとともにこの銅膜をシートの硬化後にエッチング加工することにより所定のパターンに形成される。さらに、スルーホール導体12は、芯体絶縁層1aにスルーホール11をドリル等を用いて穿設した後、このスルーホール11の内周壁に周知のめっき法により厚みが3〜50μm程度の銅めっきを析出させることにより形成される。
【0021】
また、芯体絶縁層1aは、そのスルーホール11の内部にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂から成る樹脂柱13が充填されている。樹脂柱13は、スルーホール11を塞ぐことによりスルーホール11の直上および直下に絶縁層1bを形成可能とするためのものであり、未硬化のペースト状の熱硬化性樹脂をスルーホール11内にスクリーン印刷法により充填し、これを熱硬化させた後、その上下面を略平坦に研磨することにより形成される。そして、この樹脂柱13を含む芯体絶縁層1aの上下面に絶縁層1bが積層されている。
【0022】
芯体絶縁層1aの上下面に積層された絶縁層1bは、エポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂から成り、それぞれの厚みが10〜80μmであり、各層の上面から下面にかけて直径が20〜100μmの貫通孔3を有している。絶縁層1bは、配線導体2を高密度に配線するための絶縁間隔を提供するためのものであり、上層と下層の配線導体2同士を貫通孔3の内壁に形成された銅膜から成る貫通導体3aを介して電気的に接続することにより高密度配線を立体的に形成可能としている。
【0023】
このような絶縁層1bは、従来周知のドクターブレード法を採用して形成した、絶縁層1bと成る未硬化の熱硬化性樹脂フィルムを配線導体2を被着した芯体絶縁層1aの上下面に貼着し、これを熱硬化させるとともに炭酸ガスレーザやUVレーザ・エキシマレーザ等のレーザ加工により貫通孔3を形成し、さらに、絶縁層1b上に配線導体2を、貫通孔3内部に貫通導体3aを形成した後、同様にして上層の絶縁層1bを順次積み重ねることによって積層される。
【0024】
なお、絶縁層1bは、例えばエポキシ樹脂と熱可塑性樹脂・エラストマー・無機絶縁性フィラーに溶剤等を添加した混合物を混練して液状ワニスを得、この液状ワニスをポリエチレンテレフタレート(PET)製離型シート上に塗布し、60〜100℃の温度で乾燥することによりフィルム状に成形される。また、絶縁層1bとなる乾燥後のフィルムは、フィルム上面にポリエチレンシートを積層し、ロール状に巻き取ることにより容易に貯蔵できる。さらに、フィルムの厚さは自由に設定することができるが、絶縁性の観点から20〜100μmの範囲の厚さが好ましい。
【0025】
また、配線導体2および貫通導体3aは、絶縁層1bの表面および貫通孔3内部を過マンガン酸塩類水溶液等の粗化液に浸漬し粗化した後、無電解めっき用のパラジウム触媒の水溶液中に浸漬し絶縁層1bの表面および貫通孔3内部にパラジウム触媒を付着させ、しかる後、硫酸銅・ロッセル塩・ホルマリン・EDTAナトリウム塩・安定剤等から成る無電解銅めっき液に約30分間浸漬して1〜2μm程度の無電解銅めっきを析出させ、つぎに、無電解銅めっき上に耐めっき樹脂層を被着し露光・現像により配線導体2のパターン形状に、電解銅めっきを被着させるための開口部を形成し、さらに、硫酸・硫酸銅5水和物・塩素・光沢剤等から成る電解銅めっき液に数A/dmの電流を印加しながら数時間浸漬することにより開口部に電解銅めっきを被着した後、水酸化ナトリウムで耐めっき樹脂層を剥離し、そして、耐めっき樹脂層を剥離したことにより露出する無電解銅めっきを硫酸・過酸化水素水等の硫酸系水溶液によりエッチング除去し、しかる後、無電解銅めっき層を除去することにより形成される。
【0026】
なお、配線導体2および貫通導体3aの厚みは、高速の信号を伝達させるという観点からは3μm以上であることが好ましく、配線導体2および貫通導体3aを絶縁層1bに被着形成する際に配線導体2および貫通導体3aに大きな応力を残留させず、配線導体2および貫通導体3aが絶縁層1bから剥離しにくいものとするためには50μm以下としておくことが好ましい。
【0027】
そして、絶縁層1bの一方の最外層表面の電子部品の搭載部7aに形成された配線導体2の一部は、電子部品7の各電極に例えば鉛−錫から成る導体バンプ9を介して接合される電子部品の接続用の電極パッド4および引き出し線5を形成し、また、絶縁層1bの他方の最外層表面に形成された配線導体2の一部は、外部電気回路基板の各電極(図示せず)に例えば鉛−錫から成る導体バンプ9を介して接続される。
【0028】
なお、電極パッド4および引き出し線5の露出する表面には、その酸化腐蝕を防止するとともに導体バンプ9との接続を良好とするために、半田との濡れ性が良好で耐腐蝕性に優れたニッケル・金等のめっき層が被着されている。
【0029】
また、電子部品7の搭載部7aに形成される電極パッド4は、その直径が50〜300μmで、複数列に等間隔で配列された多点格子状であり、搭載部7aの中央側の電極パッド4bと中央側の電極パッド4bからは最も周辺側に配列された第1列の電極パッド4aとから構成されている。さらに、引き出し線5は、搭載部7aより絶縁基板1の周辺側に向かって被着形成され、各電極パッド4bに接続されるとともに搭載部7aの中央側の電極パッド4bからは最も周辺側に配列された第1列の電極パッド4aの外側の領域へ引き出されている。
【0030】
そして、本発明の配線基板6においては、引き出し線5が搭載部7aより絶縁基板1の周辺側に向かって形成され、各電極パッド4に接続されるとともに搭載部の中央側の電極パッド4bからはこの電極パッド4bの直下および最も周辺側に配列された第1列の電極パッド4aの外側の領域でそれぞれ貫通導体3aを介して下層の配線導体2aに接続されて、この配線導体2aの一部が平面視で第1列の電極パッド4aと重なるようにして第1列の電極パッド4aの外側の領域へ引き出されている。そして、本発明においてはこのことが重要である。
【0031】
本発明の配線基板6によれば、引き出し線5が搭載部7aより絶縁基板1の周辺側に向かって形成され、各電極パッド4に接続されるとともに搭載部7aの中央側の電極パッド4bからはこの電極パッド4bの直下および最も周辺側に配列された第1列の電極パッド4aの外側の領域でそれぞれ貫通導体3aを介して下層の配線導体2aに接続されて、この配線導体2aの一部が平面視で第1列の電極パッド4aと重なるようにして第1列の電極パッド4aの外側の領域へ引き出されていることから、引き出し線5を第1列の電極パッド4a間の間隔とは関係なく第1列の電極パッド4aの外側の領域へ引き出すことができ、その結果、電極パッド4が高密度に形成されて最も周辺側に配列された第1列の電極パッド4a間の間隔が狭くなった場合においても、引き出し線5の引き出しが不可能となったり、引き出し線5の幅が細線化・微細化して引き出し線の電気抵抗が大きくなり信号の伝送損失が増大してしまうことはない。また、引き出し線5が下層の配線導体2aの一部を平面視で第1列の電極パッド4aと重なるようにして第1列の電極パッド4aの外側の領域へ引き出されていることから、第1列の電極パッド4a間の間隔よりも幅の広い引き出し線5を搭載部7aの中央側の電極パッド4bから第1列の電極パッド4aの外側へ直線的に引き出すことができ、その結果、引き出し線5の電気抵抗が大きくなり信号の伝送損失が増大してしまうこともない。
【0032】
なお、最外層の絶縁層1bに形成され、その直上に電極パッド4bが形成される貫通孔3aは、内周壁にめっきにより貫通導体3bを被着形成後、その内部が絶縁層1bと同様な樹脂を用いて充填されている。そして、この貫通孔3aの直上に貫通導体3bと電気的に接続する電極パッド4が形成される。あるいは、貫通孔3aを貫通導体3bを形成するめっきで充填し、その表面を電極パッド4としてもよい。
【0033】
また、本発明の配線基板6においては、下層の配線導体2aの幅を第1列の電極パッド4aから絶縁基板1の周辺側における引き出し線5の幅以上とすることが好ましい。下層の配線導体2aの幅を第1列の電極パッド4aから絶縁基板1の周辺側における引き出し線5の幅以上とすることにより、引き出し線5を配線基板1表面の第1列の電極パッド4a間のギャップを通るように細線化して引き出す場合に較べて引き出し線5の電気抵抗を大きく低減することができ、その結果、信号の伝送損失がより小さな配線基板6とすることができる。
【0034】
なお、引き出し線5においては、図2の部分平面図に示すように、下層の配線導体2a以外の部分は絶縁基体1の表面に形成されている。また、本例では、下層の配線導体2aを、絶縁基体1の表面に形成された引き出し線5と1層の絶縁層1bを隔てて形成した場合を示しているが、電極パッド4の数量によっては、下層の配線導体2aを絶縁基体1の表面に形成された引き出し線5と2層以上の絶縁層1bを隔てて形成してもよい。さらに、下層の配線導体2aを複数の絶縁層1b上に形成してもよい。
【0035】
また、電極パッド4aと下層の配線導体2aおよび引き出し線5と下層の配線導体2aとを接続する貫通導体3aは、絶縁層1bに配線導体2および貫通導体3aを形成する際に、あらかじめ所定の位置に形成しておけばよい。
【0036】
そして、引き出し線5の搭載部7aの外側に形成された一部を、絶縁層1bに形成した貫通導体3a・配線導体2、および芯体絶縁層1aに形成したスルーホール導体12・配線導体2を介して配線基板6の他方の表面に形成された外部電気回路との接続用電極パッドに電気的に接続することにより、本発明の配線基板6と成る。
【0037】
かくして、本発明の配線基板6によれば、電極パッド数4が増加したとしても配線が不可能になることはなく、高密度配線が可能な配線基板6とすることができる。また、引き出し線5の幅を第1列の電極パッド4a間で微細化・細線化する必要がないことから、引き出し線5の電気抵抗が増加して信号の伝送特性が低下することのない配線基板6とすることができる。
【0038】
なお、本発明の配線基板6は上述の実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能であり、例えば、上述の例では絶縁層1bを芯体絶縁層1aの上下面に積層し、この絶縁層1b上に配線導体2を形成したが、絶縁層1bを芯体絶縁層1aの片面のみに積層してもよい。また、上述の例では、絶縁基板1を芯体絶縁層1aに絶縁層1bを積層して成るものとしたが、絶縁基板1を芯体絶縁層1aのみで構成してもよい。
【0039】
次に、本発明の電子装置8は、配線基板6の電子部品7の搭載部7aに電子部品7を搭載し、電子部品7の各電極とこれに対応する各電極パッド4とを導体バンプ9を介して電気的に接続することにより形成される。
【0040】
導体バンプ9は、電極パッド4上に鉛−錫・錫−亜鉛・錫−銀−ビスマス合金等の導電材料より形成されている。このような導体バンプ9は次に述べる方法により形成される。まず、配線基板6表面に、電極パッド4上に開口を有するソルダーレジスト層14を従来周知のスクリーン印刷法を用いて被着する。ソルダーレジスト層14は、厚みが10〜50μmであり、例えばアクリル変性エポキシ樹脂等の感光性樹脂と開始剤とから成る混合物に30〜70重量%のシリカやタルク等の無機粉末フィラーを含有させた絶縁材料から成り、隣接する電極パッド4同士が導体バンプ9により電気的に短絡することを防止するとともに、電極パッド4と絶縁基板1との接合強度を向上させる機能を有する。次に、導体バンプ9が例えば鉛−錫から成る半田の場合、鉛−錫から成る半田ペーストをソルダーレジスト層14の開口の露出した電極パッド4上にスクリーン印刷で充填し、リフロー炉を通すことにより電極パッド4上に半球状に固着形成される。なお、配線基板6の表面に露出した電極パッド4の表面にニッケル・金等の良導電性で耐食性に優れた金属をめっき法により1〜20μmの厚みに被着させておくと、露出した電極パッド4の酸化腐食を有効に防止することができるとともに電極パッド4と導体バンプ4との接続を良好となすことができる。
【0041】
しかる後、電極パッド4に電子部品7の各電極を導体バンプ9を介して接合して電子部品7を搭載するとともに配線基板6と電子部品7とをアンダーフィル材15で接着固定し、さらに、この電子部品7を図示しない蓋体やポッティング樹脂により封止することによって電子装置8と成り、配線基板6の電子部品7の搭載部7aと反対側の電極パッドを外部電気回路基板の配線導体(図示せず)に電気的に接続することにより本発明の電子装置8が外部電気回路基板に実装されることとなる。
【0042】
なお、ソルダーレジスト層14は、感光性樹脂と光開始剤と無機粉末フィラーとから成る未硬化樹脂フィルムあるいは熱硬化性樹脂と無機粉末フィラーとから成る未硬化樹脂ワニスを塗布するか、未硬化樹脂フィルムをラミネートした後、露光・現像により開口部を形成し、これをUV硬化および熱硬化させることにより被着される。
【0043】
かくして、本発明の電子装置8によれば、上記の配線基板6の搭載部7aに電子部品7を搭載し、上記電子部品7の各接続端子とこれに対応する各電極パッド4とを電気的に接続したことから、配線が高密度であるとともに信号の伝送特性に優れた電子装置とすることができる。
【0044】
なお、本発明の配線基板および電子装置は上述の実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能であることは言うまでもない。
【0045】
【発明の効果】
本発明の配線基板によれば、引き出し線が搭載部より絶縁基板の周辺側に向かって形成され、各電極パッドに接続されるとともに搭載部の中央側の電極パッドからはこの電極パッドの直下および最も周辺側に配列された第1列の電極パッドの外側の領域でそれぞれ貫通導体を介して下層の配線導体に接続されて、第1列の電極パッドの外側の領域へ引き出されていることから、引き出し線を第1列の電極パッド間の間隔とは関係なく第1列の電極パッドの外側の領域へ引き出すことができ、その結果、電極パッドが高密度に形成されて最も周辺側に配列された第1列の電極パッド間の間隔が狭くなった場合においても、引き出し線の引き出しが不可能となったり、引き出し線の幅が細線化・微細化して引き出し線の電気抵抗が大きくなり信号の伝送損失が増大してしまうことはない。また、引き出し線が下層の配線導体の一部を平面視で第1列の電極パッドと重なるようにして第1列の電極パッドの外側の領域へ引き出されていることから、第1列の電極パッド間の間隔よりも幅の広い引き出し線を搭載部の中央側の電極パッドから第1列の電極パッドの外側へ直線的に引き出すことができ、その結果、引き出し線の電気抵抗が大きくなり信号の伝送損失が増大してしまうこともない。
【0046】
また、本発明の配線基板によれば、下層の配線導体の幅を第1列の電極パッドから絶縁基板の周辺側における引き出し線の幅以上としたことから、配線基板の表面で引き出し線を電極パッド間を通るように細線化して引き出す場合に較べて、引き出し線の電気抵抗を大きく低減することができ、その結果、信号の伝送損失が小さい配線基板とすることができる。
【0047】
本発明の電子装置によれば、上記の配線基板の搭載部に電子部品を搭載し、この電子部品の各接続端子とこれに対応する各電極パッドとを電気的に接続したことから、配線が高密度であるとともに、信号の伝送特性に優れた電子装置とすることができる。
【図面の簡単な説明】
【図1】本発明の配線基板および電子装置の実施の形態の一例を示す断面図である。
【図2】本発明の配線基板の要部拡大平面図である。
【符号の説明】
1・・・・・・絶縁基板
1a・・・・・芯体絶縁層
1b・・・・・絶縁層
2・・・・・・配線導体
2a・・・・・下層の配線導体
3・・・・・・貫通導体
3a・・・・・貫通孔
4・・・・・・電極パッド
4a・・・・・第1列の電極パッド
4b・・・・・中央側の電極パッド
5・・・・・・引き出し線
6・・・・・・配線基板
7・・・・・・電子部品
8・・・・・・電子装置
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a wiring board as a package for storing electronic components for high-density wiring such as a single-chip package (SCP) and a multi-chip package (MCP), and an electronic device using the same.
[0002]
[Prior art]
Current electronic devices are required to be small, thin, lightweight, high-performance, high-performance, high-quality, and high-reliable, as represented by mobile communication devices, and are mounted on such electronic devices. Electronic devices have also been required to be smaller and more dense. For this reason, there has been a demand for smaller, thinner, and more terminals for the wiring boards that constitute the electronic device, and in order to achieve this, the width of the conductor layers such as the wiring conductor layers and the like have been reduced and the intervals between them have been reduced. Furthermore, high-density wiring has been achieved by increasing the number of conductor layers and reducing the diameter of through conductors connecting the conductor layers.
[0003]
As a wiring board capable of such high-density wiring, a wiring board manufactured by employing a build-up method is known. With the build-up method, for example, a reinforcing material such as glass cloth or aramid non-woven fabric is impregnated with a thermosetting resin typified by an epoxy resin having heat resistance and chemical resistance, on an insulating substrate that is composited, After applying an adhesive made of a thermosetting resin such as epoxy resin with the wiring conductor layer interposed therebetween to form an insulation layer and heat-curing the insulation layer, the diameter of the laser is applied to the insulation layer above the wiring conductor layer by laser. Drills through holes of about 30 to 200 μm, then chemically roughens the surface of the insulating layer, and further uses an electroless copper plating method and an electrolytic copper plating method on the wiring conductor layer on the side surfaces of the through holes and the bottom surface of the through holes. By forming a through conductor by applying a conductor film to the wiring layer, forming a wiring conductor layer to be connected to the through conductor on the surface of the insulating layer, and forming the insulating layer and the through conductor / wiring conductor layer a plurality of times. Make a substrate It is the law.
[0004]
And such a wiring board is formed on a lower surface of the electronic component, on an electrode pad provided on a through conductor formed through the wiring board, leading to a mounting portion of an electronic component such as a semiconductor element on the surface. An electronic device is obtained by connecting the respective electrodes via a conductive bonding material such as a solder bump.
[0005]
However, as the density of electronic components increases and the number of electrodes increases, it becomes difficult to form a through conductor formed through the wiring board and led out to the mounting portion of the electronic component on the surface of the wiring board. ing. For this reason, the through conductor is formed so that its surface is led out of the mounting portion of the electronic component on the surface of the wiring board, and the electrode pad formed on the mounting portion of the electronic component and the through conductor are connected by a lead wire. Things are going on.
[0006]
However, even in such a wiring board, with the increase in the density and the number of terminals of electronic components, the electrode pads connected thereto also have a multi-point lattice shape arranged in a plurality of rows at equal intervals. However, there is a problem that it is difficult to connect the lead wire to the electrode pad. This is because the lead wire for the electrode pad located on the center side of the electrode pads formed in a multi-point lattice shape is led out of the mounting portion of the electronic component through the gap between the electrode pads located on the outside. The reason is that, when the number of arranged electrode pads increases, a large number of lead lines cannot pass through the gap between the outermost electrode pads.
[0007]
In order to solve such a problem, Japanese Patent Application Laid-Open No. 2001-127192 discloses that only a portion formed in a gap between electrode pads among lead lines of an electrode pad located on the center side is thinned. Proposed.
[0008]
[Problems to be solved by the invention]
However, in the wiring board described in Japanese Patent Application Laid-Open No. 2001-127192, the density and the number of terminals of electronic components are further increased, and when the lead wires are made thinner and finer, the electrical resistance of the lead wires is reduced. And the transmission loss of the signal increases, so that desired electrical characteristics cannot be obtained. On the other hand, if the wiring width is made wider by giving priority to the electrical characteristics, the number of lead wires that can be passed between the electrode pads is reduced as described above, so that wiring becomes impossible. .
Further, in the case where the lead line is drawn out to the outside through the space between the outermost electrode pads, the lead line is drawn once to a region near the outermost electrode pad, and further from the region in the vicinity to the outside region through the space between the electrode pads. There is a problem that the length of the lead line becomes longer due to the drawing, and the electrical resistance of the lead line further increases.
[0009]
The present invention has been completed in view of the above-mentioned problems in the prior art, and its purpose is to reduce the lead wire width of the electrode pads even if the number of electrode pads increases, and therefore, signal transmission loss is reduced. An object of the present invention is to provide a wiring board having a small high-density wiring pattern and an electronic device using the same.
[0010]
[Means for Solving the Problems]
The wiring board of the present invention has a mounting portion for an electronic component provided in a predetermined area on a main surface of an insulating substrate formed by laminating a plurality of insulating layers, and a connection terminal of the electronic component on a peripheral side in the mounting portion. And electrode pads arranged at substantially equal intervals in a plurality of rows, and formed from the mounting portion toward the peripheral side of the insulating substrate, connected to each electrode pad, and from the electrode pad on the center side of the mounting portion to the electrode pad. Each of the wiring conductors is connected to a lower layer wiring conductor via a through conductor in a region directly below the pad and outside the first row of electrode pads arranged on the most peripheral side, and a part of this wiring conductor is viewed in plan from the first row. And a lead line drawn to a region outside the first row of electrode pads so as to overlap the electrode pads of the first row.
[0011]
Further, the wiring board of the present invention is characterized in that, in the above configuration, the width of the lower layer wiring conductor is equal to or greater than the width of the lead line from the first row of electrode pads to the peripheral side of the insulating substrate.
[0012]
Further, the electronic device of the present invention is characterized in that an electronic component is mounted on the mounting portion of the wiring board, and each connection terminal of the electronic component is electrically connected to each corresponding electrode pad. Is what you do.
[0013]
According to the wiring board of the present invention, a lead line is formed from the mounting portion toward the peripheral side of the insulating substrate, connected to each electrode pad, and from the electrode pad on the center side of the mounting portion directly below the electrode pad and In the region outside the first row of electrode pads arranged on the most peripheral side, they are connected to the lower layer wiring conductors via the through conductors, respectively, and are drawn out to the region outside the first row of electrode pads. In addition, the lead lines can be drawn out to a region outside the first row of electrode pads irrespective of the interval between the first row of electrode pads. As a result, the electrode pads are formed at a high density and are arranged on the most peripheral side. Even when the distance between the first row of electrode pads is reduced, it is not possible to draw out the lead line, or the width of the lead line becomes thinner and finer, and the electrical resistance of the lead line becomes larger. Never transmission loss is increased. Further, since the lead wire is drawn to a region outside the first row of electrode pads so that a part of the lower layer wiring conductor overlaps the first row of electrode pads in plan view, the first row of electrode lines A lead line wider than the interval between the pads can be drawn linearly from the electrode pad on the center side of the mounting portion to the outside of the first row of electrode pads. As a result, the electrical resistance of the lead line increases and the signal Transmission loss does not increase.
[0014]
Further, according to the wiring board of the present invention, since the width of the lower-layer wiring conductor is set to be equal to or larger than the width of the lead from the first row of electrode pads to the periphery of the insulating substrate, the lead is formed on the surface of the wiring board by the electrode. The electrical resistance of the lead wire can be greatly reduced as compared with the case where the wire is drawn out by making the wire thinner so as to pass between the pads, and as a result, a wiring board with a small signal transmission loss can be obtained.
[0015]
According to the electronic device of the present invention, an electronic component is mounted on the mounting portion of the wiring board, and each connection terminal of the electronic component is electrically connected to each corresponding electrode pad. An electronic device having high density and excellent signal transmission characteristics can be provided.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, a wiring board of the present invention and an electronic device using the same will be described in detail with reference to the accompanying drawings.
[0017]
FIG. 1 is a sectional view of an electronic device in which electronic components such as semiconductor elements are mounted on a wiring board of the present invention, and FIG. 2 is an enlarged plan view of a main part of the wiring board of the present invention.
In these figures, 1 is an insulating substrate, 2 is a wiring conductor, 3 is a through conductor, 4 is an electrode pad, and 5 is a lead, and these mainly constitute the wiring board 6 of the present invention. The electronic device 8 of the present invention is obtained by mounting the electronic component 7 on the wiring board 6.
[0018]
The insulating substrate 1 has a function as a support member for supporting the electronic component 7 and has a vertical and horizontal length of 5 to 50 mm. In the example of this figure, a plate-shaped core insulating layer 1 a And an insulating layer 1b attached to the upper and lower surfaces.
[0019]
The core insulating layer 1a has a function of imparting strength to the insulating substrate 1 and preventing warpage, and has a thickness of about 0.3 to 1.5 mm. It is impregnated with a thermosetting resin such as a resin or a bismaleimide triazine resin, and a wiring conductor 2 made of a thin film of copper, nickel, gold or the like is formed on the upper and lower surfaces thereof. Further, the core insulating layer 1a has a plurality of through holes 11 having a diameter of 0.1 to 1.0 mm from the upper surface to the lower surface, and the inner wall of the through hole 11 has a through hole made of a copper film. The hole conductors 12 are formed by attachment, and the wiring conductors 2 on the upper and lower surfaces are electrically connected through the through-hole conductors 12.
[0020]
Such a core insulating layer 1a is manufactured by thermally curing a sheet in which a glass cloth is impregnated with an uncured thermosetting resin, and then performing drilling from the upper surface to the lower surface. The wiring conductor 2 has a predetermined thickness by coating a copper film having a thickness of 3 to 50 μm on the entire upper and lower surfaces of the uncured sheet for the core insulating layer 1a and etching the copper film after the sheet is cured. Is formed. Further, the through-hole conductor 12 is formed by drilling a through-hole 11 in the core insulating layer 1a using a drill or the like, and then plating the inner peripheral wall of the through-hole 11 with a copper plating having a thickness of about 3 to 50 μm by a known plating method. Is formed by precipitation.
[0021]
In the core insulating layer 1a, resin columns 13 made of a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin are filled in the through holes 11 thereof. The resin pillar 13 is for allowing the insulating layer 1 b to be formed directly above and directly below the through hole 11 by closing the through hole 11, and an uncured paste-like thermosetting resin is placed in the through hole 11. It is formed by filling by a screen printing method, thermally curing the material, and then polishing the upper and lower surfaces thereof to be substantially flat. An insulating layer 1b is laminated on the upper and lower surfaces of the core insulating layer 1a including the resin columns 13.
[0022]
The insulating layer 1b laminated on the upper and lower surfaces of the core insulating layer 1a is made of a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin, has a thickness of 10 to 80 μm, and has a diameter from the upper surface to the lower surface of each layer. Has a through hole 3 of 20 to 100 μm. The insulating layer 1 b is for providing an insulating interval for wiring the wiring conductors 2 at high density, and penetrates the upper and lower wiring conductors 2 by a copper film formed on the inner wall of the through hole 3. By electrically connecting via the conductor 3a, high-density wiring can be formed three-dimensionally.
[0023]
Such an insulating layer 1b is formed by employing a well-known doctor blade method, and is formed of an uncured thermosetting resin film serving as the insulating layer 1b and the upper and lower surfaces of the core insulating layer 1a on which the wiring conductor 2 is applied. The through-hole 3 is formed by laser processing such as carbon dioxide gas laser or UV laser / excimer laser, and the wiring conductor 2 is further formed on the insulating layer 1b. After the formation of the insulating layer 3a, the upper insulating layer 1b is similarly stacked by sequentially stacking.
[0024]
The insulating layer 1b is formed, for example, by kneading a mixture obtained by adding a solvent or the like to an epoxy resin and a thermoplastic resin / elastomer / inorganic insulating filler to obtain a liquid varnish. It is formed into a film by coating on it and drying at a temperature of 60 to 100 ° C. The dried film to be the insulating layer 1b can be easily stored by laminating a polyethylene sheet on the upper surface of the film and winding it up in a roll. Further, the thickness of the film can be freely set, but is preferably in the range of 20 to 100 μm from the viewpoint of insulation.
[0025]
The wiring conductor 2 and the through conductor 3a are roughened by immersing the surface of the insulating layer 1b and the inside of the through hole 3 in a roughening solution such as an aqueous solution of permanganate or the like. And then immersed in an electroless copper plating solution composed of copper sulfate, Rossell salt, formalin, sodium EDTA, a stabilizer, etc. for about 30 minutes. To deposit about 1 to 2 μm of electroless copper plating, and then deposit a plating-resistant resin layer on the electroless copper plating, and apply electrolytic copper plating to the pattern shape of the wiring conductor 2 by exposure and development. And an electrolytic copper plating solution composed of sulfuric acid, copper sulfate pentahydrate, chlorine, brightener, etc. 2 After applying electrolytic copper plating to the opening by immersing for several hours while applying a current, a plating-resistant resin layer is peeled off with sodium hydroxide, and the plating-resistant resin layer is exposed by peeling. It is formed by removing the electrolytic copper plating by etching with a sulfuric acid-based aqueous solution such as sulfuric acid / hydrogen peroxide solution, and then removing the electroless copper plating layer.
[0026]
The thickness of the wiring conductor 2 and the through conductor 3a is preferably 3 μm or more from the viewpoint of transmitting a high-speed signal. When the wiring conductor 2 and the through conductor 3a are formed on the insulating layer 1b, the thickness of the wiring The thickness is preferably 50 μm or less in order not to cause a large stress to remain in the conductor 2 and the through conductor 3a and to make it difficult for the wiring conductor 2 and the through conductor 3a to be separated from the insulating layer 1b.
[0027]
A part of the wiring conductor 2 formed on the mounting part 7a of the electronic component on one outermost layer surface of the insulating layer 1b is joined to each electrode of the electronic component 7 via a conductor bump 9 made of, for example, lead-tin. The electrode pad 4 and the lead wire 5 for connection of the electronic component to be formed are formed, and a part of the wiring conductor 2 formed on the surface of the other outermost layer of the insulating layer 1b is connected to each electrode ( (Not shown) via a conductor bump 9 made of, for example, lead-tin.
[0028]
The exposed surfaces of the electrode pads 4 and the lead wires 5 have good wettability with solder and excellent corrosion resistance in order to prevent their oxidative corrosion and improve the connection with the conductor bumps 9. A plating layer such as nickel or gold is applied.
[0029]
The electrode pad 4 formed on the mounting portion 7a of the electronic component 7 has a diameter of 50 to 300 μm, has a multipoint lattice shape arranged in a plurality of rows at equal intervals, and has a central electrode of the mounting portion 7a. The pad 4b and the electrode pad 4b on the center side include a first row of electrode pads 4a arranged on the most peripheral side. Further, the lead wire 5 is formed so as to be attached from the mounting portion 7a toward the peripheral side of the insulating substrate 1, is connected to each of the electrode pads 4b, and is the most peripheral side from the central electrode pad 4b of the mounting portion 7a. It is drawn out to a region outside the arranged first row of electrode pads 4a.
[0030]
Then, in the wiring board 6 of the present invention, the lead wire 5 is formed from the mounting portion 7a toward the peripheral side of the insulating substrate 1, is connected to each electrode pad 4, and extends from the electrode pad 4b on the center side of the mounting portion. Are connected to the lower layer wiring conductor 2a via the through conductors 3a in the regions just below the electrode pad 4b and outside the first row of electrode pads 4a arranged on the most peripheral side, respectively. The portion is drawn to a region outside the first row of electrode pads 4a so as to overlap the first row of electrode pads 4a in plan view. This is important in the present invention.
[0031]
According to the wiring board 6 of the present invention, the lead wire 5 is formed from the mounting portion 7a toward the peripheral side of the insulating substrate 1, is connected to each electrode pad 4, and extends from the electrode pad 4b on the center side of the mounting portion 7a. Are connected to the lower layer wiring conductor 2a via the through conductors 3a in the regions just below the electrode pad 4b and outside the first row of electrode pads 4a arranged on the most peripheral side, respectively. Since the portion is drawn out to a region outside the first row of electrode pads 4a so as to overlap with the first row of electrode pads 4a in plan view, the lead wire 5 is separated from the first row of electrode pads 4a by an interval. Irrespective of this, the electrode pads 4a can be drawn out to the region outside the first row of electrode pads 4a. The interval becomes narrow In case, or it becomes impossible drawer lead wire 5, the width of the lead-out wire 5 is never transmission loss of the increases and the signal is the electrical resistance of the lead line by thinning-miniaturization increases. Further, since the lead wire 5 is drawn to a region outside the first row of electrode pads 4a so that a part of the lower wiring conductor 2a overlaps the first row of electrode pads 4a in plan view, A lead wire 5 wider than the interval between the electrode pads 4a in one row can be linearly drawn out of the electrode pad 4b on the center side of the mounting portion 7a to the outside of the electrode pad 4a in the first row. The electrical resistance of the lead wire 5 does not increase and the signal transmission loss does not increase.
[0032]
The through-hole 3a formed in the outermost insulating layer 1b and directly above the electrode pad 4b is provided with a through conductor 3b formed on the inner peripheral wall by plating, and the inside thereof is similar to the insulating layer 1b. Filled with resin. An electrode pad 4 electrically connected to the through conductor 3b is formed directly above the through hole 3a. Alternatively, the through hole 3a may be filled with plating for forming the through conductor 3b, and the surface thereof may be used as the electrode pad 4.
[0033]
Further, in the wiring board 6 of the present invention, it is preferable that the width of the lower wiring conductor 2 a be equal to or larger than the width of the lead wire 5 on the peripheral side of the insulating substrate 1 from the first row of electrode pads 4 a. By setting the width of the lower layer wiring conductor 2a to be equal to or greater than the width of the lead line 5 on the peripheral side of the insulating substrate 1 from the electrode pad 4a of the first row, the lead line 5 is connected to the electrode pad 4a of the first row on the surface of the wiring board 1 The electrical resistance of the lead wire 5 can be greatly reduced as compared with the case where the wire is made thinner so as to pass through the gap between the wires, and as a result, the wiring board 6 with smaller signal transmission loss can be obtained.
[0034]
In the lead wire 5, as shown in the partial plan view of FIG. 2, portions other than the lower layer wiring conductor 2a are formed on the surface of the insulating base 1. Further, in this example, the case where the lower wiring conductor 2a is formed with the lead wire 5 formed on the surface of the insulating base 1 and one insulating layer 1b separated from each other is shown. Alternatively, the lower wiring conductor 2a may be formed by separating the lead wire 5 formed on the surface of the insulating base 1 from two or more insulating layers 1b. Further, the lower wiring conductor 2a may be formed on the plurality of insulating layers 1b.
[0035]
The through conductor 3a for connecting the electrode pad 4a to the lower layer wiring conductor 2a and the lead wire 5 to the lower layer wiring conductor 2a is a predetermined conductor when the wiring conductor 2 and the through conductor 3a are formed on the insulating layer 1b. It may be formed at a position.
[0036]
Then, a part of the lead wire 5 formed outside the mounting portion 7a is replaced with the through conductor 3a and the wiring conductor 2 formed on the insulating layer 1b, and the through-hole conductor 12 and the wiring conductor 2 formed on the core insulating layer 1a. Is electrically connected to an electrode pad for connection to an external electric circuit formed on the other surface of the wiring board 6 through the wiring board 6, thereby forming the wiring board 6 of the present invention.
[0037]
Thus, according to the wiring board 6 of the present invention, even if the number of electrode pads 4 increases, wiring is not impossible, and the wiring board 6 capable of high-density wiring can be obtained. Further, since it is not necessary to make the width of the lead wire 5 finer and thinner between the electrode pads 4a in the first row, a wiring that does not increase the electrical resistance of the lead wire 5 and lower the signal transmission characteristics. The substrate 6 can be used.
[0038]
Note that the wiring board 6 of the present invention is not limited to the above-described embodiment, and various changes can be made without departing from the gist of the present invention. Although the wiring conductors 2 are formed on the upper and lower surfaces of the core insulating layer 1a and the wiring conductors 2 are formed on the insulating layer 1b, the insulating layer 1b may be stacked on only one surface of the core insulating layer 1a. Further, in the above-described example, the insulating substrate 1 is formed by laminating the insulating layer 1b on the core insulating layer 1a. However, the insulating substrate 1 may be configured only by the core insulating layer 1a.
[0039]
Next, the electronic device 8 of the present invention mounts the electronic component 7 on the mounting portion 7a of the electronic component 7 of the wiring board 6, and connects each electrode of the electronic component 7 and each corresponding electrode pad 4 to the conductor bump 9 It is formed by being electrically connected via a.
[0040]
The conductive bump 9 is formed on the electrode pad 4 from a conductive material such as a lead-tin-tin-zinc-tin-silver-bismuth alloy. Such a conductive bump 9 is formed by a method described below. First, a solder resist layer 14 having an opening on the electrode pad 4 is applied to the surface of the wiring board 6 by using a conventionally known screen printing method. The solder resist layer 14 has a thickness of 10 to 50 μm. For example, a mixture of a photosensitive resin such as an acrylic-modified epoxy resin and an initiator contains 30 to 70% by weight of an inorganic powder filler such as silica or talc. It is made of an insulating material and has a function of preventing adjacent electrode pads 4 from being electrically short-circuited by the conductor bumps 9 and improving a bonding strength between the electrode pads 4 and the insulating substrate 1. Next, when the conductor bumps 9 are, for example, solder made of lead-tin, the solder paste made of lead-tin is filled by screen printing on the electrode pads 4 where the openings of the solder resist layer 14 are exposed, and the solder paste is passed through a reflow furnace. As a result, a hemisphere is fixedly formed on the electrode pad 4. If a metal having good conductivity and excellent corrosion resistance, such as nickel or gold, is applied to the surface of the electrode pad 4 exposed on the surface of the wiring board 6 by plating to a thickness of 1 to 20 μm, the exposed electrode is exposed. The oxidation corrosion of the pad 4 can be effectively prevented, and the connection between the electrode pad 4 and the conductor bump 4 can be made good.
[0041]
Thereafter, the respective electrodes of the electronic component 7 are bonded to the electrode pads 4 via the conductor bumps 9 to mount the electronic component 7, and the wiring board 6 and the electronic component 7 are bonded and fixed with an underfill material 15. An electronic device 8 is formed by sealing the electronic component 7 with a lid or a potting resin (not shown), and an electrode pad of the wiring board 6 opposite to the mounting portion 7a of the electronic component 7 is connected to a wiring conductor ( (Not shown), the electronic device 8 of the present invention is mounted on an external electric circuit board.
[0042]
The solder resist layer 14 is formed by applying an uncured resin film composed of a photosensitive resin, a photoinitiator, and an inorganic powder filler or an uncured resin varnish composed of a thermosetting resin and an inorganic powder filler, or by applying an uncured resin. After laminating the film, an opening is formed by exposure and development, and this is applied by UV curing and heat curing.
[0043]
Thus, according to the electronic device 8 of the present invention, the electronic component 7 is mounted on the mounting portion 7a of the wiring board 6, and each connection terminal of the electronic component 7 and each corresponding electrode pad 4 are electrically connected. Thus, an electronic device having high-density wiring and excellent signal transmission characteristics can be provided.
[0044]
It should be noted that the wiring board and the electronic device of the present invention are not limited to the above-described embodiments, and it is needless to say that various changes can be made without departing from the scope of the present invention.
[0045]
【The invention's effect】
According to the wiring board of the present invention, the lead wire is formed from the mounting portion toward the peripheral side of the insulating substrate, connected to each electrode pad, and from the electrode pad on the center side of the mounting portion directly below the electrode pad and In the region outside the first row of electrode pads arranged on the most peripheral side, they are connected to the lower layer wiring conductors via the through conductors, respectively, and are drawn out to the region outside the first row of electrode pads. In addition, the lead lines can be drawn out to a region outside the first row of electrode pads irrespective of the interval between the first row of electrode pads. As a result, the electrode pads are formed at a high density and are arranged on the most peripheral side. Even if the distance between the first row of electrode pads is reduced, it is not possible to draw out the lead line, or the width of the lead line becomes thinner and finer, and the electrical resistance of the lead line becomes larger. Never transmission loss is increased. In addition, since the lead line is drawn to a region outside the first row of electrode pads so that a part of the lower layer wiring conductor overlaps the first row of electrode pads in plan view, the first row of electrode lines is drawn. A lead line wider than the interval between the pads can be drawn linearly from the electrode pad on the center side of the mounting portion to the outside of the first row of electrode pads. As a result, the electrical resistance of the lead line increases and the signal Transmission loss does not increase.
[0046]
Further, according to the wiring board of the present invention, since the width of the lower-layer wiring conductor is set to be equal to or larger than the width of the lead from the first row of electrode pads to the periphery of the insulating substrate, the lead is formed on the surface of the wiring board by the electrode. The electrical resistance of the lead wire can be greatly reduced as compared with the case where the wire is drawn out by making the wire thinner so as to pass between the pads, and as a result, a wiring board with a small signal transmission loss can be obtained.
[0047]
According to the electronic device of the present invention, an electronic component is mounted on the mounting portion of the wiring board, and each connection terminal of the electronic component is electrically connected to each corresponding electrode pad. An electronic device having high density and excellent signal transmission characteristics can be provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating an example of an embodiment of a wiring board and an electronic device of the present invention.
FIG. 2 is an enlarged plan view of a main part of the wiring board of the present invention.
[Explanation of symbols]
1 ... Insulating substrate
1a ... core insulating layer
1b ... Insulating layer
2 Wiring conductor
2a ······ Lower wiring conductor
3 ... Through conductor
3a ... Through-hole
4 ... Electrode pad
4a... First row of electrode pads
4b ····· Center electrode pad
5 Leader line
6 Wiring board
7 Electronic parts
8 Electronic device

Claims (3)

複数の絶縁層を積層して成る絶縁基板の主面上の所定領域に設けられた電子部品の搭載部と、該搭載部内の周辺側に前記電子部品の接続端子に対応して複数列に略等間隔で配列された電極パッドと、前記搭載部より前記絶縁基板の周辺側に向かって形成され、前記各電極パッドに接続されるとともに前記搭載部の中央側の電極パッドからは該電極パッドの直下および最も周辺側に配列された第1列の電極パッドの外側の領域でそれぞれ貫通導体を介して下層の配線導体に接続されて、該配線導体の一部が平面視で前記第1列の電極パッドと重なるようにして前記第1列の電極パッドの外側の領域へ引き出されている引き出し線とを具備することを特徴とする配線基板。A mounting portion of an electronic component provided in a predetermined region on a main surface of an insulating substrate formed by laminating a plurality of insulating layers, and a plurality of rows on a peripheral side in the mounting portion corresponding to connection terminals of the electronic component. Electrode pads arranged at equal intervals, formed from the mounting portion toward the peripheral side of the insulating substrate, connected to the respective electrode pads, and from the electrode pad on the center side of the mounting portion to the electrode pads. Immediately below and in a region outside the first row of electrode pads arranged on the most peripheral side, each is connected to a lower layer wiring conductor via a through conductor, and a part of the wiring conductor is arranged in the first row in a plan view. A lead line extending to an area outside the first row of electrode pads so as to overlap with the electrode pads. 前記下層の配線導体の幅を前記第1列の電極パッドから前記絶縁基板の周辺側における前記引き出し線の幅以上としていることを特徴とする請求項1記載の配線基板。2. The wiring board according to claim 1, wherein a width of the lower layer wiring conductor is equal to or larger than a width of the lead line from the first row of electrode pads to a periphery of the insulating substrate. 3. 請求項1または請求項2記載の配線基板の前記搭載部に電子部品を搭載し、該電子部品の各接続端子とこれに対応する各前記電極パッドとを電気的に接続していることを特徴とする電子装置。An electronic component is mounted on the mounting portion of the wiring board according to claim 1, and each connection terminal of the electronic component is electrically connected to each of the corresponding electrode pads. Electronic device.
JP2002216140A 2002-07-25 2002-07-25 Circuit board and electronic device using the same Pending JP2004063530A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019186479A (en) * 2018-04-16 2019-10-24 ルネサスエレクトロニクス株式会社 Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019186479A (en) * 2018-04-16 2019-10-24 ルネサスエレクトロニクス株式会社 Semiconductor device
JP7001530B2 (en) 2018-04-16 2022-01-19 ルネサスエレクトロニクス株式会社 Semiconductor device

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