JP2004062662A - Electronic device and control method for the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce unnecessary power consumption by a differential input buffer in an I/O buffer while a controller performs data transmission. <P>SOLUTION: The USB controller 16 controls communication with another device according to USB standards. The I/O buffer 33 has output buffers 41A and 41B for outputting data transmitted from the USB controller 16 to another device, and the differential input buffer 43 for inputting a differential signal of data received from another device into the USB controller 16. A buffer control circuit 31 has a logic circuit for stopping the operation of the differential input buffer 43 with an H-level signal SUSP, while the USB controller 16 sends L-level signals DPOEZ and DMOEZ enabling data output to the output buffers 41A and 41B, when receiving the signals. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an electronic device including a controller for transmitting serial data as a differential signal to another electronic device and an I / O buffer, and a control method therefor, and more particularly, to an I / O based on USB (Universal Serial Bus). The present invention relates to a buffer control circuit and a buffer control method for reducing power consumption in a buffer.
[0002]
[Prior art]
2. Description of the Related Art In recent years, USB (Universal Serial Bus) has been frequently used in electronic devices such as personal computers in order to increase the degree of freedom of expandability of peripheral devices. USB is a serial interface standard that can be commonly used for communication with various USB-compatible devices such as a keyboard, a mouse, a camera, a printer, and a modem. By using this USB, the connector prepared for each peripheral device can be integrated into the USB connector, and the price of the personal computer can be reduced and the degree of freedom of expandability can be increased.
[0003]
In order for the electronic device to be a USB-compatible device, at least a USB controller for controlling communication with the peripheral device and an I / F for buffering data communicated between the USB controller and the peripheral device and the like. It is necessary to mount a combination with an / O (Input / Output) buffer on the electronic device. This is shown in FIG.
[0004]
The I / O buffers shown in FIG. 5 include output buffers 101A and 101B for outputting data transmitted from the USB controller to peripheral devices, input buffers 102A and 102B for inputting data received from peripheral devices to the USB controller, And a differential input buffer 103 for inputting a differential signal of data received from a peripheral device to a USB controller.
[0005]
Further, between the USB controller and the I / O buffer, data output signals DPOUT and DMOUT, data output control signals DPOEZ (and DPOE #), DMOEZ (and DMOE #), data input signals DPIN and DMIN, and differential input Signal lines for transmitting various signals such as a signal RCV, a USB suspend notification signal USB_SUS, a USB function non-use notification signal SYS_SUS, and a differential input buffer control signal SUSP are provided.
[0006]
Generally, from the viewpoint of reducing wasteful power consumption in the I / O buffer, measures are taken to prevent the output buffer and the differential input buffer in the I / O buffer from operating when the USB function is not used. .
[0007]
In the example of FIG. 5, the signal USB_SUS indicates the H level (that is, the USB controller itself is in the suspend mode), or the signal SYS_SUS indicates the H level (that is, the system does not use the USB function). ), The control signals DPOE #, DMOE #, and SUSP go high through the buffer control circuit including the OR circuit 112 and the OR circuits 111A and 111B, and the output buffers 101A and 101B and the differential input buffer 103 Are stopped respectively. The input buffers 102A and 102B are connected to a serial bus (D ⁺ , D ⁻ If there is a change in the connection state of the USB port at the end of ()), it is necessary to detect this and notify the USB controller, and the operation is not stopped.
[0008]
A technique similar to the above is also disclosed in Japanese Patent Application Laid-Open No. H11-205412. This document discloses a configuration in which a differential input buffer is turned on / off in accordance with the status of a USB port, and a serial bus (D ⁺ , D ⁻ 3) discloses a technique for reducing the useless power consumption by powering down the differential input buffer and stopping its operation during a period in which data transfer is not performed via the above.
[0009]
As described above, in the related art, during a period in which the USB function is not used or a period in which a peripheral device is not connected to the USB port of the electronic device, useless power consumption due to the differential input buffer or the like can be reduced.
[0010]
[Problems to be solved by the invention]
By the way, the above-mentioned differential input buffer is connected to the serial bus (D ⁺ , D ⁻ ) Performs differential detection of two signals (corresponding to received packets) having different phases and outputs the signals to the USB controller side, and needs to operate only when the USB controller performs data reception. There is no. Therefore, during the period when the USB controller is transmitting data to the peripheral device via the I / O buffer, it is not necessary to operate the differential input buffer.
[0011]
However, in the related art, no measure is taken to stop the operation of the differential input buffer during the data transmission. That is, during that period, power is wasted by the differential input buffer. This situation will be described with reference to the timing chart of FIG. 6 (corresponding to the configuration example of FIG. 5).
[0012]
When the USB controller performs data transmission, the data output control signals DPOEZ and DMOEZ change from H level to L level (that is, DPOE # and DMOE # change from H level to L level).
[0013]
At this time, the output buffers 101A and 101B enter an operating state, and the signals DPOUT and DMOUT, which are data (packets), are sent to the I / O buffer, and the signals DOUT are output. ⁺ , D ⁻ Is output from the I / O buffer. On the other hand, the input buffers 102A and 102B are in operation, and output data as signals DPIN and DMIN from the I / O buffer. The signal USB_SUS (and the signal SYS_SUS) is at L level (inactive), and the signal SUSP is also at L level (inactive). Therefore, the differential input buffer 103 is in the operating state and outputs the signal RCV.
[0014]
As described above, conventionally, during the period in which the USB controller is performing data transmission, the differential input buffer in the I / O buffer is in an operating state, so that there is a problem that power is wasted.
[0015]
The present invention has been made in view of the above circumstances, and an electronic device capable of reducing wasteful power consumption by a differential input buffer in an I / O buffer during a period when a controller is performing data transmission, and a control thereof. The aim is to provide a method.
[0016]
[Means for Solving the Problems]
The electronic device according to the present invention transmits data as a differential signal, a controller that controls communication with another electronic device, and an output buffer for outputting data transmitted from the controller to another electronic device. An I / O buffer having a differential input buffer for inputting a differential signal of data received from another electronic device to the controller, and a signal for enabling output of data from the controller to the output buffer are provided. And a logic circuit for receiving the signal and stopping the operation of the differential input buffer while the signal is being sent.
[0017]
Further, in the control method of an electronic device according to the present invention, a controller that transmits data as a differential signal, controls communication with another electronic device, and outputs data transmitted from the controller to another electronic device. And a differential input buffer for inputting a differential signal of data received from another electronic device to the controller. The operation of the differential input buffer is stopped while a signal for enabling data output is sent from the controller to the output buffer.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0019]
FIG. 1 shows an overall configuration of an electronic device according to an embodiment of the present invention.
[0020]
This electronic apparatus is, for example, a notebook-type or sub-notebook-type personal computer that can be driven by a battery, and includes a computer main body and an LCD panel unit that is openably and closably attached to the computer main body. This computer has a built-in battery 22 and is configured to be operable with electric power from the built-in battery 22.
[0021]
The computer can also receive power from an external power supply such as an AC commercial power supply via the AC adapter 23. When power is supplied from an external power source, the power from the external power source is used as an operating power source for the computer. At this time, charging of the built-in battery 22 is automatically performed by the power from the external power supply. When the AC adapter 23 is removed or the breaker of the AC commercial power supply is turned off, the power from the built-in battery 22 is used as the operating power supply for the computer.
[0022]
As shown, three types of buses, namely, a host bus 1, a PCI bus 2, and an ISA bus 3, are provided on a system board of the computer. Further, on the system board, a CPU 11, a host-PCI bridge device 12, a main memory 13, a VGA controller 14, a video RAM (VRAM) 15, a USB controller 16, a buffer control circuit 31, and an I / O (Input / Output) buffer 33, a PCI-ISA bridge device 17, a BIOS-ROM 18, a HDD 19, an embedded controller (EC: Embedded Controller) 20, a power supply controller 21, and the like.
[0023]
The CPU 11 executes a program loaded in the main memory 13 to execute operation control and data processing of the entire system. The main memory 13 is a memory device that stores an operating system, a device driver, an application program to be executed, processing data, and the like, and includes a plurality of DRAMs. The main memory 13 is connected to the host-PCI bridge device 12 via a dedicated memory bus having a 32-bit or 64-bit data bus.
[0024]
The host-PCI bridge device 12 is a bridge LSI that connects the host bus (CPU bus) 1 and the PCI bus 2, and functions as one of the bus masters of the PCI bus 2. The host-PCI bridge device 12 has a function of bidirectionally converting a bus cycle including data and addresses between the host bus 1 and the PCI bus 2, and a function of controlling access to the main memory 13 via the memory bus. And so on.
[0025]
The VGA controller 14 is one of the PCI devices, and controls an LCD or an external CRT to display display data drawn on the VRAM 15 on them.
[0026]
The USB controller 16 is also realized as one of the PCI devices, and controls communication with a USB device 35 connected to a USB port (USB connector) 34 provided in the computer body based on the USB standard. The USB controller 16 is realized by, for example, a one-chip LSI.
[0027]
The I / O buffer 33 is a semiconductor buffer that buffers data transmitted and received between the USB controller 16 and the USB device 35 connected to the USB port 34. The details will be described later.
[0028]
The buffer control circuit 31 is a circuit that performs control for reducing unnecessary power consumption in the I / O buffer 33 based on a signal obtained from the USB controller 16. The details will be described later.
[0029]
The I / O buffer 33 and the buffer control circuit 31 may be configured to be built in the USB controller 16.
[0030]
The PCI-ISA bridge device 17 is a bridge LSI that connects the PCI bus 2 and the ISA bus 3. The ISA bus 3 is connected with a BIOS-ROM 18, an HDD 19, an EC 20, and the like.
[0031]
The BIOS-ROM 18 stores a system BIOS (Basic Input / Output System), and is configured by a flash memory so that a program can be rewritten. The system BIOS systematizes function execution routines for accessing various hardware in the system.
[0032]
The system BIOS includes an IRT routine executed when the system is powered on, a group of BIOS drivers for controlling various hardware, and the like. Each BIOS driver includes a plurality of function execution routine groups corresponding to the functions for providing a plurality of functions for hardware control to an operating system or an application program.
[0033]
The BIOS-ROM 18 also stores a system management program such as a suspend / resume routine. When the system is powered off, the suspend / resume routine saves system status such as the status of CPU registers and peripheral LSIs in the main memory 13 and powers off most of the devices other than the main memory 13 or the system status. And a suspend process of saving the contents of the main memory in the HDD 19 and turning off the system power. Thereafter, when the system power is turned on, the suspend / resume routine uses the information in the main memory 13 or the HDD 19 to restore the system state.
[0034]
The EC 20 is a controller for controlling the additional functions of the system, a heat control function for controlling the rotation of the cooling fan according to the temperature around the CPU, etc., and various states of the system by turning on LEDs and beeping sounds. It has an LED / beep sound control function for notifying the user, a power supply sequence control function for controlling on / off of the system power supply in cooperation with the power supply controller 21, and the like.
[0035]
The power controller 21 controls a power circuit to supply power to each unit in the computer, and includes a one-chip microcomputer. The power controller 21 controls the supply and cutoff of power in response to an on / off operation of a power switch (P-SW), an LCD panel opening / closing operation, and the like. Note that even in the system suspend state, the operating power is supplied to the EC 20 and the power controller 21.
[0036]
FIG. 2 shows a circuit configuration in the USB controller 16.
[0037]
The USB controller 16 includes a host bus interface 61, a memory controller 62, a configuration register 63, a USB processing unit (microcomputer) 64, a root hub interface 65, and a root hub 66.
[0038]
The host bus interface 61 interfaces between the inside of the USB controller 16 and the PCI bus (host side).
[0039]
The memory controller 62 is controlled by the USB processing unit 64, and accesses the main memory 13 (FIG. 1) via the host bus interface 61 to read / write data.
[0040]
The configuration register 63 is controlled by the USB processing unit 64 and stores setting information related to a USB function (USB device) defined by a system BIOS or the like in the BIOS-ROM 18 (FIG. 1). For example, when setting information instructing that the system BIOS does not use the USB function is stored in the configuration register 63, the USB function non-use notification signal SYS_SUS is set to the H level (active) when the setting information indicating that the system BIOS does not use the USB function. Output to the / O buffer 33 side.
[0041]
The USB processing unit 64 controls the overall processing operation of the USB controller 16 using an operational register. For example, the USB processing unit 64 controls the host bus interface 61 and the memory controller 62 to read / write data from / to the main memory 13 (FIG. 1) and to write / reference information to / from the configuration register 63. And controls the route hub interface 65 to transmit / receive data to / from the I / O buffer 33 side.
[0042]
Further, the USB processing unit 64 shifts the USB controller 16 from the normal mode to the suspend mode (low power consumption state) when, for example, a state in which there is no data communication by the USB controller 16 has passed for a predetermined time or more. In this case, the USB processing unit 64 outputs the USB suspend notification signal USB_SUS to the I / O buffer 33 side with the signal at the H level (active). When, for example, a signal indicating that a USB device is connected is received from the I / O buffer 33 side, the USB processing unit 64 returns from the suspend mode (low power consumption state) to the normal mode.
[0043]
The root hub interface 65 performs an interface between the USB processing unit 64 and the root hub 66.
[0044]
The root hub 66 transmits and receives data to and from the I / O buffer 33 based on a predetermined synchronization pattern.
[0045]
FIG. 3 shows a configuration of an electronic circuit including the USB controller 16, the buffer control circuit 31, and the I / O buffer 33 in the computer.
[0046]
The I / O buffer 33 transmits data transmitted from the USB controller 16 to a serial bus (D ⁺ , D ⁻ ) Output buffers 41A and 41B for outputting to the upper side (that is, the USB port 34 side to which the USB device 35 is connected), and input buffers 42A and 41A for inputting the data received from the serial bus to the USB controller 16. 42B, and a differential input buffer 43 for inputting a differential signal of data received from the serial bus to the USB controller 16.
[0047]
Between the USB controller 16 and the I / O buffer 33, data output signals DPOUT and DMOUT, data output control signals DPOEZ (and DPOE #), DMOEZ (and DMOE #), data input signals DPIN and DMIN, and differential input A signal line for transmitting a signal related to transmission and reception of data, such as a signal RCV, is provided. These signal lines are connected to the aforementioned root hub 66 (FIG. 3).
[0048]
The data output signals DPOUT and DMOUT are signals corresponding to data (packets) when the USB controller 16 transmits data to the serial bus via the output buffers 41A and 41B, respectively.
[0049]
The data output control signals DPOEZ and DMOEZ are signals for controlling the transmission of the data output signals DPOUT and DMOUT by controlling the operation of the output buffers 41A and 41B via the control signals DMOE # and DMOE #, respectively. is there.
[0050]
The data input signals DPIN and DMIN are signals corresponding to data (packets) when the USB controller 16 receives data from the serial bus via the input buffers 42A and 42B.
[0051]
The differential input signal RCV is a signal output from the differential input buffer 43 to the USB controller 16, and is a signal corresponding to the result of the differential input buffer 43 performing differential detection on data received from the serial bus. is there.
[0052]
A signal line for transmitting a USB suspend notification signal USB_SUS, a USB function non-use notification signal SYS_SUS, and a differential input buffer control signal SUSP is provided between the USB controller 16 and the I / O buffer 33. .
[0053]
The USB suspend notification signal USB_SUS is a signal indicating whether or not the USB controller 16 itself is in a suspend mode (low power consumption state).
[0054]
The USB function non-use notification signal SYS_SUS is a signal indicating whether or not the system instructs not to use the USB function.
[0055]
The differential input buffer control signal SUSP is a signal for controlling the operation (power-on / power-off) of the differential input buffer 43 via a control signal input terminal provided in the differential input buffer 43. The low power consumption operation of the buffer 43 is realized.
[0056]
In the present embodiment, from the viewpoint of reducing wasteful power consumption in the I / O buffer 33, the buffer control circuit 31 for controlling the operations of the output buffers 41A and 41B and the differential input buffer 43 in the I / O buffer 33. Is provided. The buffer control circuit 31 includes OR circuits 51A and 51B, a NAND circuit 52, and an OR circuit 53. With this configuration, the buffer control circuit 31 performs low power consumption control on the I / O buffer 33 as described in (1) to (3) below. It should be noted that the input buffers 42A and 42B do not stop the operation because it is necessary to detect a change in the connection state of the USB port at the end of the serial bus and notify the USB controller of the change.
[0057]
(1) Period during which the USB function is not used (SYS_SUS is at H level)
In this period, signals DPOEZ and DMOEZ are both at H level (inactive), and signal USB_SUS is at L level (inactive).
[0058]
When the signal SYS_SUS is at H level (active), the control signals DPOE # and DMOE # become H level by the OR circuits 51A and 51B, and the operation of the output buffers 41A and 41B is stopped.
[0059]
When the signal SYS_SUS is at the H level (active), the control signal SUSP is at the H level by the OR circuit 53, and the operation of the differential input buffer 43 is stopped.
[0060]
(2) Period during which the USB controller is in the suspend mode (USB_SUS is at H level)
In this period, signals DPOEZ and DMOEZ are both at H level (inactive), and signal SYS_SUS is at L level (inactive).
[0061]
Also, since the signals DPOEZ and DMOEZ are both at the H level, the control signals DPOE # and DMOE # are brought to the H level by the OR circuits 51A and 51B and the operation of the output buffers 41A and 41B is stopped, as in the case of (1). It will be in the state of having done.
[0062]
When the signal USB_SUS is at the H level (active), the control signal SUSP is set to the H level by the OR circuit 53, and the operation of the differential input buffer 43 is stopped.
[0063]
(3) Period during which the USB controller is transmitting data (DPOEZ and DMOEZ are at L level)
During this period, the signal USB_SUS is at the L level (inactive), and the signal SYS_SUS is at the L level (inactive).
[0064]
Also, while data transmission is performed by the signals DPOUT and DMOUT, both the signals DPOEZ and DMOEZ are set to L level (active). At this time, since the signal SYS_SUS is at the L level, the control signals DPOE # and DMOE # are at the L level, and the output buffers 41A and 41B are activated.
[0065]
Since both signals DPOEZ and DMOEZ are at L level, the output of NAND circuit 52 goes to H level and the output of OR circuit 53 goes to H level. That is, the control signal SUSP is set to the H level by the OR circuit 53, and the operation of the differential input buffer 43 is stopped.
[0066]
Next, the operation of the low power consumption control on the I / O buffer 33 will be described with reference to the timing chart of FIG.
[0067]
Now, consider a state in which the USB controller 16 has not yet transmitted data.
[0068]
At this time, the signals DPOUT and DMOUT as data (packets) are not output from the USB controller 16, and the signals DPOEZ and DMOEZ for data output control are at the H level (inactive) (that is, DPOE # and DMOE #). Is H level (inactive)). Therefore, the operation of the output buffers 41A and 41B is stopped, and the signal D is output on the system bus. ⁺ , D ⁻ Is not output.
[0069]
On the other hand, the input buffers 42A and 42B are in an operating state, and the USB controller 16 can input signals DPIN and DMIN as data (packets).
[0070]
The signal USB_SUS (and the signal SYS_SUS) is at L level (inactive), and the signal SUSP is at L level (inactive). Therefore, the differential input buffer 103 is in the operating state and outputs the signal RCV.
[0071]
Here, a case is considered where the USB controller 16 starts data transmission based on a predetermined synchronization pattern.
[0072]
At this time, the USB controller 16 changes the data output control signals DPOEZ and DMOEZ from H level (inactive) to L level (active) (ie, changes DPOE # and DMOE # from H level (inactive) to L level). (Active)). As a result, the output buffers 41A and 41B are in the operating state. Therefore, when the USB controller 16 transmits the signals DPOUT and DMOUT, which are data (packets), the signal D ⁺ , D ⁻ Is output.
[0073]
Further, the input buffers 42A and 42B are in the operating state, and the USB controller 16 can respond to the input of the signals DPIN and DMIN from the input buffers 42A and 42B.
[0074]
Also, since the data output control signals DPOEZ and DMOEZ become L level (active) (the signals DPOE # and DMOE # also become L level (the output buffers 41A and 41B become active)), the logic circuit (the NAND circuit 52 and the The control signal SUSP becomes H level via the OR circuit 53), and the operation of the differential input buffer 43 is stopped.
[0075]
After the USB controller 16 completes the data transmission, each of the above signals returns to the state before the data transmission.
[0076]
As described above, according to the present embodiment, not only during the period when the USB function is not used or during the period when the USB controller is in the suspend mode, but also during the period when the USB controller is performing data transmission, Since the operation of the differential input buffer 103 is controlled by the control unit 31, the useless power consumption of the I / O buffer 33 can be reduced.
[0077]
The present invention is not limited to the above-described embodiment, and can be implemented with various modifications within the scope of the gist. For example, in the above embodiment, the low power consumption control on the I / O buffer connected to the USB controller has been described, but the present invention is not limited to this. That is, the present invention is also applicable to a device corresponding to a serial interface other than USB as long as the I / O buffer includes a differential input buffer.
[0078]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to reduce wasteful power consumption by the differential input buffer in the I / O buffer during the period when the controller is performing data transmission.
[Brief description of the drawings]
FIG. 1 is an exemplary view showing the overall configuration of an electronic apparatus according to an embodiment of the present invention.
FIG. 2 is a diagram showing a circuit configuration in the USB controller shown in FIG. 1;
FIG. 3 is a diagram illustrating a configuration of an electronic circuit including a USB controller, a buffer control circuit, and an I / O buffer illustrated in FIG. 1;
FIG. 4 is a timing chart for explaining an operation of low power consumption control for an I / O buffer.
FIG. 5 is a diagram for explaining a conventional circuit configuration for low power consumption control of an I / O buffer.
FIG. 6 is a timing chart for explaining an operation of a conventional low power consumption control for an I / O buffer.
[Explanation of symbols]
1: Host bus
2. PCI bus
3. ISA bus
11 CPU
12. Host-PCI bridge device
13: Main memory
14 VGA controller
15. Video RAM (VRAM)
16 ... USB controller
17 ... PCI-ISA bridge device
18 ... BIOS-ROM
19 ... HDD
20 ... Embedded controller
21 Power supply controller
22 ... Battery
23… AC adapter
31 ... Buffer control circuit
33 ... I / O buffer
34… USB port
35… USB device
41A, 41B ... output buffer
42A, 42B ... input buffer
43… Differential input buffer
51A, 51B, 53 ... OR circuit
52 ... NAND circuit
61: Host bus interface
62 ... Memory controller
63: Configuration register
64: USB processing unit (microcomputer)
65: Root hub interface
66 ... Root hub

Claims (5)

A controller that transmits data as a differential signal and controls communication with other electronic devices;
An I / O having an output buffer for outputting data transmitted from the controller to another electronic device and a differential input buffer for inputting a differential signal of data received from another electronic device to the controller; An O buffer,
While a signal for enabling the output of data is sent from the controller to the output buffer, a logic circuit that receives the signal and stops the operation of the differential input buffer,
An electronic device comprising: 2. The buffer according to claim 1, wherein the logic circuit stops the operation of the differential input buffer by receiving a signal indicating the state from the controller even while the controller is in a low power consumption state. Control circuit. The logic circuit, even while the controller does not use the interface function with another electronic device, receives a signal indicating the state from the controller and stops the operation of the differential input buffer. The buffer control circuit according to claim 1, wherein 2. The buffer control circuit according to claim 1, wherein the controller and the I / O buffer are based on the Universal Serial Bus standard. A controller that transmits data as a differential signal and controls communication with other electronic devices;
An I / O having an output buffer for outputting data transmitted from the controller to another electronic device and a differential input buffer for inputting a differential signal of data received from another electronic device to the controller; An O buffer,
An electronic device control method comprising:
A method for controlling an electronic device, comprising: controlling to stop operation of the differential input buffer while a signal for enabling data output is sent from the controller to the output buffer.

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