JP2004055939A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device equipped with a unit logic circuit of simple constitution for multiple purposes. <P>SOLUTION: A first input signal is supplied to the source or drain of a first MOSFET and, when a second input signal supplied to the gate is at one level, a signal of the other level of the 1st input signal is outputted from the other drain or source. The first input signal is supplied to the source or drain of a second MOSFET and, when the second input signal supplied to the gate is at the other level, a signal of one level of the first input signal is outputted from the other drain or source. A fixed potential corresponding to one level of the first input signal supplied to the source or drain of a 3rd MOSFET is outputted from the other drain or source when the second input signal supplied to the gate is at the other level. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and more particularly to a technology effective when used in a device having a built-in decoder circuit for selecting a memory cell according to an address signal or selecting a gray scale voltage according to display data.
[0002]
[Prior art]
FIG. 18 is a circuit diagram of a decoder circuit studied prior to the present invention. This decoder circuit uses a NAND (NAND) gate circuit to receive a 4-bit input signal consisting of address signals A0 to A3 and form 16 kinds of decoded output signals such as 0 to F. Each gate circuit NAND includes four pairs of P-channel MOSFETs and N-channel MOSFETs whose gates are connected to the input terminals IN1 to IN4, one of which is exemplarily shown in FIG. The P-channel MOSFETs are connected in parallel with each other, and the N-channel MOSFETs are connected in series with each other. Further, as examples of a decoder circuit used in a liquid crystal driving device, there are JP-A-10-3285 and US Pat. No. 5,719,591.
[0003]
[Problems to be solved by the invention]
In the decoding circuit using the logic gate circuit, when the number of bits of the address signal is N bits, ^N × N × 2 transistors are required, and as the number of bits of the address signal increases, the number of transistors increases exponentially accordingly. In a control driver for a TFT (thin film transistor) liquid crystal display, a gray scale voltage generated by a liquid crystal power generation circuit is selected by a gray scale selection signal according to display data, and is supplied to a liquid crystal panel as a liquid crystal drive voltage. I have.
[0004]
As a gradation selector for selecting the gradation voltage, a tournament type switch tree as shown in FIG. 19 was studied in order to reduce the number of circuit elements. In this circuit, since each switch tree is controlled by a selection signal to select one of, for example, 64 gradation levels to form a liquid crystal drive voltage, the number of MOS transistors can be reduced. However, although the MOS transistor can be suppressed, in order to set the liquid crystal driving voltage terminal to a desired voltage, the ON resistance of the switch from the gradation level voltage generation amplifier to the terminal appears in series for the number of selected bits. That is, when the selection signal consists of 6 bits as in this example, one gradation voltage is selected via six pairs of CMOS switches.
[0005]
FIG. 20 shows a waveform diagram of the liquid crystal drive signal selected by the gradation selector of FIG. As shown in the figure, in the actual liquid crystal panel, the rising waveform becomes dull due to the influence of the ON resistance and the liquid crystal panel resistance in the above-mentioned switch tree in the LSI. In addition, when the size of the liquid crystal display is increased, the period of one frame is shortened, and the blunt rising waveform affects the image quality. Therefore, a reduction in output ON resistance is an essential condition for an LSI capable of increasing the screen size of a liquid crystal panel.
[0006]
An object of the present invention is to provide a semiconductor integrated circuit device provided with a unit logic circuit for a versatile use with a simple configuration. Another object of the present invention is to provide a semiconductor integrated circuit device for a liquid crystal driving device having high display quality and high integration. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0007]
[Means for Solving the Problems]
The outline of a representative one of the inventions disclosed in the present application will be briefly described as follows. A first input signal is supplied to one of a source and a drain of the first MOSFET, and when the second input signal supplied to the gate of the first MOSFET is at one level, the signal of the other level of the first input signal is supplied to the first MOSFET. And a first input signal is supplied to one of the source and the drain of the second MOSFET, and the first input signal is supplied when the second input signal supplied to the gate of the second MOSFET is at the other level. A signal of one level of the signal is output from the other of the source and the drain of the second MOSFET, and a predetermined potential corresponding to one level of the first input signal applied to one of the source and the drain of the third MOSFET is supplied to the third MOSFET. When the second input signal supplied to the gate is at the other level, the source or drain of the third MOSFET is Is output from the in the other constituting the unit logic circuits.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a circuit diagram showing one embodiment of a unit logic circuit according to the present invention. This embodiment is directed to an AND gate circuit. That is, an output signal of logic 1 is formed when both input signals are logic 1 (high level), and an output signal of logic 0 is formed when one of the input signals is logic 0 (low level). . Although the logic circuit of this embodiment is not particularly limited, it is directed to a tournament logic type decoder circuit to be described later, and two input signals corresponding to the selection signal (positive or negative) complementary to the upper node. , And the output terminal is a lower node.
[0009]
In the case of adopting the positive logic in which the high level is set to logic 1 as described above, a P-channel selection signal transmission PMOS Q1 is connected between an upper node as one input terminal and an output node corresponding to the output terminal. , N-channel non-selection signal transmission NMOS Q2 are provided in parallel. An N-channel non-selected lower node fixed NMOS Q3 is provided between the ground potential of the circuit corresponding to logic 0 (non-selection level) and the output node. The gates of the P-channel MOSFET Q1 and the N-channel MOSFET Q3 are commonly connected and used as the other input terminal, to which a selection negative signal is supplied. The gate of the N-channel MOSFET Q2 is used as the other input terminal, and is supplied with a selection positive signal. Here, the selection negative signal is a negative signal among the complementary signals that are set to a low level at the time of selection, and the selection positive signal is a positive signal among the complementary signals that are set to a high level at the time of selection.
[0010]
In the figure, the unit logic circuit composed of the MOSFETs Q1 to Q3 is indicated by a simplified circuit symbol in the tournament logic type decoder circuits shown in FIGS. 6, 7, 13, 14, and 16 below. As described above, a switch, upper nodes and circuit nodes provided at both ends thereof, and switch selection signals P (positive) and N (negative) are represented.
[0011]
In FIG. 1, when one input signal supplied to the upper node is a logic 1 high level, the other input signal, the selection positive signal is a logic 1 high level and the selection negative signal is a logic 0 low level, the selection is made. The P-channel MOSFET Q1 is turned on by the low level of the negative signal, and the high level of logic 1 of one input signal supplied to the upper node is output to the output node. At this time, the N-channel MOSFET Q2 is also in the ON state due to the high level of the logic 1 of the selection positive signal, but the high level of the upper node is shifted to the output node by the threshold voltage Vth of the MOSFET Q2 and transmitted to the output node. Therefore, it is considered that the transmission of the high level of the upper node to the lower node is performed by the P-channel MOSFET Q1.
[0012]
In FIG. 1, when one input signal supplied to the upper node is a logic 1 high level, the other input signal, the selection positive signal is a logic 1 low level and the selection negative signal is a logic 0 high level, the selection is made. The high level of the negative signal turns off the P-channel MOSFET Q1, and the low level of the selected positive signal turns off the N-channel MOSFET Q2. At this time, the N-channel MOSFET Q3 is turned on by the high level of the selection negative signal, and the low level is transmitted to the lower node. That is, an output signal corresponding to logic 0 is formed between the upper node and the lower node while preventing the floating state of the output node due to the disconnection of both the MOSFETs Q1 and Q2 due to the OFF state.
[0013]
In FIG. 1, when one input signal supplied to the upper node is a logic 0 low level, the other input signal, a selection positive signal is a logic 1 high level and a selection negative signal is a logic 0 low level, The high level of the signal turns on the N-channel MOSFET Q2, and outputs a low level of logic 0 of one input signal supplied to the upper node to the output node. At this time, the P-channel MOSFET Q1 is also in the ON state due to the logic 0 low level of the selection negative signal, but the low level of the upper node is shifted by the threshold voltage Vth of the MOSFET Q1 and transmitted to the output node. Therefore, it is considered that the low level of the upper node is transmitted to the lower node by the P-channel MOSFET Q2.
[0014]
In FIG. 1, when one input signal supplied to the upper node is a logic 0 low level, the other input signal, the selection positive signal is a logic 1 low level, and the selection negative signal is a logic 0 high level, the selection negative signal is low. The high level of the signal turns off the P-channel MOSFET Q1, and the low level of the selection positive signal turns off the N-channel MOSFET Q2. At this time, the N-channel MOSFET Q3 is turned on by the high level of the selection negative signal, and the low level is transmitted to the lower node. That is, an output signal corresponding to logic 0 is formed between the upper node and the lower node while preventing the floating state of the output node due to the disconnection of both the MOSFETs Q1 and Q2 due to the OFF state.
[0015]
Thus, an AND logic circuit can be realized by combining three MOSFETs. When an AND gate circuit is formed by MOSFETs, a combination of a NAND gate circuit and an inverter circuit is used. Therefore, a 2-input circuit requires a total of 4 + 2 MOSFETs. In addition, since the signal is transmitted by the two logic stages of the NAND gate circuit and the inverter circuit, the signal propagation delay time becomes long. On the other hand, in the AND gate circuit of this embodiment, the circuit can be constituted by the three MOSFETs, and furthermore, the signal transmission is performed by the signal propagation delay time between the gate and the source of the MOSFET, so that the high speed operation is possible. Become.
[0016]
Strictly speaking, since an inverter circuit is required to generate the selection negative signal and the selection positive signal, a total of five MOSFETs are required. However, in the tournament logic type decoder circuit described later, the selection positive signal and the selection negative signal can be used in common for a plurality of logic stages, and therefore, in such a tournament logic type decoder circuit, substantially one logic circuit is used. Can be regarded as being composed of three.
[0017]
FIG. 2 is a circuit diagram showing another embodiment of the logic circuit according to the present invention. This embodiment is directed to an OR gate circuit. That is, an output signal of logic 0 is formed when both input signals are logic 0 (low level), and an output signal of logic 1 is formed when one of the input signals is logic 1 (high level). . As in FIG. 1, the two input signals are selection signals (positive and negative) complementary to the upper node, and the output terminal is the lower node.
[0018]
In the circuit of this embodiment, a P-channel non-selection signal transmission PMOS Q4 and an N-channel selection signal transmission NMOS Q5 are provided between an upper node as one input terminal and an output node corresponding to the output terminal. Provided in a side-by-side configuration. Further, a PMOS Q6 for fixing the lower node when the P channel is not selected is provided between the power supply voltage VDD corresponding to logic 1 (non-selection level) and the output node. The gates of the N-channel MOSFET Q5 and the P-channel MOSFET Q6 are commonly connected and used as the other input terminal, to which a selection positive signal is supplied. The gate of the P-channel MOSFET Q4 is used as the other input terminal, and is supplied with a selection negative signal.
[0019]
In this embodiment, the logic level and the conductivity type of the MOSFET are opposite to those of the embodiment of FIG. 1, and one input signal of the upper node is logic 0 and the other input signal is logic 0, that is, the selected positive signal is high. When the selection negative signal is at the low level, logic 0 of the upper node is transmitted to the output node through MOSFET Q5. In other combinations, the logic 1 of the input node is transmitted through the P-channel MOSFET Q1 to the lower node that is the output, or the logic 1 of the power supply voltage VDD is transmitted through the N-channel MOSFET Q6 to the lower node that is the output.
[0020]
The circuit of the embodiment in FIG. 2 operates as an AND gate circuit when adopting negative logic in which the low level is logic 1. Conversely, the circuit of the embodiment of FIG. 1 operates as an OR gate circuit when adopting negative logic in which the low level is logic 1.
[0021]
FIG. 3 shows an element layout diagram of one embodiment of the circuit of the embodiment of FIG. Two N-channel MOSFETs (Q2, Q3) are formed in the P-type well region PWEL of the first conductivity type. That is, the source and drain regions corresponding to the lower node are shared, two gate electrodes of the source and drain regions are arranged, and the other source and drain regions are formed so as to sandwich the two gate electrodes, respectively. , A non-selection signal transmission NMO (Q2) and a non-selection lower node fixing NMOS (Q3). A selection signal (positive signal) is supplied to a right gate electrode corresponding to the non-selection signal transmission NMOS (Q2), and a left gate electrode corresponding to the lower node fixing NMOS (Q3) at the time of non-selection is selected. A signal (negative signal) is supplied. The substrate potential (lower ground potential) is applied to the other source and drain regions of the lower node fixing NMOS (Q3) at the time of non-selection.
[0022]
An N-type well region NWEL of the second conductivity type is provided adjacent to the N-channel MOSFET (Q2, Q3) formed in the P-type well region PWEL in the direction in which the gate electrodes extend. In the N-type well region NWEL, a pair of P-type source and drain regions and a gate electrode are formed so as to be sandwiched between the pair of source and drain regions, thereby forming a selection signal transmitting PMOS (Q1). The selection signal transmitting PMOS (Q1) and the non-selection signal transmitting NMOS (Q2) are arranged such that their gate, source, and drain regions are arranged in the extending direction of the gate electrode. The wiring forming the upper node as one input terminal and the wiring forming the lower node as the output terminal are connected with the shortest distance by a linear wiring arranged in the extending direction of the gate electrode.
[0023]
The gate electrode of the non-selected lower node fixing NMOS (Q3) to which the selection signal (negative signal) is transmitted and the gate electrode of the selection signal transmitting PMOS (Q1) are integrally formed. That is, as a result of the arrangement of the source and the drain as described above, the gate electrode of the selection signal transmission PMOS (Q1) and the gate electrode of the non-selection signal transmission NMOS (Q2) are arranged in a straight line. Therefore, the gate electrode of the selection signal transmitting PMOS (Q1) and the gate electrode of the non-selected lower node fixing NMOS (Q3) are integrally formed so as to be bent along the junction between the well regions PWEL and NWEL. Is done.
[0024]
As in this embodiment, the source and drain regions corresponding to the lower nodes of the two N-channel MOSFETs (Q2 and Q3) are shared, and the contact region therefor can be shared. Although the logic circuit is configured, the circuit elements can be efficiently arranged.
[0025]
FIG. 4 shows an element layout diagram of an embodiment directed to a tournament logic type decoder circuit by combining two embodiments of the embodiment of FIG. This embodiment is directed to one tournament branch (mountain) in which two lower nodes are provided for one input node. In this embodiment, the upper node is shared by the two unit logic circuits. That is, the gate electrode, the source, and the drain region are arranged in a mirror image relationship (mirror) with the connection wiring corresponding to the upper node as a center. As a result, a total of six MOSFETs can be efficiently arranged.
[0026]
FIG. 5 shows an element layout diagram of one embodiment directed to a tournament logic type decoder circuit in which three tournament branches (mountains) in FIG. 4 are combined. In this embodiment, a 2-bit decoder circuit is configured by combining the three tournament branches (mountains). The two unit theory and other circuits corresponding to the highest node are the same as those in the embodiment of FIG. Two tournament branches (mountains) of the next bit having the output nodes of these two unit logic circuits as input nodes are provided in the same manner as described above. Also in this configuration, since the unit logic circuits are arranged so as to have a mirror image relationship, element arrangement can be performed efficiently.
[0027]
FIG. 6 is a circuit diagram showing one embodiment of a tournament logic type decoder circuit using a unit logic circuit according to the present invention. In the tournament logic type decoder circuit of this embodiment, 16-bit decode signals 0 to F are formed by decoding 4-bit address signals A0 to A3.
[0028]
In this embodiment, the address signal A3 of the most significant bit is directly output as an inverted signal (negative signal) and a non-inverted signal (positive signal) by the two inverter circuits N7 and N8 connected in series. The negative signal and the positive signal are used as they are as the signals of the input nodes of the unit logic circuits UL21 to UL24 that receive the selection signal (positive signal, negative signal) formed by the address signal A2. That is, the negative signal corresponding to the address signal A3 is transmitted to the input node of the tournament branch unit logic circuit including the two unit logic circuits UL21 and UL22. The positive signal corresponding to the address signal A3 is transmitted to the input node of the tournament branch unit logic circuit including the two unit logic circuits UL23 and UL24.
[0029]
An output node of the unit logic circuit UL21 using the address signal A2 as a selection signal is transmitted to an input node of a tournament branch unit logic circuit including two unit logic circuits UL11 and UL12 using the lower address signal A1 as a selection signal. Similarly, the output nodes of the unit logic circuits UL22 to UL24 also include three tournament branch units each including two unit logic circuits UL13 and UL14, UL15 and UL16, and UL17 and UL18 each using the lower address signal A1 as a selection signal. It is transmitted to each input node of the logic circuit. As for the address signals A0 to A2, selection signals (negative signal and positive signal) are formed by inverter circuits N1, N2 to N5 and N6, respectively.
[0030]
The output node of the unit logic circuit UL11 using the address signal A1 as a selection signal is connected to the input node of a tournament branch unit logic circuit including two unit logic circuits UL01 and UL02 using the lowest address signal A0 as a selection signal. Reportedly. The output nodes of the remaining seven unit logic circuits UL12 to UL18 are also provided with two unit logic circuits, respectively. As a result, the unit logic circuit using the address signal A0 of the least significant bit as the selection signal is composed of 16 units such as UL01 to UL0F, and outputs 16 kinds of decode signals such as 0 to F from each.
[0031]
In the tournament logic type decoder circuit system of this embodiment, the unit logic circuit shown in FIG. 1 in which the highest address is an input signal and the following address signal is a control signal is arranged in a tournament type. A lower node of a unit logic circuit controlled by an address is used as a decode output.
[0032]
FIG. 7 is an explanatory diagram for explaining an example of the operation of the tournament logic type decoder circuit of FIG. In this embodiment, the state of each node when (0110) is input as the address signals A3 to A0 is shown. As shown in the figure, only the selected address outputs a positive signal as indicated by a solid black line, and the other signals are fixed to negative signals in some form as indicated by hatching, although the number of stages is different.
[0033]
In this embodiment, as the selection signal, the high level of the inverted signal of the address signal A3 due to the logic 0 is the selection transmission path of the unit logic circuit according to the logic 1 of the address signal A2 as indicated by the thick solid line, and the logic of the address signal A1. A high-level selection signal is output from the decode output 6 through a selection signal transmission path of the unit logic circuit based on 1 and a selection signal transmission path of the unit logic circuit based on the logic 0 of the address signal A0.
[0034]
On the other hand, in the decode output 0, the low level formed by the non-selected circuit node fixed NMOS formed by the address signal A1 is output through the selection signal transmission path of the unit logic circuit based on the logic 0 of the address signal A0. . Such a signal path is the same for the decode outputs 4, 8, and C. As the decode output 1, a low level formed by the non-selected circuit node fixed NMOS formed by the address signal A0 is output. In such a signal path, the decode outputs 3, 5, 9, C, and F are similar. The decode output 2 has a low level formed by the non-selected circuit node fixed NMOS formed by the address signal A2, the unit signal transmission path of the unit logic circuit based on the logic 1 of the address signal A1, and the unit based on the logic 0 of the address signal A0. It is output through the selection signal transmission path of the logic circuit. Such a signal path is the same for the decode output A.
[0035]
The decode output E is a selection signal that has a low level of a non-inverted signal based on logic 0 of the address signal A3, a selection transmission path of the unit logic circuit based on logic 1 of the address signal A2, and a selection transmission path of the unit logic circuit based on logic 1 of the address signal A1. The decode output 6 is output as a low-level non-selection signal through the selection signal transmission path and the selection signal transmission path of the unit logic circuit based on the logic 0 of the address signal A0.
[0036]
The basic operation of this circuit is that regardless of the increase in the number of bits of the address signal, even when the number of bits is increased, a decoder circuit can be realized only by adding a unit logic circuit of the least significant bit of the tournament. In this case, the number of transistors of the N-bit decoder circuit is about 56% for 5 bits, about 48% for 6 bits, and 7 bits when the NAND type is adopted as shown in FIG. The effect increases as the number of bits increases, for example, about 42% for 8 bits and about 37% for 8 bits. That is, the effect of reducing the number of elements increases. In addition, the decoder selection speed is higher than that in the case where a NAND circuit is used for both the selected and unselected addresses, so that the decoder circuit has equal or higher performance.
[0037]
FIG. 9 is a block diagram of a main part of one embodiment of a liquid crystal display system to which the present invention is applied. The display system of this embodiment includes a microprocessor (not shown) for generating display data, a TFT drain driver LSI, a GATE (gate) driver, and a liquid crystal panel.
[0038]
Although not particularly limited, the TFT drain driver LSI is constituted by one semiconductor integrated circuit device, and a liquid crystal driving voltage generating circuit (display voltage) for supplying a voltage (display voltage) used for driving a liquid crystal panel. Generating circuit), a liquid crystal driver (DRAIN driver) for driving a liquid crystal panel based on the liquid crystal driving voltage, an output voltage control switch, a controller, and a memory. The controller controls operations of the drain driver and the liquid crystal drive voltage generation circuit.
[0039]
The scanning line electrodes (gate electrodes) of the liquid crystal panel are sequentially selected by a GATE driver. A signal line electrode (drain line) of the liquid crystal panel is driven by a DRAIN driver that outputs a liquid crystal driving voltage corresponding to display data. An active matrix display operation is performed by inputting a liquid crystal driving voltage corresponding to gray scale display by one pixel provided at the intersection of the scanning line electrode and the signal line electrode of the liquid crystal panel and holding it for one frame period. I do.
[0040]
That is, the liquid crystal panel is composed of a liquid crystal display panel having an active TFT (thin film transistor) configuration, and a display voltage is applied by a TFT transistor to an intersection of a plurality of scanning line electrodes (common electrodes) and a plurality of signal line electrodes (segment electrodes). It is composed of pixels. A microprocessor (not shown) forms display data, performs predetermined data processing, and generates display data and the like for displaying the result on the liquid crystal panel.
[0041]
FIG. 10 is a block diagram showing one embodiment of the liquid crystal display drive circuit. This liquid crystal display driving circuit corresponds to the DRAIN driver section shown in FIG. In the display data input from the microcomputer, a plurality of display data for at least one scanning line is held in a controller or a memory circuit (not shown) or an output voltage control latch, and the display data is supplied in parallel to the tournament logic type decoder circuit according to the present invention. Is entered.
[0042]
A plurality of the tournament logic type decoder circuits are provided corresponding to the plurality of display data, and decode the display data to form a gradation selection signal. The gray scale selector provided corresponding to the signal line electrode (drain line) of the liquid crystal display panel selects a gray scale corresponding to the display data from a plurality of gray scale voltages formed by the gray scale voltage generation circuit. One gradation voltage is selected according to the selection signal, and the gradation voltage is output to the signal line electrode (drain line) of the liquid crystal display panel.
[0043]
FIG. 11 shows a circuit diagram of one embodiment of one of the plurality of gradation selectors of FIG. The selection signal formed by the tournament logic type decoder circuit is output through inverter circuits N10, N11, etc., which form complementary control signals for a CMOS switch composed of a P-channel MOSFET and an N-channel MOSFET. A voltage as shown in FIG. 12 is output to the gradation input through this gradation selector. If the signal generated by the tournament logic type decoder circuit is lower than such an output gray level, the gray scale voltage cannot be output through the CMOS switch, so that the inverter circuits N10, N11, etc. A level conversion function is provided so that the level of the selection signal of the CMOS switch is sufficiently higher than the gradation voltage.
[0044]
A CMOS switch composed of the N-channel MOSFET and the P-channel MOSFET is provided for a plurality of gradation levels, and the output side is connected in common and output as a liquid crystal drive voltage. In this configuration, one CMOS switch is provided in the signal path for outputting the gradation level. For this reason, if the switch ON resistance is R, the output resistance of the display driver can be reduced to R. Therefore, it is possible to obtain a liquid crystal panel charging voltage close to the ideal waveform in FIG. 20 as compared with the configuration in which one of a plurality of gray scale voltages is selected and output by the tournament type switch tree as described above. High display quality can be obtained.
[0045]
FIG. 13 is a circuit diagram of another embodiment of a tournament logic type decoder circuit using a unit logic circuit according to the present invention. The tournament logic type decoder circuit of this embodiment also decodes the 4-bit address signals A0 to A3 in the same manner as in FIG. 6 to form 16 decode signals 0 to F.
[0046]
In this embodiment, the NOR gate circuits G7 and G8 form selection signals (negative signal and positive signal) for the address signal A3 of the most significant bit. An address selection signal AS is supplied to the NOR gate circuits G7 and G8. By setting the signal AS to a high level (logic 1), the signal levels of the gate circuits G7 and G8 can be set to a low level (logic 0) independently of the address signal A3. In this configuration, by setting the address selection signal AS to a high level, all the decoder outputs 0 to F can be set to a non-selection level (low level).
[0047]
In this embodiment, the decoder outputs 0 to F can be simultaneously all unselected by a simple configuration in which the inverter circuits N7 and N8 in FIG. 6 are changed to the gate circuits G7 and G8. This configuration is useful, for example, when creating a completely unselected state for a memory circuit or a liquid crystal panel.
[0048]
FIG. 14 is a circuit diagram of still another embodiment of the tournament logic type decoder circuit using the unit logic circuit according to the present invention. The tournament logic type decoder circuit of this embodiment also decodes the 4-bit address signals A0 to A3 in the same manner as in FIG. 6 to form 16 decode signals 0 to F.
[0049]
In this embodiment, the inverter circuits N1 to N6 corresponding to the address signals A0 to A2 in FIG. 6 are replaced with OR gate circuits G1 to G6, and the inverter circuits N7 and N8 corresponding to the address signal A3 are connected to the NAND gate circuits G7 and G8. Be replaced. Then, the address selection signal AS is transmitted to the gate circuits G1 to G6, inverted by the inverter circuit N9, and transmitted to the gate circuits G7 and G8.
[0050]
In this configuration, when the address selection signal AS is set to a high level (logic 1), the input node corresponding to the most significant bit is set to a high level (logic 1) regardless of the address signal A3, and regardless of the address signals A0 to A2. Both the negative signal (N) and the positive signal (P) become low level (logic 0), and the selection transmission PMOS is turned on (ie, the switch is connected) in each unit logic circuit. Since the input nodes corresponding to the most significant bit A3 are both at the high level (logic 1), the decode output signals 0 to F are at the high level in the all-selected state.
[0051]
In this embodiment, the decoder outputs 0 to F can be all selected at the same time by a simple configuration in which the inverter circuit is changed to the NOR gate circuit and the NAND gate circuit. This configuration is useful, for example, when creating an all-selected state for a memory circuit or a liquid crystal panel.
[0052]
FIG. 15 is a circuit diagram showing one embodiment of a static RAM to which the present invention is applied. The memory cell includes a latch circuit in which an input and an output of a CMOS inverter circuit are cross-connected, an N-channel address selection MOSFET provided between a pair of input / output nodes of the latch circuit and a complementary data line. Consists of The gate of the address selection MOSFET is connected to a word line.
[0053]
The memory cell is provided at an intersection between a plurality of complementary data line pairs and a plurality of word lines. The word line selection circuit forms a selection signal for one of the plurality of word lines. The data line selection circuit selects a pair of data lines from the plurality of pairs of data lines and transmits a read signal of the data line to an input terminal of an amplifier circuit such as a sense amplifier (not shown). Alternatively, a write signal formed by a write amplifier (not shown) is transmitted to the pair of data lines, and the write signal is written to a memory cell whose word line is selected.
[0054]
FIG. 16 is a circuit diagram of one embodiment of the word line selection circuit of FIG. In this embodiment, the tournament logic type decoder circuit having all non-selection functions shown in FIG. 13 is used. A word driver composed of an inverter circuit is provided at an output portion of the tournament logic type decoder circuit shown in FIG. 13, and word drive signals such as word lines WL0 to WL15 are formed.
[0055]
In this embodiment, in the data holding state (standby state) in which neither writing nor reading is performed in the static RAM, all the word lines WL0 to WL15 can be set to the non-selected low level by the high level of the signal AS. With this configuration, in the static RAM as shown in FIG. 15, all the address selection MOSFETs of the memory cells can be turned off. As a result, it is possible to prevent the generation of a direct current flowing through the memory cell from a load MOSFET or the like (not shown) provided on the data line, thereby achieving low power consumption.
[0056]
The tournament logic type decoder circuit of the present embodiment can be applied to all decoder circuit portions included in such a memory circuit. As a result, in addition to the simple provision of the above all non-selection function, the element As a result, the layout area can be reduced.
[0057]
FIG. 17 is a block diagram showing one embodiment of a mobile phone device to which the present invention is applied. A voice interface is provided corresponding to a microphone (transmitter) and a speaker (receiver). A high-frequency interface for outputting a transmission radio wave and inputting a reception radio wave is provided corresponding to the antenna. A microprocessor for performing signal processing (baseband), a DSP (digital signal processor) and an ASIC (logic circuit) and a memory circuit for storing data are provided. As the memory circuit, a static RAM or a nonvolatile memory (flash memory) is used.
[0058]
The above-described liquid crystal controller (LSI) and the liquid crystal panel are provided to perform necessary display operations. Note that a switch (button or a switch (button) for switching an operation mode) for dial input or character input is included in the baseband unit. A liquid crystal controller mounted on such a mobile phone device includes a liquid crystal driver or By using the tournament logic type decoder circuit in the display RAM, the layout area can be reduced.
[0059]
The drain driver LSI for the TFT liquid crystal has a built-in decoder circuit for each output terminal in order to output the liquid crystal level selected respectively to the panel from each output terminal. Since the circuit connected to this output terminal is a logic for outputting a liquid crystal drive voltage, it must be configured with an element (high breakdown voltage element) that can operate even at a high voltage, and has a larger area than a normal unit element.
[0060]
By employing the tournament logic type decoder circuit according to the present invention, the area of the output terminal portion is reduced to about half of the case where the decoder circuit as shown in FIG. 18 studied prior to the present invention is employed. it can. That is, when the gradation selector shown in FIG. 11 is used, the ON resistance of the output can be reduced, but the decoder must also be configured with a high withstand voltage. It will be doubled. In a normal liquid crystal driving LSI, the gradation selector section is about 30% of the chip, so that the entire chip is 60% larger. As described above, the tournament logic type decoder circuit according to the present invention, which can be configured with a smaller number of high-withstand-voltage CMOS structures, will be useful for the gradation selector of the future liquid crystal controller driver LSI.
[0061]
Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention. Nor. For example, the element rare widget of the unit logic circuit can adopt various embodiments according to the circuit configuration. The present invention can be widely used not only for a tournament logic type decoder circuit used for a memory circuit such as a liquid crystal driving LSI or a static RAM, but also for a tarrandom logic circuit including an AND gate circuit or an OR gate circuit.
[0062]
【The invention's effect】
The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application. A first input signal is supplied to one of a source and a drain of the first MOSFET. When the second input signal supplied to the gate of the first MOSFET is at one level, a signal of the other level of the first input signal is supplied to the first MOSFET. , And a first input signal is supplied to one of the source and the drain of the second MOSFET, and the first input signal is supplied when the second input signal supplied to the gate of the second MOSFET is at the other level. A signal of one level of the signal is output from the other of the source and the drain of the second MOSFET, and a fixed potential corresponding to one level of the first input signal applied to one of the source and the drain of the third MOSFET is applied to the third MOSFET. When the second input signal supplied to the gate is at the other level, the other of the source and drain of the third MOSFET By et output, it is possible to obtain a unit logic circuits for the versatile with a simple structure.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing one embodiment of a logic circuit according to the present invention.
FIG. 2 is a circuit diagram showing another embodiment of the logic circuit according to the present invention.
FIG. 3 is an element layout diagram of one embodiment of the logic circuit of FIG. 1;
4 is an element layout diagram of one embodiment of a tournament logic type decoder circuit in which two logic circuits of FIG. 1 are combined.
5 is an element layout diagram of one embodiment of a tournament logic type decoder circuit in which three tournament branches in FIG. 4 are combined.
FIG. 6 is a circuit diagram showing one embodiment of a tournament logic type decoder circuit using a unit logic circuit according to the present invention.
FIG. 7 is an explanatory diagram for explaining an example of the operation of the tournament logic type decoder circuit of FIG. 6;
FIG. 8 is a comparative explanatory diagram of the required number of transistors in the tournament logic type and NAND type decoder circuits according to the present invention.
FIG. 9 is a block diagram of a main part showing an embodiment of a liquid crystal display system to which the present invention is applied.
FIG. 10 is a block diagram showing one embodiment of a liquid crystal display drive circuit.
FIG. 11 is a circuit diagram showing one embodiment of a gradation selector of FIG. 10;
FIG. 12 is a characteristic diagram for explaining the relationship between gradation and voltage.
FIG. 13 is a circuit diagram showing another embodiment of the tournament logic type decoder circuit using the unit logic circuit according to the present invention.
FIG. 14 is a circuit diagram showing still another embodiment of the tournament logic type decoder circuit using the unit logic circuit according to the present invention.
FIG. 15 is a circuit diagram showing one embodiment of a static RAM to which the present invention is applied.
FIG. 16 is a circuit diagram showing one embodiment of the word line selection circuit of FIG. 15;
FIG. 17 is a block diagram showing one embodiment of a mobile phone device to which the present invention is applied.
FIG. 18 is a circuit diagram of a decoder circuit studied prior to the present invention.
FIG. 19 is a circuit diagram of a gradation selector that has been studied prior to the present invention.
20 is a waveform diagram of a liquid crystal drive signal selected by the gradation selector of FIG.
[Explanation of symbols]
Q1 to Q6: MOSFET, UL01 to UL24: Unit logic circuit, N1 to N11: Inverter circuit, G1 to G8: Gate circuit.

Claims (9)

A first input signal is supplied to one of a source and a drain, a second input signal is supplied to a gate, and when the second input signal is at one level, a signal at the other level of the first input signal is supplied to the source. Or a first MOSFET of a first conductivity type for outputting to the output node from the other of the drains;
One of the source and the drain is supplied with the first input signal, the gate is supplied with an inverted signal of the second input signal, and the other of the first input signal when the second input signal is at the other level. A second MOSFET of a second conductivity type for outputting a level signal from the other of the source or the drain to the output node;
When a predetermined potential corresponding to a signal of one level of the first input signal is applied to one of a source and a drain, and the second input signal is supplied to a gate, and the second input signal is at the other level, A semiconductor integrated circuit device comprising a unit logic circuit such as a third MOSFET of a second conductivity type that transmits the predetermined potential to the output node. In claim 1,
The first MOSFET is a P-channel type, the other level of the first input signal is a positive power supply voltage,
2. The semiconductor integrated circuit device according to claim 1, wherein the second MOSFET and the third MOSFET are N-channel type, and one level of the first input signal is a circuit ground potential. In claim 1,
The first MOSFET is an N-channel type, the other level of the first input signal is a circuit ground potential,
2. The semiconductor integrated circuit device according to claim 1, wherein the second MOSFET and the third MOSFET are P-channel type, and one level of the first input signal is a positive power supply voltage. In claim 1,
The second input signal is a complementary signal having a binary weight,
The second input signal is supplied complementarily as a set of two unit logic circuits,
The input nodes of the two unit logic circuits are supplied with the first input signal in common, and the output nodes of each unit logic circuit are connected to the two unit logic circuits corresponding to the second input signal of lower bits. A semiconductor integrated circuit device connected to an input node of a circuit. In claim 4,
As for the signal of the most significant bit of the second input signal composed of a plurality of bits, one of the complementary signals is transmitted to the two unit logic circuits as the first input signal, and the other signal is the two input signals. Transmitted to the unit logic circuit as a first input signal,
A semiconductor integrated circuit device, wherein a binary signal of a bit next to the most significant bit is supplied as the second input signal to the four unit logic circuits. In claim 5,
The semiconductor integrated circuit device according to claim 1, wherein the signal of the upper-order bit is a signal in which the complementary signal is forcibly set to an in-phase signal by a control signal. 6. The semiconductor integrated circuit device according to claim 5, wherein in the second input signal having a plurality of bits, the complementary signal is forcibly set to an in-phase signal by a control signal. In claim 6,
A semiconductor integrated circuit device, wherein the unit logic circuit constitutes a decoder circuit that decodes an address signal supplied to a memory circuit to form a word line or bit line selection signal. In claim 7,
A semiconductor integrated circuit device, wherein the unit logic circuit constitutes a decoder circuit for forming a selection signal of a selection switch for selecting one of a plurality of gray scale voltages in accordance with display data.

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