JP2004055825A - Mounting structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve high reliability in electrical connection between a semiconductor chip and a build-up wiring board and also to achieve a high reliability in electrical connection between the build-up wiring board and a mother board, in a mounting structure wherein the mother board, the build-up wiring board, and the semiconductor chip are stacked in layers. <P>SOLUTION: The mounting structure X1 comprises the mother board 30 having electrode sections 31; buffer section 40 which have conductive connection sections 42 electrically connected to the electrode sections 31, and which is mounted on the mother board 30; build-up wiring board 20 which has, on a first plane, a first electrode section 22d in contact with the conductive connection sections 42, and has a second electrode section 22e on a second plane on the opposite side from the first plane, and which is mounted on the mother board 30 via the buffer section 40; and semiconductor chip 10 which is mounted on the build-up wiring board 20 via bump sections 11 electrically connected to the second electrode section 22e. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a mounting structure in which a semiconductor device including a build-up wiring board and a semiconductor chip mounted on the build-up wiring board is mounted on a mother board.
[0002]
[Prior art]
2. Description of the Related Art In recent years, with demands for higher performance and smaller size of electronic devices, high-density mounting of electronic components incorporated in the electronic devices has been rapidly progressing. In order to cope with such high-density mounting, semiconductor chips such as CPUs are surface-mounted in a bare chip state, and a board for mounting the semiconductor chips is a build-up wiring board in which wiring is multilayered. Is often adopted. A semiconductor package or a semiconductor device having such a mounting structure is further mounted on a motherboard so as to constitute a part of a predetermined electronic circuit.
[0003]
The build-up wiring board generally has a core board and build-up portions formed on both surfaces thereof. In the build-up section, wiring patterns are embedded between a plurality of stacked build-up insulating layers, and each wiring pattern is electrically connected by a via formed in a via hole formed in the insulating layer. I have.
[0004]
In the manufacture of a build-up wiring board, the formation of a build-up insulating layer and the formation of a wiring pattern on the insulating layer are sequentially repeated, and the wiring is multilayered. Specifically, first, a build-up insulating layer is formed on a core substrate or a build-up insulating layer on which a wiring pattern has already been formed from above the wiring pattern. Next, a via hole is formed in the insulating layer. As a method of forming a via hole, a method of forming a hole in the insulating layer by photolithography using a photosensitive resin as a material of the insulating layer, a method of forming a hole in the insulating layer by irradiating a laser, or the like is adopted. After forming a via hole in the insulating layer, a wiring pattern is formed on the insulating layer by, for example, a semi-additive method or a subtractive method. At this time, vias are formed in the via holes with the conductive material together with the wiring patterns. After the wiring pattern is formed on the insulating layer in this manner, a series of steps from the formation of the insulating layer to the formation of the wiring pattern are repeated a predetermined number of times, whereby the wiring can be multilayered.
[0005]
In the build-up wiring board, a fine wiring pattern can be formed at a high density in the build-up portion, and thus it is possible to provide the external connection electrode portions at a fine pitch on the surface of the build-up portion. . Therefore, for example, a semiconductor chip having a plurality of ball electrodes for external connection provided in a grid array at a fine pitch can be surface-mounted on a build-up wiring board in a bare chip state. .
[0006]
In surface mounting of a semiconductor chip on a build-up wiring board, that is, flip chip mounting, connection reliability is often low due to a difference in thermal expansion coefficient between the build-up wiring board and the semiconductor chip. The thermal expansion coefficient in the plane spreading direction of a semiconductor chip made of a general semiconductor material is 3 to 3.5 ppm / K, and the thermal expansion in the plane spreading direction of a general build-up wiring board employing a glass epoxy substrate as a core substrate. The rate is 15 to 20 ppm / K, and the difference between the two coefficients of thermal expansion is relatively large. For this reason, stress is likely to occur in the electrical connection between the semiconductor chip and the build-up wiring board due to a change in the environmental temperature. Therefore, the reliability of the electrical connection between the semiconductor chip and the build-up wiring board is low. They tend to be low.
[0007]
As one of means for improving connection reliability, there is known a technique in which a core substrate of a build-up wiring substrate employs a substrate obtained by impregnating a carbon fiber sheet with a resin material instead of a conventional glass epoxy substrate. Has been. Since the coefficient of thermal expansion of a core substrate including a carbon fiber sheet is smaller than that of a core substrate generally used in the related art, the coefficient of thermal expansion of a build-up wiring board including the core substrate is equal to the coefficient of thermal expansion of a semiconductor chip. A value closer to the expansion rate is shown. Therefore, by using the build-up wiring board employing the core substrate including the carbon fiber sheet, the connection reliability in flip-chip mounting of the semiconductor chip on the build-up wiring board can be improved. A wiring board provided with a core substrate in which a carbon fiber sheet is impregnated with a resin material is disclosed in, for example, JP-A-11-40902 and JP-A-2001-332828.
[0008]
[Means for Solving the Problems]
A semiconductor package or a semiconductor device including a build-up wiring board and a semiconductor chip flip-chip mounted thereon is mounted on a mother board as described above. From the viewpoint of high-density mounting of electronic components, the semiconductor package may be provided with a plurality of solder ball electrodes arranged in a grid array, and may be surface-mounted on a motherboard via the solder ball electrodes.
[0009]
However, the build-up wiring board including the carbon fiber sheet-containing core board has a smaller coefficient of thermal expansion in the plane spreading direction than that of a general mother board. The coefficient of thermal expansion in the plane spreading direction of a general mother board is 15 to 18 ppm / K, which is almost the same as the coefficient of thermal expansion in the plane spreading direction of a general build-up wiring board employing a glass epoxy substrate as a core substrate. is there. Therefore, when a build-up wiring substrate having a carbon fiber sheet-containing core substrate and having a smaller coefficient of thermal expansion than the conventional one is surface-mounted on a mother substrate via a plurality of solder ball electrodes provided thereon, there is a gap between the two. Since there is a significant difference in the coefficient of thermal expansion, a relatively large stress is likely to be generated in the electrical connection between the build-up wiring board and the mother board due to a change in the environmental temperature. That is, when using a build-up wiring board including a carbon fiber sheet-containing core board, the connection reliability in mounting a semiconductor package is lower than when using a general build-up wiring board including a glass epoxy core board. It will be lost.
[0010]
The present invention was conceived under such circumstances, and a semiconductor package or a semiconductor device including a build-up wiring board and a semiconductor chip mounted on the flip-chip is mounted on a mother board. The purpose of the present invention is to achieve high reliability in the electrical connection between the semiconductor chip and the build-up wiring board, and also achieve high reliability in the electrical connection between the build-up wiring board and the mother board in the mounting structure. I do.
[0011]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a mounting structure. This mounting structure has a mother substrate having an electrode portion, a conductive contact portion electrically connected to the electrode portion, a buffer portion mounted on the mother substrate, and a third portion in contact with the conductive contact portion. A build-up wiring board having one electrode portion on the first surface, having a second electrode portion on a second surface opposite to the first surface, mounted on the motherboard via a buffer portion, And a semiconductor chip mounted on the build-up wiring board via a bump section electrically connected to the section.
[0012]
According to such a configuration, high reliability of electrical connection between the build-up wiring board and the mother board can be achieved. In the mounting structure according to the first aspect of the present invention, the build-up wiring board is electrically connected to the mother board via a conductive connecting part of a buffer mounted on the mother board. The first electrode portion of the build-up wiring board is not joined to the conductive connecting portion electrically connected to the electrode portion of the mother board. The first electrode portion is in contact with the conductive connecting portion so as to be electrically connected. Therefore, even when the difference between the coefficients of thermal expansion in the plane spreading direction of the build-up wiring board and the mother board is relatively large, there is a gap between the first electrode portion of the build-up wiring board and the conductive connecting portion of the buffer section. Even if the environmental temperature changes, no stress is generated, or only a sufficiently small stress is generated. As a result, regarding the electrical connection between the build-up wiring board and the mother board, even when the difference in the coefficient of thermal expansion between the build-up wiring board and the mother board is relatively large, the connection reliability due to the generation of stress is reduced. The decrease is eliminated or sufficiently reduced.
[0013]
Further, according to the mounting structure according to the first aspect of the present invention, high reliability can be achieved also for the electrical connection between the semiconductor chip and the build-up wiring board. Regarding the electrical connection between the build-up wiring board and the mother board, as described above, it is possible to achieve good connection reliability even when the difference in thermal expansion coefficient between the two is relatively large. Therefore, a substrate having a coefficient of thermal expansion close to the coefficient of thermal expansion of the semiconductor chip can be used as the build-up wiring board. A predetermined semiconductor chip is surface-mounted on a build-up wiring board having a coefficient of thermal expansion close to the coefficient of thermal expansion to eliminate or sufficiently reduce a decrease in connection reliability caused by a difference between the two coefficients of thermal expansion. It is possible to reduce.
[0014]
As described above, according to the mounting structure according to the first aspect of the present invention, high reliability is achieved for the electrical connection between the semiconductor chip and the build-up wiring board, and the electrical connection between the build-up wiring board and the mother board is achieved. Can also achieve high reliability.
[0015]
According to a second aspect of the present invention, another mounting structure is provided. This mounting structure includes a mother substrate having an electrode portion, a socket body mounted on the mother substrate including a buffer portion having a conductive connection portion electrically connected to the electrode portion, and a socket body. A semiconductor device mounted on the motherboard through the semiconductor device, and a socket lid for pressing the semiconductor device against the socket body. The semiconductor device has a first electrode portion in contact with the conductive contact portion on a first surface. A build-up wiring board having a second electrode portion on a second surface opposite to the first surface, and mounted on the build-up wiring board via a bump portion electrically connected to the second electrode portion. It is characterized by including a semiconductor chip.
[0016]
The mounting structure according to the second aspect of the present invention includes the configuration of the mounting structure according to the first aspect. Therefore, according to the second aspect of the present invention, effects similar to those described above with respect to the first aspect can be obtained.
[0017]
Preferably, the difference in thermal expansion coefficient between the build-up wiring board and the semiconductor chip in the plane spreading direction is 1.5 to 7 ppm / K, and the difference in thermal expansion coefficient between the mother substrate and the build-up wiring board in the plane spreading direction is 5 ppm. １３13 ppm / K. Alternatively, preferably, the thermal expansion coefficients of the semiconductor chip, the build-up wiring board, and the mother board in the plane spreading direction are 3 to 3.5 ppm / K, 5 to 10 ppm / K, and 15 to 18 ppm / K, respectively. K. Such a configuration relating to the coefficient of thermal expansion is achieved by using a semiconductor chip and a build-up wiring board in a mounting structure in which a semiconductor device including a build-up wiring board and a semiconductor chip mounted on the flip-chip is mounted on a mother board. And the electrical connection between the build-up wiring board and the mother board tend to be preferably achieved in order to achieve high reliability.
[0018]
Preferably, the bump portion is a plurality of ball electrodes provided in a grid array between the build-up wiring board and the semiconductor chip. Such a ball grid array structure is suitable for mounting a multi-pin semiconductor chip on a build-up wiring board on which fine wiring is formed.
[0019]
Preferably, an underfill material is interposed between the build-up wiring board and the semiconductor chip. According to such a configuration, part of the stress generated in the electrical connection between the build-up wiring board and the semiconductor chip is absorbed by the underfill material, and as a result, the connection reliability between the build-up wiring board and the semiconductor chip is reduced. The decline in sex is suppressed.
[0020]
Preferably, the build-up wiring substrate has a core substrate, and the core substrate has a plurality of carbon fiber cloths woven from carbon fiber yarns in which carbon fibers having a diameter of 10 μm or less are bundled in the thickness direction at intervals of 100 μm or less. A through-hole via is provided in a through-hole that is buried apart and penetrates in the thickness direction and has an insulating film formed on the surface. A build-up wiring board including a core substrate in which a plurality of carbon fiber cloths woven from carbon fiber yarns bundled with carbon fibers having a diameter of 10 μm or less are buried at intervals of 100 μm or less in the thickness direction is 5 to 10 ppm / K. That is, the core substrate having such a configuration is suitable for reducing the difference in the coefficient of thermal expansion between the semiconductor chip and the build-up wiring board. In addition, the carbon fiber cloth of the present configuration has a relatively low degree of obstacle to a drill to be used when forming a through hole penetrating the substrate in the thickness direction, and therefore, reduces the frequency of breakage of the drill. Can be. In addition, the insulating film provided on the surface of the through hole ensures an electrical insulation state between the carbon fiber cloth and the through hole via.
[0021]
Preferably, the buffer unit has a flexible substrate that holds the conductive connecting portion, and the conductive connecting portion faces both surfaces of the flexible substrate. When the conductive connection portion for achieving electrical connection between the electrode portion of the mother board and the first electrode portion of the build-up wiring board is held by the flexible substrate, for example, the electrode portion of the mother board and the conductive connection portion may be solder reflowed. In such a case, some of the stress that may occur between the electrode portion and the conductive connection portion is absorbed by the relatively soft flexible substrate.
[0022]
Preferably, the first electrode portion is a plurality of land electrodes provided in a grid array on the first surface. In such a land grid array (LGA) structure, the first electrode portion of the build-up wiring board and the conductive contact portion of the buffer portion easily come into surface contact with a significant area. Is suitable for electrical connection.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is an exploded perspective view of a mounting structure X1 according to the first embodiment of the present invention. FIG. 2 is a partial cross-sectional view of the mounting structure X1 along the line II-II in FIG. 1, and FIG. 3 is a partial enlarged view of FIG. The mounting structure X1 includes a semiconductor chip 10, a build-up wiring board 20, a mother board 30, and a buffer section 40 interposed between the build-up wiring board 20 and the mother board 30.
[0024]
The semiconductor chip 10 is mounted on a build-up wiring board 20 via a plurality of ball electrodes 11 as shown in FIG. The main part of the semiconductor chip 10 is made of a general semiconductor element material such as silicon, and has a coefficient of thermal expansion of 3 to 3.5 ppm / K. 2, the internal structure of the semiconductor chip 10 is omitted from FIG. The plurality of ball electrodes 11 are arranged in a grid array on one surface of the semiconductor chip 10 to form a ball grid array. The ball electrode 11 is made of gold or solder having a predetermined composition.
[0025]
The build-up wiring board 20 includes a core board 21 and a build-up section 22. The core substrate 21 is formed by laminating a plurality of prepregs 21 ′ obtained by impregnating a carbon fiber cloth (not shown) as a base material with a resin material. In the present embodiment, the core substrate 21 includes five prepregs. 21 '. Inner layer patterns 21 a are formed on both surfaces of the core substrate 21, and the inner layer patterns are electrically connected by through-hole vias 21 b penetrating the core substrate 21. The through-hole via 21b is provided in a through-hole 21d having an insulating film 21c formed on the surface.
[0026]
Examples of the resin material for forming the core substrate 21 or the prepreg 21 ′ include an epoxy resin, a polyimide resin, a maleimide resin, a bismaleimide resin, a cyanate resin, a polyphenylene ether resin, a polyphenylene oxide resin, and a fluorine-containing resin. . If the resin material has a glass transition temperature, the temperature is desirably a high temperature, for example, 150 ° C. or more. The resin material has a higher glass transition temperature if it can be softened by heating at, for example, 150 ° C. or more at the time of manufacturing the core substrate 21 and at 200 ° C. or more at the time of mounting the semiconductor chip 10, for example. Is good. As the glass transition temperature of the resin material constituting the core substrate is higher, the temperature region in which the mounting structure X1 functions effectively often expands to the higher temperature side.
[0027]
The carbon fiber cloth is a cloth in which carbon fiber yarns in which carbon fibers are bundled are woven. In the present embodiment, one carbon fiber cloth included in one prepreg 21 ′ is plain-woven with carbon fiber yarns in which the average number of carbon fibers having a cross-sectional diameter of 10 μm or less is 200 or more. Such carbon fiber cloths are arranged on the core substrate 21 at intervals of 100 μm or less in the substrate thickness direction. The volume occupancy of the carbon fibers in the core substrate 21 is preferably 40 to 90%. The build-up wiring board 20 according to the present embodiment includes the core substrate 21 containing the carbon fiber cloth in such a configuration, and is configured to exhibit a coefficient of thermal expansion of 5 to 10 ppm / K.
[0028]
The build-up section 22 includes a build-up insulating layer 22a, a wiring pattern 22b, a via 22c, and land electrodes 22d and 22e. Specifically, in the build-up section 22, a wiring pattern 22b is embedded between a plurality of stacked build-up insulating layers 22a, and between each wiring pattern is a via hole formed in the build-up insulating layer 22a. It is electrically connected by the provided via 22c. The land electrodes 22d and 22e are terminals for external connection, and are provided on the surface of the build-up portion 22. From the viewpoint of simplification of the drawings, FIGS. 2 and 3 show a state in which a plurality of stacked build-up insulating layers 22a are integrated. As a material forming the build-up insulating layer 22a, a general thermosetting resin can be used. For example, an epoxy resin or a polyimide resin may be used. Considering that the temperature is high when the build-up wiring board 20 is manufactured and when the semiconductor chip 10 is mounted, the build-up insulating layer material has a thermal characteristic similar to the resin material forming the core substrate 21 or the prepreg 21 ′. It is desirable to use a thermosetting resin. Also, from the viewpoint of reducing the thickness of the build-up wiring board 20, the layer thickness of the build-up insulating layer 22a is desirably 100 μm or less.
[0029]
In the manufacture of the build-up wiring board 20, first, a carbon fiber cloth woven with carbon fiber yarns having an average number of 200 or more carbon fibers having a cross-sectional diameter of 10 μm or less is impregnated with a resin material, and the prepreg 21 ′ Is prepared. Next, a plurality of prepregs 21 ′ are laminated, and the laminated body is pressed in the laminating direction under heating to produce an unprocessed core substrate 21. Next, a predetermined number of through holes 21d having a predetermined opening diameter penetrating the core substrate 21 in the thickness direction are formed by drilling. Next, a thermosetting resin material in a B-stage state is laminated on both surfaces of the core substrate 21 by, for example, a vacuum press. At this time, the thermosetting resin material covers the surface of the core substrate and fills the through holes 21d. Next, a through hole is formed in the resin material filled in the through hole 21d by using a drill having a smaller diameter than the previous drill. Thus, an insulating film (not shown) is formed on the surface of the core substrate, and an insulating film 21c is formed on the surface of the through hole. Subsequently, after performing a desmear treatment, an electroless copper plating film is formed on the surface of the core substrate and the surface of the through hole. Next, a dry film resist having a predetermined pattern (corresponding to the inner layer pattern 21a) is formed on the surface of the core substrate, and while using this as a mask, the previously formed electroless copper plating film is used as a current-carrying layer to form an electric copper plating film. To form At this time, a through-hole via 21b is formed by growing an electrolytic copper plating film also on the surface of the through-hole 21d. The through hole 21d is further filled with a resin material. After the dry film resist is removed, the electroless copper plating film that has been covered with the dry film resist is removed by etching. Thus, the core substrate 21 on which the inner layer pattern 21a and the through-hole via 21b are formed is manufactured.
[0030]
In the manufacture of the build-up wiring substrate 20, subsequently, a build-up multilayer wiring structure is formed on both surfaces of the core substrate 21 by a build-up process. In the build-up process, for example, first, the core substrate 21 on which the inner layer pattern 21a is formed, or the build-up insulating layer 22a on which the wiring pattern 22b is formed, Then, a build-up insulating layer 22a is further formed by lamination. The resin material for forming the build-up insulating layer 22a may be sheet-like or liquid. Next, a via hole is formed in the laminated build-up insulating layer 22a. As a method of forming a via hole, a method of forming a hole in the build-up insulating layer 22a by photolithography using a photosensitive resin as an insulating layer material or a method of forming a hole in the build-up insulating layer 22a by irradiating a laser Etc. can be adopted. After forming a via hole in the build-up insulating layer 22a, a wiring pattern 22b is formed on the build-up insulating layer by, for example, a semi-additive method or a subtractive method. At this time, a via 22c is formed in the via hole with the conductive material together with the wiring pattern 22b. After the wiring patterns 22b and the vias 22c are formed in the build-up insulating layer 22a in this manner, a series of steps from the formation of the additional build-up insulating layer 22a to the formation of the wiring patterns 22b and the vias 22c are repeated a predetermined number of times. . By the above build-up process, a build-up multilayer wiring structure is formed on both surfaces of the core substrate 21.
[0031]
In the manufacture of the build-up wiring substrate 20, subsequently, an overcoat layer or a solder resist is formed on the surface of the build-up multilayer wiring structure formed as described above by screen printing and photolithography. 2 and 3, the overcoat layer is shown as being integrated with the build-up insulating layer 22a. An opening is provided in the overcoat layer so that a part of the uppermost wiring pattern 22b in the build-up multilayer wiring structure faces. Next, land electrodes 22d and 22e for connection with external terminals are formed by forming a gold plating film following the electroless nickel film on the wiring pattern facing the opening. The land electrodes 22d formed in the lower build-up section 22 in FIG. 2 are arranged at positions corresponding to the conductive connection sections 42 of the buffer section 40 described later, and constitute a land grid array. The land electrodes 22e formed in the upper build-up section 22 in FIG. 2 are arranged in a grid array at positions corresponding to the ball electrodes 11 of the semiconductor chip 10, thereby forming a land grid array. In this manner, the build-up wiring board 20 having the build-up portions 22 on both surfaces of the core substrate 21 and having the land electrodes 22d and 22e forming the land grid array on both surfaces is manufactured. The semiconductor chip 10 described above is joined to the land electrode 22e by solder reflow with respect to the build-up wiring board 20 having such a configuration. An underfill material 13 is filled between the semiconductor chip 10 and the build-up wiring board 20.
[0032]
The mother substrate 30 has an electrode portion 31 exposed on the surface. The electrode unit 31 is omitted in FIG. 1 from the viewpoint of simplifying the drawing. The mother substrate 30 is, for example, a multilayer printed wiring board manufactured by a batch lamination method, and the electrode portions 31 are electrically connected to predetermined wirings (not shown) formed on the mother substrate 30. For example, a mother board 30 which is a multilayer printed wiring board manufactured by a batch lamination method is configured to exhibit a coefficient of thermal expansion of 15 to 18 ppm / K. The electrode portion 31 is disposed at a position corresponding to the land electrode 22d formed on the lower buildup portion 22 of the buildup wiring board 20.
[0033]
The buffer section 40 includes a base 41 and a conductive connecting section 42 held by the base 41. The conductive connecting portion 42 is made of a conductive material such as copper, for example, and is held by an opening 41 a provided at a predetermined position of the base 41. In FIG. 1, the opening 41a and the conductive connecting part 42 in the buffer part 40 are omitted from the viewpoint of simplifying the drawing. The base 41 is a rigid substrate in the present embodiment, and is obtained by impregnating a predetermined base material such as glass fiber with a resin material. Examples of such a resin material include a phenol resin, an epoxy resin, a polyester resin, a polyimide resin, and a BT resin. As shown in FIG. 3, the conductive contact portion 42 has a curved shape and a first contact portion 42a abutting against the wall surface of the opening 41a, and a second contact portion extending from the first contact portion. 42b, and has a predetermined width in the direction perpendicular to the paper of FIGS. 2 and 3. The first contact portion 42a contacts the land electrode 22d of the build-up wiring board 20, and the second contact portion 42b contacts the electrode portion 31 of the mother board 30. The conductive contact portion 42 is held in the opening 41a by an urging force acting in a direction in which the curved shape of the first contact portion 42a opens. In the disassembled state of the mounting structure X1 as shown in FIG. 1, for example, the first contact portion 42a and the second contact portion 42b protrude from the opening 41a by a predetermined length. On the other hand, in the assembled state of the mounting structure X1 as shown in FIGS. 2 and 3, the first contact portion 42a comes into contact with the land electrode 22d of the build-up wiring board 20 and moves downward in the drawing. It is in a state of being pressed inward of the opening 41a. In addition, the second contact portion 42b comes into contact with the electrode portion 31 of the mother substrate 30 and is pressed inward in the opening portion 41a in the figure. Since the contact is made while the pressing force is acting, good electrical connection is achieved between the first contact portion 42a and the land electrode 22d and between the second contact portion 42b and the electrode portion 31.
[0034]
The buffer unit 40 is incorporated in a part of a socket for a land grid array type package, for example. The socket includes a socket body 51, a socket lid 52, and a stiffener 53, as shown in FIG. The socket body 51 is for accommodating a semiconductor package or a semiconductor device including the semiconductor chip 10 and the build-up wiring board 20, and has a buffer portion 40 formed at a bottom surface thereof. The socket lid 52 has a pressure contact portion 52a for pressing the semiconductor package housed in the socket main body 51 against the socket main body 51. The stiffener 53 is a member for reinforcing the mother board 30 when the socket is mounted, and is provided on the mother board 30 behind the mounting portion 30a.
[0035]
While the semiconductor package including the semiconductor chip 10 and the build-up wiring board 20 is housed in the socket body 51, the socket body 51, the socket lid 52, and the stiffener 53 are screwed with screws 54 so that the socket is attached to the motherboard 30. Fixed. As described above, the semiconductor package including the semiconductor chip 10 and the build-up wiring board 20 is mounted on the mother board 30 via the buffer unit 40.
[0036]
In the mounting structure X1, the coefficient of thermal expansion of the semiconductor chip 10 mounted on the build-up wiring board 20 via the ball electrodes 11 forming the ball grid array is 3 to 3.5 ppm / K, and the build-up wiring The coefficient of thermal expansion of the substrate 20 is 5 to 10 ppm / K. That is, the difference in the coefficient of thermal expansion between the semiconductor chip 10 and the build-up wiring board 20 in the plane spreading direction is 1.5 to 7 ppm / K. Such a difference in the coefficient of thermal expansion is smaller than the difference in the coefficient of thermal expansion (about 11.5 to 17 ppm) in the conventional general semiconductor chip-build-up wiring board mounting structure. Therefore, in the mounting structure X1, a decrease in connection reliability between the semiconductor chip 10 and the build-up wiring board 20 due to a change in environmental temperature can be reduced as compared with the related art.
[0037]
In the mounting structure X1, the coefficient of thermal expansion of the build-up wiring board 20 is 5 to 10 ppm / K as described above, and the coefficient of thermal expansion of the mother board 30 is 15 to 18 ppm / K. That is, the difference between the coefficients of thermal expansion of the build-up wiring board 20 and the mother board 30 in the plane spreading direction is 5 to 13 ppm / K, which is relatively large. However, the buffer section 40 is interposed between the build-up wiring board 20 and the mother board 30 while maintaining electrical connection between them. The land electrode 22d of the build-up wiring board 20 is in contact with the conductive connecting part 42 of the buffer part 40 and is not joined. At the same time, the electrode portion 31 of the mother substrate 30 is in contact with the conductive connecting portion 42 and is not joined. Therefore, in the mounting structure X1, even when the build-up wiring board 20, the mother board 30, and the buffer section 40 expand to a different degree with a relatively large difference according to a change in the environmental temperature, the land electrode 22d and the electrode By maintaining an appropriate contact state between the portion 31 and the conductive contact portion 42, good connection reliability between the build-up wiring board 20 and the mother board 30 can be achieved.
[0038]
In the present embodiment, the second contact portion 42b of the conductive connecting portion 42 and the electrode portion 31 may be joined via, for example, a conductive adhesive or a solder material. , Similarly to the mother substrate 30, the thermal expansion coefficient is 15 to 18 ppm / K. By making the thermal expansion coefficients of the buffer section 40 and the mother substrate 30 close to each other, even when the second contact section 42b of the conductive connecting section 42 and the electrode section 31 are joined, the conductive connecting section 42 and the electrode section 31 are not bonded. Unreasonable stress is less likely to occur at the joint. Therefore, even in the case where the conductive contact portion 42 and the electrode portion 31 are joined in the present embodiment, it is possible to achieve good connection reliability between the build-up wiring board 20 and the mother board 30. .
[0039]
As described above, in the mounting structure X1, good connection reliability between the semiconductor chip 10 and the build-up wiring board 20 is achieved, and good connection reliability between the build-up wiring board 20 and the mother board 30 is achieved. It is possible to achieve.
[0040]
FIG. 4 shows a mounting structure X2 according to the second embodiment of the present invention, and is a partial cross-sectional view of a portion corresponding to the partial cross-sectional view of FIG. 2 in the mounting structure X1. FIG. 5 is a partially enlarged view of FIG. The mounting structure X2 differs from the mounting structure X1 in the configuration of the buffer unit 40. Other configurations are the same as those of the mounting structure X1.
[0041]
The buffer section 40 of the mounting structure X2 includes a base 41 and a conductive connecting section 42 held by the base 41. The base 41 is a flexible substrate and is made of, for example, a flexible polyimide film or polyester film. The base 41 has, for example, a cylindrical opening at a predetermined position. The conductive connecting portion 42 is formed by patterning the base 41 in a region including the opening by a subtractive method or an additive method, and penetrates the base 41 through the opening to be formed on both surfaces of the base 41. I'm coming. In the assembled state of the mounting structure X2, one end of the conductive connecting portion 42 is in contact with the land electrode 22d of the build-up wiring board 20, and the other end is in contact with the electrode portion 31 of the motherboard 30.
[0042]
In the mounting structure X2, similarly to the mounting structure X1, the difference in the coefficient of thermal expansion in the plane spreading direction of the semiconductor chip 10 and the build-up wiring board 20 is 1.5 to 7 ppm / K. Such a difference in the coefficient of thermal expansion is smaller than the difference in the coefficient of thermal expansion (about 11.5 to 17 ppm) in the conventional general semiconductor chip-build-up wiring board mounting structure. Therefore, also in the mounting structure X2, similarly to the mounting structure X1, a decrease in connection reliability between the semiconductor chip 10 and the build-up wiring board 20 due to a change in environmental temperature can be reduced as compared with the related art.
[0043]
Further, in the mounting structure X2, similarly to the mounting structure X1, the difference in the coefficient of thermal expansion in the planar spreading direction of the build-up wiring board 20 and the mother board 30 is relatively large, 5 to 13 ppm / K. However, the land electrode 22d of the build-up wiring board 20 is in contact with the conductive connection part 42 of the buffer part 40 and is not joined. At the same time, the electrode portions 31 of the mother substrate 30 are in contact with the conductive connecting portions 42 and are not joined. Therefore, in the mounting structure X2, similarly to the mounting structure X1, the build-up wiring board 20, the mother board 30, and the buffer section 40 expand to a different degree with a relatively large difference according to a change in environmental temperature. Even when the land electrode 22d and the electrode portion 31 and the conductive contact portion 42 maintain an appropriate contact state, it is possible to achieve good connection reliability between the build-up wiring board 20 and the mother board 30. it can.
[0044]
In the present embodiment, the conductive connecting portion 42 and the electrode portion 31 may be joined via, for example, a conductive adhesive or a solder material. In this case, since the conductive connecting portion 42 is held by the base 41 which is a flexible substrate, a part of the stress that may occur between the electrode portion and the conductive connecting portion is absorbed by the relatively soft base 41. Therefore, even in the case where the conductive contact portion 42 and the electrode portion 31 are joined in the present embodiment, good connection reliability between the build-up wiring board 20 and the mother board 30 can be achieved.
[0045]
As described above, in the mounting structure X2, similarly to the mounting structure X1, good connection reliability between the semiconductor chip 10 and the build-up wiring board 20 is achieved, and the build-up wiring board 20 and the mother board 30 are connected. It is possible to achieve good connection reliability between the two.
[0046]
【Example】
<Preparation of mounting structure>
A carbon fiber cloth (trade name: TORAYCA, manufactured by Toray) was impregnated with an epoxy resin and then dried to prepare a prepreg having a thickness of 0.2 mm. The carbon fiber cloth of the present embodiment is obtained by plain weaving a carbon fiber yarn obtained by bundling carbon fibers having a cross section diameter of 10 μm or less with an average number of 200 or more. Four prepregs thus prepared were laminated, and pressed in a laminating direction at 170 ° C. for 1 hour by a vacuum press to produce an unprocessed core substrate having a thickness of about 0.8 mm.
[0047]
Next, an inner layer pattern and a through-hole via were formed on the core substrate. Specifically, first, a through hole having an opening diameter of 0.5 mm was formed in a predetermined portion of the core substrate by a drill. After the degreasing treatment and the washing treatment, an epoxy resin sheet (thickness: 0.07 mm) in a B-stage state was laminated on both surfaces of the core substrate by a vacuum press at 170 ° C. for 30 minutes. As a result, the epoxy resin coated the core substrate surface and filled the through holes. Next, a through hole having an opening diameter of 0.2 mm was formed in the epoxy resin filled in the through hole by using a drill smaller in diameter than the previous drill. As a result, an insulating film is formed on the surface of the through hole. Next, after performing a desmear treatment, an electroless copper plating film was formed on the surface of the core substrate whose surface was insulated and coated. At this time, an electroless copper plating film was also formed on the surface of the through hole whose surface was insulated. Next, a dry film resist was formed in a predetermined pattern on the surface of the core substrate, and an electrocopper plating film was formed using the previously formed electroless copper plating film as a current-carrying layer while using the resist as a mask. At this time, an electrolytic copper plating film was also formed on the surface of the through hole. After the dry film resist was peeled off, the electroless copper plating film that had been covered with the dry film resist was removed by etching. Thus, an inner layer pattern and a through-hole via were formed on the core substrate. The location and number of through-hole vias are determined according to the layout of the inner layer pattern. In this embodiment, 1000 through-hole vias are formed at predetermined locations on the core substrate.
[0048]
Next, build-up portions were formed on both sides of the core substrate. Specifically, first, a build-up insulating layer was formed on the core substrate on which the inner layer pattern was formed. As a resin material for forming the build-up insulating layer, a photosensitive resin (trade name: PVI-500, manufactured by Taiyo Ink) was used. Next, via holes were formed by photolithography at predetermined positions of the laminated build-up insulating layer. Next, a copper wiring pattern was formed on the insulating layer by a semi-additive method. At this time, a via was formed together with the copper wiring pattern by depositing copper also on the surface of the via hole. Thereafter, a series of steps from lamination formation of the build-up insulating layer to formation of the wiring pattern and via was repeated four times, thereby forming a build-up portion having a five-layer wiring structure on both surfaces of the core substrate.
[0049]
Next, an overcoat layer was formed on the surface of the build-up portion by screen printing and photolithography. An opening was provided at a predetermined portion of the overcoat layer such that a part of the uppermost wiring pattern in the build-up portion faced. Next, a land electrode for connection with an external terminal was formed by forming a gold plating film following the electroless nickel film on the wiring pattern facing the opening. The land electrode formed on one surface of the build-up wiring board is arranged corresponding to the electrode arrangement of a semiconductor chip to be mounted later, and the land electrode formed on the other surface is Are arranged corresponding to the arrangement of the conductive connecting portions of the buffer portion in the socket in which is mounted.
[0050]
When the amount of warpage of the build-up wiring board manufactured in this manner was measured, it was 10 μm or less over a 20 mm span of the chip mounting area. On the other hand, the amount of warpage of the build-up wiring board manufactured by the above process was measured except that the same size organic core board was used instead of the core board of the present embodiment. It was about 30 μm. As the organic core substrate, a substrate whose core substrate was a BT resin substrate was used. As described above, the amount of warpage of the build-up wiring board of the present embodiment was smaller than that of the conventional build-up wiring board employing the organic core. The coefficient of thermal expansion of the build-up wiring board of this example in the plane spreading direction was 7 ppm / K.
[0051]
A predetermined semiconductor chip is flip-chip mounted on one surface of the build-up wiring board according to the present embodiment having a small amount of warpage via a plurality of ball electrodes forming a ball grid array formed on the predetermined semiconductor chip. did. The coefficient of thermal expansion in the plane spreading direction of the semiconductor chip is 5 ppm / K. Next, the semiconductor package thus obtained was mounted on a mother board having a thermal expansion coefficient of 15 ppm / K via a socket for an LGA package. As shown in FIGS. 1 and 2, for example, an LGA package socket includes a socket body for housing a semiconductor package, a socket lid for pressing the semiconductor package against the socket body, and a stiffener for reinforcing a mother board. . The bottom surface of the socket body is constituted by a buffer unit having a conductive connection unit. The conductive connecting portion is disposed at a position where it abuts on the land electrode of the build-up wiring board in the semiconductor package and is electrically connected to the electrode section of the motherboard. The socket lid has a pressing portion for urging the semiconductor package housed in the socket body toward the socket body. While mounting the semiconductor package in the socket main body, the socket main body, the socket lid body, the stiffener, and the mother board were collectively screwed to produce the mounting structure of this embodiment.
[0052]
<Temperature cycle test>
The connection reliability of the mounting structure of this example was examined by a temperature cycle test. Specifically, first, the initial conduction resistance of each electrical connection between the semiconductor chip of the mounting structure and the build-up wiring board and each electrical connection between the build-up wiring board and the mother board are measured. did. Next, after performing a temperature cycle test in the range of -65 ° C to 150 ° C, the conduction resistance of each electrical connection was measured again. In the temperature cycle test, cooling at −65 ° C. for 15 minutes and heating at 150 ° C. for 15 minutes were one cycle, and this cycle was repeated 1000 times. As a result, with respect to the mounting structure of this example, the rate of increase in resistance at each electrical connection was less than 10%, and it was confirmed that a good connection was formed. Also, no cracking or peeling occurred between the ball electrode of the semiconductor chip and the land electrode of the build-up wiring board.
[0053]
[Comparative example]
A mounting structure was produced in the same manner as in the example, except that the semiconductor package including the same build-up wiring board and the semiconductor chip as in the example was mounted on the motherboard via a plurality of solder balls instead of the socket. . Specifically, in this comparative example, the solder ball is melt-bonded to the land electrode of the build-up wiring board in the semiconductor package and also melt-bonded to the electrode portion of the mother board. , Are mechanically and electrically connected to the motherboard via the solder balls. When a temperature cycle test was performed on the mounting structure of this comparative example in the same manner as in the example, the rate of increase in connection resistance at each electrical connection portion exceeded 10% in 300 cycles. At 300 cycles, there was a joint where cracks were observed at the interface between the ball electrode of the semiconductor chip and the land electrode of the build-up wiring board.
[0054]
As a summary of the above, the configuration of the present invention and its variations are listed below as supplementary notes.
[0055]
(Supplementary Note 1) A mother substrate having an electrode portion;
Having a conductive contact portion electrically connected to the electrode portion, a buffer portion mounted on the mother substrate,
A first electrode portion in contact with the conductive connecting portion is provided on a first surface, and a second electrode portion is provided on a second surface opposite to the first surface, and is mounted on the motherboard via the buffer portion. A build-up wiring board,
And a semiconductor chip mounted on the build-up wiring board via a bump portion electrically connected to the second electrode portion.
(Supplementary Note 2) A mother substrate having an electrode portion;
A buffer body having a conductive contact portion electrically connected to the electrode portion, a socket body mounted on the mother board,
A build-up wiring board having a first electrode portion on a first surface in contact with the conductive contact portion and having a second electrode portion on a second surface opposite to the first surface, and electrically connecting to the second electrode portion A semiconductor device including a semiconductor chip mounted on the build-up wiring board via a connected bump portion, and mounted on the motherboard via the socket body;
A socket cover for pressing the semiconductor device against the socket body.
(Supplementary Note 3) The difference in thermal expansion coefficient between the build-up wiring board and the semiconductor chip in the plane spreading direction is 1.5 to 7 ppm / K, and the thermal expansion in the mother board and the build-up wiring board in the plane spreading direction. 3. The mounting structure according to Supplementary Note 1 or 2, wherein the difference between the rates is 5 to 13 ppm / K.
(Supplementary Note 4) The thermal expansion coefficients of the semiconductor chip, the build-up wiring board, and the mother board in the planar spreading direction are 3 to 3.5 ppm / K, 5 to 10 ppm / K, and 15 to 18 ppm, respectively. 4. The mounting structure according to any one of supplementary notes 1 to 3, wherein
(Supplementary note 5) The mounting structure according to any one of Supplementary notes 1 to 4, wherein the bump portion is a plurality of ball electrodes provided in a grid array between the build-up wiring board and the semiconductor chip. body.
(Supplementary note 6) The mounting structure according to any one of supplementary notes 1 to 5, wherein an underfill material is interposed between the build-up wiring board and the semiconductor chip. (Supplementary Note 7) The build-up wiring board has a core substrate, and the core substrate has a plurality of carbon fiber cloths woven from carbon fiber yarns in which carbon fibers having a diameter of 10 μm or less are bundled at a thickness of 100 μm or less. 7. The mounting structure according to Supplementary Notes 1 to 6, wherein a through-hole via is provided in a through-hole that is buried at a distance in a direction and penetrates in a thickness direction and has an insulating film formed on a surface thereof.
(Supplementary Note 8) The buffer according to any one of Supplementary Notes 1 to 7, wherein the buffer unit includes a flexible substrate that holds the conductive connecting unit, and the conductive connecting unit faces both surfaces of the flexible substrate. Mounting structure.
(Supplementary Note 9) The mounting structure according to any one of Supplementary Notes 1 to 8, wherein the first electrode unit is a plurality of land electrodes provided in a grid array on the first surface.
[0056]
【The invention's effect】
According to the present invention, in a mounting structure in which a semiconductor device including a build-up wiring board and a semiconductor chip mounted on the flip-chip is mounted on a mother board, electrical connection between the semiconductor chip and the build-up wiring board In addition to achieving high reliability, it is possible to achieve high reliability for the electrical connection between the build-up wiring board and the motherboard. By employing such a mounting structure according to the present invention, it is possible to appropriately cope with high-density mounting of electronic components incorporated in an electronic device.
[Brief description of the drawings]
FIG. 1 is an exploded perspective view of a mounting structure according to a first embodiment of the present invention.
FIG. 2 is a partial cross-sectional view of the mounting structure taken along line II-II in FIG.
FIG. 3 is a partially enlarged view of FIG. 2;
FIG. 4 is a partial cross-sectional view of a mounting structure according to a second embodiment of the present invention.
FIG. 5 is a partially enlarged view of FIG. 4;
[Explanation of symbols]
X1, X2 mounting structure
10 Semiconductor chip
11 ball electrode
20 Build-up wiring board
21 Core substrate
22 Build-up part
22d, 22e Land electrode
30 Mother board
31 Electrode section
40 buffer section
41 base
42 conductive contact
51 Socket body
52 Socket cover
52a Pressure contact part

Claims (5)

A mother substrate having an electrode portion,
Having a conductive contact portion electrically connected to the electrode portion, a buffer portion mounted on the mother substrate,
A first electrode portion in contact with the conductive connecting portion is provided on a first surface, and a second electrode portion is provided on a second surface opposite to the first surface, and is mounted on the motherboard via the buffer portion. A build-up wiring board,
And a semiconductor chip mounted on the build-up wiring board via a bump portion electrically connected to the second electrode portion. A mother substrate having an electrode portion,
A buffer body having a conductive contact portion electrically connected to the electrode portion, a socket body mounted on the mother board,
A build-up wiring board having a first electrode portion on a first surface in contact with the conductive contact portion and having a second electrode portion on a second surface opposite to the first surface, and electrically connecting to the second electrode portion A semiconductor device including a semiconductor chip mounted on the build-up wiring board via a connected bump portion, and mounted on the motherboard via the socket body;
A socket cover for pressing the semiconductor device against the socket body. The difference in the coefficient of thermal expansion between the build-up wiring board and the semiconductor chip in the plane spreading direction is 1.5 to 7 ppm / K. The mounting structure according to claim 1, wherein the difference is 5 to 13 ppm / K. The mounting structure according to any one of claims 1 to 3, wherein the buffer unit has a flexible substrate that holds the conductive connecting portion, and the conductive connecting portion faces both surfaces of the flexible substrate. . The mounting structure according to claim 1, wherein the first electrode unit is a plurality of land electrodes provided in a grid array on the first surface.

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