JP2004047938A - Method for manufacturing semiconductor device and semiconductor device - Google Patents

Method for manufacturing semiconductor device and semiconductor device Download PDF

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Publication number
JP2004047938A
JP2004047938A JP2003042671A JP2003042671A JP2004047938A JP 2004047938 A JP2004047938 A JP 2004047938A JP 2003042671 A JP2003042671 A JP 2003042671A JP 2003042671 A JP2003042671 A JP 2003042671A JP 2004047938 A JP2004047938 A JP 2004047938A
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semiconductor element
chip
semiconductor device
flip
conductive
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Yohei Kurashima
倉島　羊平
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Seiko Epson Corp
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Seiko Epson Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To easily and surely perform processing following through-hole formation. <P>SOLUTION: A bump 21 on the surface side of an IC chip 20 is flip chip mounted on a pad 11 of a base board 10, a through-hole 22 is formed from the rear side of the IC chip 20 up to the bump 21, a conductive via 25 is formed in the through-hole 22, a bump 21 for a succeeding IC chip 20 is flip chip mounted on the conductive via 25. Thus the formation of the through-hole 22 and the formation of the conductive via 25 are successively performed to stack the succeeding IC chip 20. Since processing associated with through-hole formation is applied to the stacked IC chip 20, as different from conventional processing, the strength or the like of the thinned IC chip 20 can be secured. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、ＩＣチップ等の半導体素子を積層してパッケージにする半導体装置の製造方法及び半導体装置に関する。
【０００２】
【従来の技術】
従来より、ＩＣチップ等の半導体素子を積層する場合、たとえば図７に示す方法が知られている。すなわち、図７（ａ）に示すＡｌパッド２を有するＩＣチップ１に対し、図７（ｂ）に示すように、Ｄｉｃｉｎｇ　Ｂｅｆｏｒｅ　Ｇｒｉｄｉｎｇ　の技術を使用してたとえば５０μｍ厚に薄型化する。次いで、図７（ｃ）に示すように、Ａｌパッド２の導電化処理により導電膜３を形成する。導電化処理に際しては、無電解Ｎｉ／Ａｕメッキによる処理が行われる。
【０００３】
導電化処理が行われた後、図７（ｄ）に示すように、レーザ加工により、ＩＣチップ１の裏面からＡｌパッド２に到達するまで貫通させたスルーホール４を形成する。スルーホール４が形成されると、図７（ｅ）に示すように、ＩＣチップ１の裏面及びスルーホール４に絶縁膜５を形成する。絶縁膜５が形成されると、図７（ｆ）に示すように、ＩＣチップ１の裏面からＡｌパッド２に到達するまで貫通させた貫通孔６を形成した後、図７（ｇ）に示すように、貫通孔６に導電樹脂７を充填する。
【０００４】
このようにして形成されたＩＣチップ１は、図７（ｈ）に示すように、下方のＩＣチップ１のＡｌパッド２上の導電膜３及び上方のＩＣチップ１の導電樹脂７間を、半田材又は導電接着剤による導電材８を介して導通をとることで、積層される。このようなＩＣチップ１の積層が行われると、最後に図７（ｉ）に示すように、たとえば最下方のＩＣチップ１の導電樹脂７の部分に半田ボール９を付けた後、パッケージングされる。
【０００５】
【発明が解決しようとする課題】
ところで、上述した半導体装置の積層方法では、たとえば５０μｍ厚に薄型化された個々のＩＣチップ１にスルーホール４を形成し、そのスルーホール４に絶縁膜５を形成し、さらに貫通孔６を形成してその貫通孔６に導電樹脂７を充填した後、導電材８を介してＩＣチップ１を積層するようにしている。つまり、積層される前に個々のＩＣチップ１にスルーホール化に伴う処理を行うようにしているため、薄型化されたＩＣチップ１の強度等の点から、その処理が困難となるものと考えられる。
【０００６】
本発明は、このような状況に鑑みてなされたものであり、スルーホール化に伴う処理を容易かつ確実に行うことができる半導体装置の製造方法及び半導体装置を提供することができるようにするものである。
【０００７】
【課題を解決するための手段】
本発明の半導体装置の製造方法は、ベース部材の電極に半導体素子の表面側のバンプをフリップチップ実装する工程と、半導体素子の裏面側からバンプに到達するまでスルーホールを形成する工程と、スルーホールに導電ビアを形成する工程とを有し、導電ビアに次の半導体素子のバンプをフリップチップ実装するとともに、スルーホールの形成と導電ビアの形成とを行って順次、次の半導体素子を積層することを特徴とする。
【０００８】
また、本発明の半導体装置の製造方法は、スルーホールに絶縁材を充填させる工程と、半導体素子の裏面側からバンプに到達するまで充填させた絶縁材に孔を形成する工程とを有するようにすることができる。
【０００９】
また、本発明の半導体装置の製造方法は、半導体素子のフリップチップ実装後、半導体素子の裏面側を研削し、半導体素子の厚みを薄くする工程を有するようにすることができる。
【００１０】
また、本発明の半導体装置の製造方法は、半導体素子のフリップチップ実装時、比熱の高い材料、融点の高い材料、透過率の低い材料の少なくとも一つの材料を介して接続する工程を有するようにすることができる。
【００１１】
また、本発明の半導体装置の製造方法は、半導体素子のフリップチップ実装時、ベース部材との間及び半導体素子との間に接着剤を充填させる工程を有するようにすることができる。
【００１２】
また、本発明の半導体装置の製造方法は、最上方の半導体素子の裏面側に導電ビアに導通する導電膜を形成する工程と、導電膜に異種の半導体素子のバンプを接続する工程とを有するようにすることができる。
【００１３】
また、本発明の半導体装置の製造方法は、ベース部材に、ワイヤーボンディングされた半導体素子を実装する工程を有するようにすることができる。
【００１４】
また、本発明の半導体装置の製造方法は、ベース部材は、基板又は半導体素子であるようにすることができる。
【００１５】
本発明の半導体装置は、ベース部材と、ベース部材の電極に導電ビアに導通するバンプがフリップチップ実装された半導体素子と、導電ビア及びこの導電ビアに導通するバンプを有する他の複数の半導体素子とを備え、他の半導体素子が導電ビアに対するバンプの導通がとられるように順次フリップチップ実装されてなることを特徴とする。
【００１６】
また、本発明の半導体装置は、半導体素子のフリップチップ実装後、半導体素子の裏面側が研削され、半導体素子の厚みが薄くされているようにすることができる。
【００１７】
また、本発明の半導体装置は、半導体素子は、比熱の高い材料、融点の高い材料、透過率の低い材料の少なくとも一つの材料を介してフリップチップ実装されているようにすることができる。
【００１８】
また、本発明の半導体装置は、ベース部材との間及び半導体素子との間に接着剤が充填されているようにすることができる。
【００１９】
また、本発明の半導体装置は、最上方の半導体素子の裏面側に導電ビアに導通する導電膜が形成され、導電膜に異種の半導体素子のバンプが接続されているようにすることができる。
【００２０】
また、本発明の半導体装置は、ベース部材に、ワイヤーボンディングされた半導体素子が実装されているようにすることができる。
【００２１】
また、本発明の半導体装置は、ベース部材は、基板又は半導体素子であるようにすることができる。
【００２２】
本発明の半導体装置の製造方法及び半導体装置は、ベース部材の電極に半導体素子の表面側のバンプをフリップチップ実装し、半導体素子の裏面側からバンプに到達するまでスルーホールを形成し、スルーホールに導電ビアを形成するとともに、導電ビアに次の半導体素子のバンプをフリップチップ実装し、スルーホールの形成と導電ビアの形成とを行って順次、次の半導体素子を積層するようにする。
【００２３】
【発明の実施の形態】
以下、本発明の実施の形態について説明する。
【００２４】
図１は、本発明の半導体装置の製造方法の一実施の形態を示す図、図２〜図６は、他の半導体装置の製造方法を説明するための図である。
【００２５】
まず、図１（ａ）に示すように、たとえばベース基板１０のパッド１１に、半導体素子としてのＩＣチップ２０の表面側のバンプ２１をたとえば半田１２を介してフリップチップ実装する。ここで、半田１２は、後述のレーザ加工等による耐熱性のよいものが好ましく、比熱の高い材料、融点が高い材料、透過率の低い材料を用いることができ、例えば鉛フリー半田等がある。また、ベース基板１０とＩＣチップ２０との間に接着剤１３を充填することで、ベース基板１０とＩＣチップ２０との熱膨張率差に起因する応力による影響が避けられる。
【００２６】
なお、ベース基板１０の代りにＩＣチップを用いるようにしてもよい。また、ベース基板１０にＩＣチップ２０をフリップチップ実装した後、ＩＣチップ２０の裏面側を研削し、ＩＣチップ２０の厚みを薄くすることもできる。このように、ＩＣチップ２０の厚みを薄くすることで、後述のスルーホール２２の形成を容易に行うことができる。また、半導体素子としては、ウェハとしてもよい。
【００２７】
次いで、図１（ｂ）に示すように、ＩＣチップ２０の裏面側からバンプ２１に到達するまでレーザ加工等によってスルーホール２２を形成した後、図１（ｃ）に示すように、ＩＣチップ２０の裏面及びスルーホール２２に絶縁樹脂２３を塗布及び充填させる。
【００２８】
次いで、図１（ｄ）に示すように、ＩＣチップ２０の裏面側からバンプ２１に到達するまでレーザ加工等によって孔２４を形成した後、図１（ｅ）に示すように、その孔２４に導電ビア２５を形成する。導電ビア２５の形成に際しては、Ａｕ粒子等をインクジェット吐出技術を用いてもよい。
【００２９】
次いで、図１（ｆ）に示すように、次のＩＣチップ２０のバンプ２１を先のＩＣチップ２０の導電ビア２５に接続することで、先のＩＣチップ２０上に次のＩＣチップ２０を積層する。その後、図１（ｂ）〜図１（ｅ）に示した手順で次のＩＣチップ２０に導電ビア２５を形成し、同様に次のＩＣチップ２０にさらに次のＩＣチップ２０を積層する。
【００３０】
以上のような手順により、たとえば図１（ｇ）に示すように、ベース基板１０上にたとえば４個のＩＣチップ２０を積層することができる。
【００３１】
このように本実施の形態では、ベース基板１０のパッド１１にＩＣチップ２０の表面側のバンプ２１をフリップチップ実装し、ＩＣチップ２０の裏面側からバンプ２１に到達するまでスルーホール２２を形成し、スルーホール２２に導電ビア２５を形成するとともに、導電ビア２５に次のＩＣチップ２０のバンプ２１をフリップチップ実装し、スルーホール２２の形成と導電ビア２５の形成とを行って順次、次のＩＣチップ２０を積層するようにした。つまり、従来とは異なり、積層された後にＩＣチップ２０にスルーホール化に伴う処理を行うようにしているため、薄型化されたＩＣチップ２０の強度等を確保することができることから、スルーホール化に伴う処理を容易かつ確実に行うことができる。
【００３２】
なお、本実施の形態では、ベース基板１０上に４個のＩＣチップ２０を積層した場合について説明したが、この例に限らず、３個以下、５個以上であってもよい。
【００３３】
また、本実施の形態では、ベース基板１０上に同種のＩＣチップ２０を積層する場合について説明したが、この例に限らず、たとえば図２に示すように、ＩＣチップ２０上に異種のＩＣチップ３０を積層することも可能である。この場合、ＩＣチップ２０の導電ビア２５に導通する導電膜２６を形成し、その導電膜２６に異種のＩＣチップ３０のバンプ３１を接続するようにする。また、ＩＣチップ２０とＩＣチップ３０との間に接着剤２７を充填することでＩＣチップ２０とＩＣチップ３０との熱膨張率差に起因する応力による影響が避けられる。
【００３４】
また、図３に示すように、積層したＩＣチップ２０のうち、最下方のＩＣチップ２０の導電ビア２５に導電膜２７ａを形成し、その導電膜２７ａに半田ボール２８を付けることで、ＷＣＳＰ（Ｗａｆｅｒ　ｌｅｖｅｌ　Ｃｈｉｐ　Ｓｉｚｅ　Ｐａｃｋａｇｅ）　に積層することも可能である。
【００３５】
また、図４に示すように、ベース基板１０上にたとえば４個のＩＣチップ２０を積層するとともに、ベース基板１０に導電膜２７ａ，２９を形成し、その導電膜２７ａに半田ボール２８を付けることで、インターポーザに積層化することも可能である。
【００３６】
また、図５に示すように、ベース基板１０にＩＣチップ４０をワイヤー４１により接続して実装させる実装工程を混在させることもできる。この場合、ＩＣチップ４０のバンプ４２と導電膜２７ｃとをワイヤー４１により接続する。また、導電膜２７ｃは、導電膜２７ａ，２７ｂを介して半田ボール２８と導通がとられるようにする。
【００３７】
また、図６に示すように、ベース基板１０上のＩＣチップ４０のバンプ４３と最上方のＩＣチップ２０の導電ビア２５とをワイヤー４４により接続させる実装工程を混在させることもできる。
【００３８】
【発明の効果】
以上の如く本発明に係る半導体装置の製造方法及び半導体装置によれば、ベース部材の電極に半導体素子の表面側のバンプをフリップチップ実装し、半導体素子の裏面側からバンプに到達するまでスルーホールを形成し、スルーホールに導電ビアを形成するとともに、導電ビアに次の半導体素子のバンプをフリップチップ実装し、スルーホールの形成と導電ビアの形成とを行って順次、次の半導体素子を積層するようにしたので、スルーホール化に伴う処理を容易かつ確実に行うことができる。
【図面の簡単な説明】
【図１】本発明の半導体装置の製造方法の一実施の形態を示す図である。
【図２】他の半導体装置の製造方法を説明するための図である。
【図３】他の半導体装置の製造方法を説明するための図である。
【図４】他の半導体装置の製造方法を説明するための図である。
【図５】他の半導体装置の製造方法を説明するための図である。
【図６】他の半導体装置の製造方法を説明するための図である。
【図７】従来の半導体装置の製造方法の一例を説明するための図である。
【符号の説明】
１０　ベース基板
１１　パッド
１２　半田
１３，２７　接着剤
２０，３０，４０　ＩＣチップ
２１，３１，４２，４３　バンプ
２２　スルーホール
２３　絶縁樹脂
２５　導電ビア
２６，２７ａ，２７ｂ，２９　導電膜
２８　半田ボール
４１，４４　ワイヤー[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device manufacturing method and a semiconductor device in which a semiconductor element such as an IC chip is stacked and packaged.
[0002]
[Prior art]
Conventionally, when semiconductor elements such as IC chips are stacked, for example, a method shown in FIG. 7 is known. That is, as shown in FIG. 7B, the thickness of the IC chip 1 having the Al pad 2 shown in FIG. 7A is reduced to, for example, a 50 μm thickness by using a dicing before gridding technique. Next, as shown in FIG. 7C, a conductive film 3 is formed by conducting the Al pad 2 into a conductive state. At the time of the conductive treatment, a treatment by electroless Ni / Au plating is performed.
[0003]
After the conducting process is performed, as shown in FIG. 7D, through holes 4 penetrating from the back surface of the IC chip 1 to the Al pads 2 are formed by laser processing. When the through hole 4 is formed, an insulating film 5 is formed on the back surface of the IC chip 1 and the through hole 4 as shown in FIG. When the insulating film 5 is formed, as shown in FIG. 7F, a through hole 6 penetrating from the back surface of the IC chip 1 to reach the Al pad 2 is formed, and then as shown in FIG. As described above, the through holes 6 are filled with the conductive resin 7.
[0004]
As shown in FIG. 7 (h), the IC chip 1 thus formed is connected between the conductive film 3 on the Al pad 2 of the lower IC chip 1 and the conductive resin 7 of the upper IC chip 1 by soldering. The layers are laminated by conducting through the conductive material 8 made of a material or a conductive adhesive. When such IC chips 1 are stacked, finally, as shown in FIG. 7 (i), for example, solder balls 9 are attached to the conductive resin 7 of the lowermost IC chip 1 and then packaged. You.
[0005]
[Problems to be solved by the invention]
By the way, in the above-described lamination method of a semiconductor device, a through hole 4 is formed in each IC chip 1 thinned to a thickness of, for example, 50 μm, an insulating film 5 is formed in the through hole 4, and a through hole 6 is further formed. After filling the through holes 6 with the conductive resin 7, the IC chips 1 are stacked via the conductive material 8. In other words, since the processing for forming the through holes is performed on the individual IC chips 1 before they are stacked, it is considered that the processing becomes difficult in terms of the strength of the thinned IC chips 1 and the like. Can be
[0006]
The present invention has been made in view of such a situation, and provides a method of manufacturing a semiconductor device and a semiconductor device capable of easily and reliably performing a process associated with forming a through hole. It is.
[0007]
[Means for Solving the Problems]
The method of manufacturing a semiconductor device according to the present invention includes a step of flip-chip mounting a bump on a front surface side of a semiconductor element on an electrode of a base member, a step of forming a through hole from the back side of the semiconductor element to reach the bump, Forming a conductive via in the hole, flip-chip mounting a bump of the next semiconductor element in the conductive via, forming a through hole and forming a conductive via, and sequentially stacking the next semiconductor element It is characterized by doing.
[0008]
Further, the method for manufacturing a semiconductor device of the present invention includes a step of filling the through hole with an insulating material and a step of forming a hole in the filled insulating material until reaching the bump from the back surface side of the semiconductor element. can do.
[0009]
Further, the method of manufacturing a semiconductor device according to the present invention may include a step of grinding the back surface side of the semiconductor element after flip-chip mounting the semiconductor element to reduce the thickness of the semiconductor element.
[0010]
Further, the method for manufacturing a semiconductor device of the present invention includes a step of connecting via at least one of a material having a high specific heat, a material having a high melting point, and a material having a low transmittance when flip-chip mounting a semiconductor element. can do.
[0011]
In addition, the method of manufacturing a semiconductor device according to the present invention may include a step of filling an adhesive between the semiconductor element and the base member and between the semiconductor element and the semiconductor element when flip-chip mounting the semiconductor element.
[0012]
Further, the method of manufacturing a semiconductor device according to the present invention includes a step of forming a conductive film that is conductive to a conductive via on the back surface side of the uppermost semiconductor element, and a step of connecting a bump of a different kind of semiconductor element to the conductive film. You can do so.
[0013]
In addition, the method of manufacturing a semiconductor device according to the present invention may include a step of mounting a wire-bonded semiconductor element on a base member.
[0014]
In the method for manufacturing a semiconductor device according to the present invention, the base member may be a substrate or a semiconductor element.
[0015]
The semiconductor device of the present invention includes a base member, a semiconductor element in which a bump conducting to a conductive via is connected to an electrode of the base member by flip-chip mounting, and a plurality of other semiconductor elements having a conductive via and a bump conducting to the conductive via. And the other semiconductor elements are sequentially flip-chip mounted so that the bumps are electrically connected to the conductive vias.
[0016]
Further, in the semiconductor device of the present invention, after the semiconductor element is flip-chip mounted, the back surface side of the semiconductor element can be ground to reduce the thickness of the semiconductor element.
[0017]
Further, in the semiconductor device of the present invention, the semiconductor element can be flip-chip mounted via at least one of a material having a high specific heat, a material having a high melting point, and a material having a low transmittance.
[0018]
In the semiconductor device of the present invention, an adhesive may be filled between the base member and the semiconductor element.
[0019]
Further, in the semiconductor device of the present invention, a conductive film that is connected to the conductive via may be formed on the back surface side of the uppermost semiconductor element, and bumps of different kinds of semiconductor elements may be connected to the conductive film.
[0020]
Further, in the semiconductor device of the present invention, a wire-bonded semiconductor element can be mounted on the base member.
[0021]
Further, in the semiconductor device of the present invention, the base member can be a substrate or a semiconductor element.
[0022]
The method for manufacturing a semiconductor device and the semiconductor device according to the present invention include flip-chip mounting a bump on a front surface of a semiconductor element on an electrode of a base member, forming a through hole from the back side of the semiconductor element to the bump, A conductive via is formed on the conductive via, a bump of the next semiconductor element is flip-chip mounted on the conductive via, a through hole is formed and a conductive via is formed, and the next semiconductor element is sequentially stacked.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
[0024]
FIG. 1 is a view showing one embodiment of a method of manufacturing a semiconductor device according to the present invention, and FIGS. 2 to 6 are views for explaining a method of manufacturing another semiconductor device.
[0025]
First, as shown in FIG. 1A, bumps 21 on the front side of an IC chip 20 as a semiconductor element are flip-chip mounted on, for example, pads 11 of a base substrate 10 via solder 12, for example. Here, the solder 12 preferably has good heat resistance by laser processing or the like described later, and a material having a high specific heat, a material having a high melting point, or a material having a low transmittance can be used, and examples thereof include lead-free solder. Further, by filling the adhesive 13 between the base substrate 10 and the IC chip 20, the influence of the stress caused by the difference in the coefficient of thermal expansion between the base substrate 10 and the IC chip 20 can be avoided.
[0026]
Note that an IC chip may be used instead of the base substrate 10. Further, after the IC chip 20 is flip-chip mounted on the base substrate 10, the back surface side of the IC chip 20 can be ground to reduce the thickness of the IC chip 20. As described above, by reducing the thickness of the IC chip 20, a later-described through hole 22 can be easily formed. Further, the semiconductor element may be a wafer.
[0027]
Next, as shown in FIG. 1B, a through hole 22 is formed by laser processing or the like from the back surface side of the IC chip 20 to the bump 21 and then, as shown in FIG. The insulating resin 23 is applied and filled on the back surface of the substrate and the through hole 22.
[0028]
Next, as shown in FIG. 1D, a hole 24 is formed by laser processing or the like from the back surface side of the IC chip 20 to reach the bump 21, and then, as shown in FIG. A conductive via 25 is formed. When forming the conductive vias 25, an inkjet discharge technique for Au particles or the like may be used.
[0029]
Next, as shown in FIG. 1F, the next IC chip 20 is stacked on the previous IC chip 20 by connecting the bump 21 of the next IC chip 20 to the conductive via 25 of the previous IC chip 20. I do. Thereafter, a conductive via 25 is formed in the next IC chip 20 by the procedure shown in FIGS. 1B to 1E, and the next IC chip 20 is further laminated on the next IC chip 20 in the same manner.
[0030]
By the above-described procedure, for example, as shown in FIG. 1G, for example, four IC chips 20 can be stacked on the base substrate 10.
[0031]
As described above, in the present embodiment, the bumps 21 on the front surface side of the IC chip 20 are flip-chip mounted on the pads 11 of the base substrate 10, and the through holes 22 are formed from the back surface side of the IC chip 20 until the bumps 21 are reached. Then, the conductive via 25 is formed in the through hole 22, the bump 21 of the next IC chip 20 is flip-chip mounted on the conductive via 25, and the formation of the through hole 22 and the formation of the conductive via 25 are sequentially performed. The IC chips 20 were stacked. In other words, unlike the conventional case, since the IC chip 20 is subjected to the processing associated with the through hole after being stacked, the strength and the like of the thinned IC chip 20 can be ensured. Can be easily and reliably performed.
[0032]
In the present embodiment, the case where four IC chips 20 are stacked on the base substrate 10 has been described. However, the present invention is not limited to this example, and three or less IC chips 20 may be used.
[0033]
In this embodiment, the case where the same type of IC chip 20 is stacked on the base substrate 10 has been described. However, the present invention is not limited to this example. For example, as shown in FIG. It is also possible to stack 30. In this case, a conductive film 26 conducting to the conductive via 25 of the IC chip 20 is formed, and the bump 31 of the IC chip 30 of a different kind is connected to the conductive film 26. Further, by filling the adhesive 27 between the IC chip 20 and the IC chip 30, the influence of the stress caused by the difference in the coefficient of thermal expansion between the IC chip 20 and the IC chip 30 can be avoided.
[0034]
As shown in FIG. 3, a conductive film 27a is formed in the conductive via 25 of the lowermost IC chip 20 of the stacked IC chips 20, and a solder ball 28 is attached to the conductive film 27a, so that the WCSP ( It can also be laminated on a Wafer level Chip Size Package.
[0035]
Further, as shown in FIG. 4, for example, four IC chips 20 are stacked on the base substrate 10, and conductive films 27a and 29 are formed on the base substrate 10, and solder balls 28 are attached to the conductive film 27a. Thus, it is also possible to stack the layers on the interposer.
[0036]
Further, as shown in FIG. 5, a mounting step of connecting and mounting the IC chip 40 to the base substrate 10 by the wires 41 can be mixed. In this case, the bump 42 of the IC chip 40 and the conductive film 27c are connected by the wire 41. Further, the conductive film 27c is made to be conductive with the solder ball 28 via the conductive films 27a and 27b.
[0037]
Further, as shown in FIG. 6, a mounting process of connecting the bump 43 of the IC chip 40 on the base substrate 10 and the conductive via 25 of the uppermost IC chip 20 by the wire 44 can be mixed.
[0038]
【The invention's effect】
As described above, according to the method for manufacturing a semiconductor device and the semiconductor device according to the present invention, the bumps on the front side of the semiconductor element are flip-chip mounted on the electrodes of the base member, and the through holes are formed from the back side of the semiconductor element to the bumps. Then, a conductive via is formed in the through hole, and a bump of the next semiconductor element is flip-chip mounted on the conductive via, a through hole is formed, and a conductive via is formed. Therefore, it is possible to easily and reliably perform the processing associated with the formation of the through hole.
[Brief description of the drawings]
FIG. 1 is a diagram showing one embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 2 is a drawing for explaining another method of manufacturing a semiconductor device.
FIG. 3 is a diagram for explaining a method for manufacturing another semiconductor device.
FIG. 4 is a diagram for explaining another method of manufacturing a semiconductor device.
FIG. 5 is a diagram for explaining another method of manufacturing a semiconductor device.
FIG. 6 is a view illustrating a method for manufacturing another semiconductor device.
FIG. 7 is a diagram illustrating an example of a conventional method for manufacturing a semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Base board 11 Pad 12 Solder 13, 27 Adhesive 20, 30, 40 IC chip 21, 31, 42, 43 Bump 22 Through hole 23 Insulating resin 25 Conductive via 26, 27a, 27b, 29 Conductive film 28 Solder ball 41, 44 wires

Claims (15)

ベース部材の電極に半導体素子の表面側のバンプをフリップチップ実装する工程と、
前記半導体素子の裏面側から前記バンプに到達するまでスルーホールを形成する工程と、
前記スルーホールに導電ビアを形成する工程と
を有し、
前記導電ビアに次の半導体素子のバンプをフリップチップ実装するとともに、前記スルーホールの形成と前記導電ビアの形成とを行って順次、次の半導体素子を積層することを特徴とする半導体装置の製造方法。A step of flip-chip mounting a bump on the front side of the semiconductor element on the electrode of the base member,
Forming a through hole from the back side of the semiconductor element to reach the bump;
Forming a conductive via in the through hole,
Manufacturing the semiconductor device, flip-chip mounting a bump of the next semiconductor element on the conductive via, forming the through hole and forming the conductive via, and sequentially stacking the next semiconductor element. Method. 前記スルーホールに絶縁材を充填させる工程と、
前記半導体素子の裏面側から前記バンプに到達するまで前記充填させた絶縁材に孔を形成する工程とを有する
ことを特徴とする請求項１に記載の半導体装置の製造方法。A step of filling the through hole with an insulating material,
Forming a hole in the filled insulating material from the back side of the semiconductor element to reach the bump. 前記半導体素子のフリップチップ実装後、前記半導体素子の裏面側を研削し、前記半導体素子の厚みを薄くする工程を有することを特徴とする請求項１又は２に記載の半導体装置の製造方法。3. The method according to claim 1, further comprising, after flip-chip mounting the semiconductor element, grinding a back surface side of the semiconductor element to reduce a thickness of the semiconductor element. 前記半導体素子のフリップチップ実装時、比熱の高い材料、融点の高い材料、透過率の低い材料の少なくとも一つの材料を介して接続する工程を有することを特徴とする請求項１〜３の何れかに記載の半導体装置の製造方法。The flip chip mounting of the semiconductor element, comprising a step of connecting via at least one of a material having a high specific heat, a material having a high melting point, and a material having a low transmittance. 13. The method for manufacturing a semiconductor device according to claim 1. 前記半導体素子のフリップチップ実装時、前記ベース部材との間及び前記半導体素子との間に接着剤を充填させる工程を有することを特徴とする請求項１〜４の何れかに記載の半導体装置の製造方法。5. The semiconductor device according to claim 1, further comprising a step of filling an adhesive between the semiconductor element and the base member and between the semiconductor element and the semiconductor element when flip-chip mounting the semiconductor element. 6. Production method. 最上方の前記半導体素子の裏面側に前記導電ビアに導通する導電膜を形成する工程と、
前記導電膜に異種の半導体素子のバンプを接続する工程とを有する
ことを特徴とする請求項１〜５の何れかに記載の半導体装置の製造方法。Forming a conductive film conducting to the conductive via on the back surface side of the uppermost semiconductor element;
6. The method of manufacturing a semiconductor device according to claim 1, further comprising: connecting a bump of a different kind of semiconductor element to the conductive film. 前記ベース部材に、ワイヤーボンディングされた半導体素子を実装する工程を有することを特徴とする請求項１〜５の何れかに記載の半導体装置の製造方法。6. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of mounting a wire-bonded semiconductor element on said base member. 前記ベース部材は、基板又は半導体素子であることを特徴とする請求項１〜７の何れかに記載の半導体装置の製造方法。The method according to claim 1, wherein the base member is a substrate or a semiconductor element. ベース部材と、
前記ベース部材の電極に導電ビアに導通するバンプがフリップチップ実装された半導体素子と、
導電ビア及びこの導電ビアに導通するバンプを有する他の複数の半導体素子とを備え、
前記他の半導体素子が前記導電ビアに対する前記バンプの導通がとられるように順次フリップチップ実装されてなることを特徴とする半導体装置。A base member,
A semiconductor element in which a bump conducting to a conductive via is flip-chip mounted on an electrode of the base member,
Comprising a plurality of semiconductor elements having conductive vias and bumps that are conductive to the conductive vias,
A semiconductor device, wherein the other semiconductor elements are sequentially flip-chip mounted so that the bumps are electrically connected to the conductive vias. 前記半導体素子のフリップチップ実装後、前記半導体素子の裏面側が研削され、前記半導体素子の厚みが薄くされていることを特徴とする請求項９に記載の半導体装置。10. The semiconductor device according to claim 9, wherein after flip-chip mounting the semiconductor element, the back surface side of the semiconductor element is ground to reduce the thickness of the semiconductor element. 前記半導体素子は、比熱の高い材料、融点の高い材料、透過率の低い材料の少なくとも一つの材料を介して前記フリップチップ実装されていることを特徴とする請求項９又は１０に記載の半導体装置。11. The semiconductor device according to claim 9, wherein the semiconductor element is mounted on the flip chip via at least one of a material having a high specific heat, a material having a high melting point, and a material having a low transmittance. . 前記ベース部材との間及び前記半導体素子との間に接着剤が充填されていることを特徴とする請求項９〜１１の何れかに記載の半導体装置。The semiconductor device according to any one of claims 9 to 11, wherein an adhesive is filled between the base member and the semiconductor element. 最上方の前記半導体素子の裏面側に前記導電ビアに導通する導電膜が形成され、前記導電膜に異種の半導体素子のバンプが接続されていることを特徴とする請求項９〜１２の何れかに記載の半導体装置。13. The semiconductor device according to claim 9, wherein a conductive film that is electrically connected to the conductive via is formed on a rear surface side of the uppermost semiconductor element, and a bump of a different type of semiconductor element is connected to the conductive film. 3. The semiconductor device according to claim 1. 前記ベース部材に、ワイヤーボンディングされた半導体素子が実装されていることを特徴とする請求項９〜１２の何れかに記載の半導体装置。The semiconductor device according to claim 9, wherein a semiconductor element wire-bonded is mounted on the base member. 前記ベース部材は、基板又は半導体素子であることを特徴とする請求項９〜１４の何れかに記載の半導体装置。The semiconductor device according to claim 9, wherein the base member is a substrate or a semiconductor element.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100842916B1 (en) 2007-03-09 2008-07-03 주식회사 하이닉스반도체 Method for fabricating stack package
US8581414B2 (en) 2009-09-21 2013-11-12 Kabushiki Kaisha Toshiba Method of manufacturing three-dimensional integrated circuit and three-dimensional integrated circuit apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100842916B1 (en) 2007-03-09 2008-07-03 주식회사 하이닉스반도체 Method for fabricating stack package
US8581414B2 (en) 2009-09-21 2013-11-12 Kabushiki Kaisha Toshiba Method of manufacturing three-dimensional integrated circuit and three-dimensional integrated circuit apparatus

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