JP2004046251A - Electroluminescence display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve picture quality by eliminating the overlap time between a select signal and a next select signal. <P>SOLUTION: A device is equipped with a display panel and a shift register formed on the same substrate, a plurality of select switches Tx1 to Tx3 selecting a plurality of electroluminescence elements, a select signal generating circuit which outputs select signals x1 to x3 driving the select switches Tx1 to Tx3 in order, and a mask signal-INL generating circuit which masks the select signals x1 to x3 and eliminates the overlap time between successive select signals. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to an EL display device that drives an electroluminescence (hereinafter, referred to as EL) element using a thin film transistor (hereinafter, referred to as TFT).

FIGS. 5 and 6 are views showing a conventional example. Hereinafter, a conventional example will be described with reference to the drawings.

  FIG. 5 is an explanatory diagram of a conventional X-axis shift register. In FIG. 5, NAND circuits 21 and 22 are waveform shaping circuits, to which a clock -CL having an opposite phase and a low-level ("L") start pulse (X-axis synchronization signal) -SP are input. The clocked inverters 26 to 32 and the inverters 33 to 37 are shift registers. Further, the inverters 38 to 43 and the NAND circuits 44 to 46 are logic circuits that output selection signals x1 to x3.

(4) When one of the clock CL and the anti-phase clock -CL is at a high level (“H”), the other is at a low level (“L”).

The clocked inverter becomes active when the clock CL input is “L” and the opposite phase clock −CL input is “H”, and operates as an inverter. Conversely, when the clock CL input is “H”, the opposite phase clock − When the CL input is “L”, the state becomes a high impedance state.

{For example, the clocked inverter 26 and the clocked inverter 29 have the clock CL input and the opposite-phase clock input -CL connected in reverse. Therefore, when the clocked inverter 26 is in the active state, the clocked inverter 29 is in a high impedance state.

FIG. 6 is a waveform explanatory diagram of a conventional example. Hereinafter, the operation of the X-axis shift register of FIG. 5 will be described based on waveforms at respective points in FIG.

(1) The potential at point A, which is the output of the waveform shaping circuit, is "H" when there is no start pulse -SP ("L"). At this time, when the “L” start pulse −SP is input, the point A becomes “L” (see FIG. 6, A).

(2) The point B becomes "H" when the point A becomes "L" because the clocked inverter 26 is in the active state, and when the clocked inverter 26 becomes the high impedance state next time, Since "29" is in the active state, "H" at the point B is held only during the active period of the clocked inverter 29 (see FIG. 6, B).

(3) The point C has a waveform opposite in phase to the point B by the inverter 33 (see FIG. 6, C).

(4) The point D has a waveform delayed by a half clock cycle from the point B by the holding circuit including the clocked inverter 27 and the inverter 34 and the clocked inverter 30 which are activated simultaneously with the clocked inverter 29.

(5) The point E becomes a waveform having a phase opposite to that of the point D by the inverter 34, and a waveform delayed by half a clock cycle from the waveform of the point C (see FIG. 6, E).

(6) The point F has a waveform delayed by a half clock cycle from the point D due to the holding circuit including the clocked inverter 28 which becomes active at the same time as the clocked inverter 30 and the inverter 35 and the clocked inverter 31.

(7) The point G becomes a waveform having a phase opposite to that of the point F by the inverter 35, and a waveform delayed by half a clock cycle from the waveform of the point E (see FIG. 6, G).

(8) The H point becomes an inverted signal of the C point by the inverter 38 (see H in FIG. 6). The point I becomes an inverted signal of the point E by the inverter 39 (see I in FIG. 6). The point J is an inverted signal of the point G by the inverter 40 (see FIG. 6, J).

(9) The point K is the output of the NAND circuit 44, and the signals at the points H and E are input to the two inputs of the NAND circuit 44. The point L is an output of the NAND circuit 45, and signals of the points I and G are input to two inputs of the NAND circuit 45. The point M is an output of the NAND circuit 46. Two inputs of the NAND circuit 46 are input with a signal from a point J and an inverter (not shown).

(10) The selection signal x1 becomes an inverted signal at point K by the inverter 41 (see x1 in FIG. 6), and the selection signal x1 is input to the gate of the N-channel field effect transistor Tx1. For this reason, when the selection signal x1 becomes "H", the transistor Tx1 is turned on, and the drain and the source thereof are conducted.

(11) The selection signal x2 is an inverted signal at the point L by the inverter 42 (see x2 in FIG. 6), and this selection signal x2 is input to the gate of the N-channel field effect transistor Tx2. Therefore, when the selection signal x2 becomes “H”, the transistor Tx2 is turned on.

(12) The selection signal x3 becomes an inverted signal at the point M by the inverter 43 (see x3 in FIG. 6), and this selection signal x3 is input to the gate of the N-channel field effect transistor Tx3. Therefore, when the selection signal x3 becomes “H”, the transistor Tx3 is turned on.

In this way, signals having a half clock cycle shift in the order of the selection signals x1, x2, x3,... Are obtained. The solid line waveforms of the selection signals x1 to x3 are ideal waveforms, and the waveforms actually applied to the gates of the transistors Tx1 to Tx3, which are selection switches, are represented by dotted lines due to the capacitance and resistance of the circuit. Time ΔT is required for the rise and fall.

(4) The conventional one described above has the following problems.

現 実 The actual waveforms of the selection signals x1 to x3 (dotted lines in FIG. 6) require a time ΔT determined by the circuit for the rise and fall. For this reason, during this period of time ΔT, for example, the output of the selection signal x1 and the output of the next selection signal x2 overlap. Thus, during this period, the transistors Tx1 and Tx2, which are the selection switches, are simultaneously turned on, and the image data signal -VL of the capacitor c11 enters the capacitor c21 of the adjacent pixel. For this reason, the image quality of the EL display device may be deteriorated.

The object of the present invention is to improve the image quality of an EL display device by providing a mask period between a selection signal and the next selection signal to eliminate overlap between the selection signals.

The present invention is configured as follows in order to solve the above problems.

FIG. 2 is an explanatory diagram of the embodiment of the present invention, and shows a configuration of a selection signal generation circuit which is an X-axis shift register. In FIG. 2, NAND circuits 21 and 22 are waveform shaping circuits to which clocks -CL of opposite phases and a start pulse -SP of "L" are input. The clocked inverters 26 to 32 and the inverters 33 to 37 are shift registers. Further, the inverters 38 to 43 and the three-input NAND circuits 23 to 25 are logic circuits that output X-axis selection signals x1 to x3. The mask signal -INL from the mask signal generation circuit is connected to one input of the three-input NAND circuits 23 to 25, and the image data signal -VL is connected to transistors Tx1 to Tx3 which are X-axis selection switches. .

作用 The operation based on the above configuration will be described.

The X-axis selection signal x1 is obtained by inputting an output obtained by inverting the output from the inverter 33 of the shift register by the inverter 38, the output of the inverter 34 of the shift register, and the mask signal -INL to the three-input NAND circuit 23. The output of the three-input NAND circuit 23 is inverted by the inverter 41.

The selection signal x2 is obtained by inputting the output obtained by inverting the output from the inverter 34 by the inverter 39, the output of the inverter 35, and the mask signal -INL to the three-input NAND circuit 24. 42.

Similarly, the selection signal x3 is obtained by inverting the output from the three-input NAND circuit 25 by the inverter 43.

(4) The mask period of the mask signal -INL is equal to or longer than the overlap period ΔT between the selection signal x1 of the conventional example (see FIG. 6) and the next selection signal x2.

(4) As described above, by eliminating the overlap in which the selection signal and the next selection signal are output simultaneously, the image quality of the EL display device can be improved.

As described above, according to the present invention, since the mask means for eliminating the overlap time of the selection signals for sequentially driving the transistors Tx1 to Tx3, which are the selection switches, is provided, the image data signal of a certain pixel is changed to the image data signal of another pixel. Thus, the image quality of the EL display device can be improved without penetrating.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1 to 4 show the embodiments of the present invention, and the same components as those in FIGS. 5 to 6 are denoted by the same reference numerals.

FIG. 1 is an explanatory view of the present invention, and FIG. 1A is a panel block diagram. In FIG. 1A, a display (display) panel 10 is provided with a display screen 11, an X-axis shift register 12, and a Y-axis shift register 13.

(4) EL power is supplied to the display screen 11, and power supply of the shift register and input of the X-axis synchronization signal are performed to the X-axis shift register 12. Further, supply of power to the shift register and input of a Y-axis synchronization signal are performed to the Y-axis shift register 13. Further, an output of the image data signal is provided at an output section of the X-axis shift register 12.

FIG. 1B is an enlarged explanatory view of a portion A in FIG. 1A. One pixel (shown by a dotted square) of the display screen 11 has two transistors, one capacitor, and one EL element. It is composed of one.

The light emitting operation of this one pixel is, for example, when the selection signal y1 is output from the Y-axis shift register 13 and the selection signal x1 is output from the X-axis shift register 12, the transistors Ty11 and Tx1 are turned on. It becomes.

Therefore, the image data signal -VL is input to the gate of the drive transistor M11. As a result, a current corresponding to the gate voltage flows from the EL power supply to the drain and source of the drive transistor M11, and the EL element EL11 emits light.

At the next timing, the X-axis shift register 12 turns off the output of the selection signal x1 and outputs the selection signal x2. However, the gate voltage of the drive transistor M11 is held by the capacitor c11. The light emission of the EL element EL11 continues until this pixel is selected.

FIG. 2 is an explanatory diagram of an embodiment of the present invention, and shows a circuit configuration of an X-axis shift register. In FIG. 2, NAND circuits 21 and 22 are waveform shaping circuits to which clocks -CL of opposite phases and a start pulse -SP of "L" are input. The clocked inverters 26 to 32 and the inverters 33 to 37 are shift registers. These waveform shaping circuits and shift registers are the same as those in the conventional example of FIG.

The inverters 38 to 43 and the three-input NAND circuits 23 to 25 are logic circuits that output X-axis selection signals x1 to x3.

The first input of the three-input NAND circuit 23 receives the signal at the point H, which is an inverted signal of the point C, from the inverter 38, the signal at the point E at the second input, and the mask signal at the third input. -INL is input. A signal obtained by inverting the signal at the point K, which is the output of the three-input NAND circuit 23, by the inverter 41 is the selection signal x1.

A first input of the three-input NAND circuit 24 is supplied with a signal at point I, which is an inverted signal at point E, by an inverter 39, a signal at point G is supplied to a second input, and a mask signal is supplied to a third input. INL is input. A signal obtained by inverting the signal at the point L, which is the output of the three-input NAND circuit 24, by the inverter 42 is the selection signal x2.

The first input of the three-input NAND circuit 25 receives a signal at point J, which is an inverted signal of point G by the inverter 40, and the second input receives a signal from an inverter (not shown) of the shift register. The mask signal -INL is input to the third input. The signal obtained by inverting the signal at point M, which is the output of the three-input NAND circuit 25, by the inverter 42 is the selection signal x3.

Thus, the selection signals x1, x2, x3,... Which are X-axis shift pulses can be obtained.

FIG. 3 is an explanatory diagram of waveforms in the embodiment. The waveform at point H input to the first input of the three-input NAND circuit 23 is an inverted waveform at point C of the shift register, and is "H" for one clock cycle. It becomes. The waveform at the point E input to the second input of the three-input NAND circuit 23 is a waveform delayed by half a clock cycle from the waveform at the point C. Further, a mask signal −INL is input to a third input of the three-input NAND circuit 23. The mask period MK of this mask signal is set to a period in which the falling and rising of the selection signal x1 and the next selection signal x2 do not overlap.

(4) In the waveform at the point K, which is the output of the three-input NAND circuit 23, the period of “L” is shorter by the mask period MK than the clock waveform CL. The inverted signal at the point K becomes the selection signal x1.

Similarly, the selection signals x2 and x3 are also pulses having a short width for the mask period MK of the mask signal -INL.

As described above, the mask period without the pulse of “H” is provided between the selection signals, so that the transistor Tx1 as the selection switch and the next transistor Tx2 can be prevented from being turned on at the same time.

FIG. 4 is an explanatory diagram of a mask signal, and FIG. 4A is an explanatory diagram of a mask signal generating circuit. In FIG. 4A, an eight-fold clock generated by a generator (not shown) is input to a divide-by-8 circuit 1 and a circuit 2 sequentially.

The divide-by-8 circuit 1 counts four clock pulses of the input clock (eight-times clock) to “H”, counts the next four clock pulses and outputs “L”,. H ”and“ L ”. As a result, a standard clock CL having an eight-fold pulse width is obtained.

The sequential circuit 2 outputs a repetitive waveform in which the input clock is counted as 3 clock cycles and is set to “L” for one clock cycle. As a result, a mask signal -INL is obtained.

FIG. 4B is an explanatory diagram of waveforms, and shows the waveforms of the eight-times clock, the clock CL which is a divide-by-8 output, and the mask signal -INL. In this case, the mask period MK of the mask signal -INL is 25% of a half clock cycle. The mask period is not limited to this, and can be appropriately changed according to the overlap period ΔT of the selection signal and the like.

It is an explanatory view of the present invention. It is an explanatory view of an embodiment of the invention. FIG. 4 is a waveform explanatory diagram according to the embodiment. FIG. 4 is an explanatory diagram of a mask signal according to the embodiment. It is explanatory drawing of the X-axis shift register of the conventional example. It is a waveform explanatory view of a conventional example.

Explanation of reference numerals

21 to 22 NAND circuit 23 to 25 3-input NAND circuit 26 to 32 Clocked inverter 33 to 43 Inverter Tx1 to Tx3 Transistor (selection switch)
x1 to x3 selection signal -INL mask signal -VL image data signal

Claims (9)

A display panel in which pixels each having one of a source and a drain connected to an EL element and a drive transistor having a gate connected to one of the source and the drain of the transistor are arranged in a matrix;
A shift register electrically connected to the transistor,
An active matrix type electroluminescent display device, wherein the display panel and the shift register are formed on the same substrate. A transistor having a gate connected to the gate signal line, and one of a source and a drain connected to the source signal line;
A drive transistor having a gate connected to the other of the source or the drain of the transistor;
An EL element connected to one of a source and a drain of the drive transistor;
An EL power supply line connected to the other of the source and the drain of the drive transistor;
A pixel having
A display panel in which the pixels are arranged in a matrix,
A shift register electrically connected to the transistor,
The active matrix type electroluminescent display device, wherein the display panel and the shift register are formed on the same substrate. A transistor having a gate connected to the gate signal line, and one of a source and a drain connected to the source signal line;
A drive transistor having a gate connected to the other of the source or the drain of the transistor;
An EL element connected to one of a source and a drain of the drive transistor;
An EL power supply line connected to the other of the source and the drain of the drive transistor;
A capacitor disposed between the gate of the drive transistor and the other of the source or the drain of the drive transistor;
A pixel having
A display panel in which the pixels are arranged in a matrix,
A shift register electrically connected to the transistor,
The active matrix type electroluminescent display device, wherein the display panel and the shift register are formed on the same substrate. A transistor having a gate connected to the gate signal line, and one of a source and a drain connected to the source signal line;
A drive transistor having a gate connected to the other of the source or the drain of the transistor;
An EL element connected to one of a source and a drain of the drive transistor;
An EL power supply line connected to the other of the source and the drain of the drive transistor;
A capacitor connected to the gate of the drive transistor and the EL power line;
A pixel having
A display panel in which the pixels are arranged in a matrix,
A shift register electrically connected to the transistor,
The active matrix type electroluminescent display device, wherein the display panel and the shift register are formed on the same substrate. A transistor having a gate connected to the gate signal line, and one of a source and a drain connected to the source signal line;
A drive transistor having a gate connected to the other of the source or the drain of the transistor;
An EL element connected to one of a source and a drain of the drive transistor;
An EL power supply line connected to the other of the source and the drain of the drive transistor;
A pixel having
A display panel in which the pixels are arranged in a matrix,
A selection switch for inputting an image data signal to the pixel via the source signal line;
A logic circuit that outputs a selection signal to the gate of the selection switch;
A shift register connected to the logic circuit,
The active matrix type electroluminescent display device, wherein the display panel, the selection switch, the logic circuit, and the shift register are formed on the same substrate. A transistor having a gate connected to the gate signal line, and one of a source and a drain connected to the source signal line;
A drive transistor having a gate connected to the other of the source or the drain of the transistor;
An EL element connected to one of a source and a drain of the drive transistor;
An EL power supply line connected to the other of the source and the drain of the drive transistor;
A pixel having
A display panel in which the pixels are arranged in a matrix,
A selection switch for inputting an image data signal to the pixel via the source signal line;
A logic circuit that outputs a selection signal to the gate of the selection switch;
A shift register connected to the logic circuit,
The display panel, the selection switch, the logic circuit, and the shift register are formed on the same substrate,
An active matrix type electroluminescent display device, wherein a mask signal is input to the logic circuit. 7. The active matrix type electroluminescent display device according to claim 6, wherein the mask signal masks a period in which the fall of the select signal of a certain column and the rise of the select signal of the next column overlap. The active matrix type electroluminescent display device according to claim 6, wherein the mask signal is output from a mask signal generation circuit. An active matrix type electroluminescent display device according to any one of claims 2 to 8, wherein the EL power supply line extends in parallel with the gate signal line.

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