JP2004038468A - Memory device and system with function to automatically fix software error, and method for automatically fixing software error - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory device and system with the function to automatically fix software errors and a method for automatically fixing software errors making it possible to automatically fix software errors within the memory device and to automatically fix errors by accessing an external server if necessary. <P>SOLUTION: In a system with a CPU and a memory device serving as a storage part, the memory device has a set of three memories capable of saving data and reading/writing data, and an error detection control circuit for executing the reading/writing of data from and to the memories under control of the CPU and for detecting and fixing troubles such as software errors occurring within the memories. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a memory device and a system with a soft error automatic repair function, and a method for automatically repairing a soft error, and more particularly to automatically repairing a soft error in a memory device and, when necessary, automatically accessing an external server. The present invention relates to a memory device and a system having a soft error automatic repair function, and a soft error automatic repair method, which makes possible.
[0002]
[Prior art]
Generally, as the memory is highly integrated and the area of the memory cell is reduced, the amount of charge stored in the memory cell is reduced. As the amount of stored charge decreases, alpha particles emitted by radiation decay of uranium and thorium contained in trace amounts in package materials and wiring materials, or neutron particles from outer space, etc., enter the memory, causing Electron-hole pairs generated by the interaction become noise in the memory cell, and a transient error tends to occur. This error is called a "soft error" because it is not permanent and returns to normal by rewriting to memory.
[0003]
Even soft errors can cause equipment and system malfunctions, so it is important to take sufficient measures when a soft error occurs. As an example, an “error correction mechanism for redundant memory” described in Japanese Patent Application Laid-Open No. 10-49448 is known.
[0004]
This publication describes a technique for preventing a non-recoverable error from developing due to accumulation of soft errors in a memory and realizing a highly reliable redundant memory.
[0005]
[Problems to be solved by the invention]
The above-mentioned conventional countermeasures against soft errors do not automatically recover the soft errors in the memory device.
[0006]
Therefore, an object of the present invention is to provide a memory device with a soft error automatic repair function, a memory device and a system capable of automatically repairing a soft error in a memory device and, when necessary, accessing an external server to automatically repair the soft error. It is to provide a soft error automatic repair method.
[0007]
[Means for Solving the Problems]
A memory device with a soft error automatic repair function according to the present invention is a device having a CPU (Central Processing Unit) and a memory device as a data storage unit, wherein the memory device stores and holds data and A set of three readable / writable memories, and an error for reading / writing data to / from the memory under the control of the CPU and detecting / repairing a defect such as a soft error occurring in the memory. And a detection control circuit.
[0008]
Each of the memories includes a user data area for storing data of a user who uses the memory device, and a redundant data area for storing redundant data for soft error detection of data stored in the user data area. A memory write unit that writes data to the memory in response to a data write request from the CPU; and a memory read that reads data from the memory in response to a data read request from the CPU. And an error repair unit that, when the memory read unit reads data from the memory, detects that a soft error has occurred in the data and repairs the data in which the error has occurred. , Is characterized.
[0009]
Further, the memory write unit writes the data requested to be written by designating an address from the CPU to a corresponding address in the user data area of any one of the three memories, Generating redundant data of the data, writing the redundant data to a corresponding address corresponding portion of the redundant data area of the memory, and writing the data and the redundant data to a corresponding address of the other two memories of the memory; It is characterized by copying over a part and overwriting.
[0010]
Further, the memory read unit specifies data read from the CPU by designating an address, and stores the data in the user data area of any one of the three memories (first memory) in the user data area. And the redundant data of the data is read from the corresponding address portion of the redundant data area of the memory (first memory). A first test is performed to determine whether a data error has occurred. If the first test does not detect a defect such as a soft error in the data, the data is sent to the CPU. As a result, when a defect such as a soft error is detected in the data, the address of the data is notified to the error repair unit.
[0011]
Further, the error repair unit may store the data at the address notified from the memory read unit in any one of the other two memories (first memory) from which the memory read unit has read. (2) reading from the corresponding address in the user data area of the user data area, and reading the redundant data of the data from the corresponding address section of the redundant data area in the memory (second memory); From the redundant data, a second check is performed to determine whether or not a defect such as a soft error has occurred in the data. As a result of the second check, if no defect is detected in the data, the data is replaced with the data. The data is sent to the memory read unit, and the memory read unit sends the data to the CPU. Further, the error repair unit sends the data of the memory (second memory) and the redundant data. Is written to the user data area and the redundant data area of the memory (first memory) to which the memory read unit has already read, thereby restoring the memory (first memory) to which the memory read unit has already read. Is performed.
[0012]
Further, when a defect is detected in the data as a result of the second inspection by the error repair unit, the error repair unit reads the data at the address into the memory that has already read the data (the first memory and the first memory). The data is read from the corresponding address in the user data area of another memory (third memory) of the second memory), and the redundant data of the data is read from the corresponding address of the redundant data area of the memory (third memory). The data is read from the address corresponding portion, and a third check is performed from the data and the redundant data to determine whether or not a defect such as a soft error has occurred in the data. As a result of the third check, If no defect is detected, the data is sent to the memory read unit, the memory read unit sends the data to the CPU, and the error repair unit further sends the data to the memory (third memory). B) rewriting the data and the redundant data in the user data area and the redundant data area of the first memory and the second memory, respectively, thereby restoring the first memory and the second memory. If a defect is detected in the data as a result of the third inspection, the memory read unit is notified that the error cannot be repaired, and the memory read unit determines that the error cannot be repaired. The effect is notified to the CPU.
[0013]
A memory system with a soft error automatic recovery function according to the present invention is a device having a CPU and a memory device as a data storage unit, wherein the memory device stores and holds data and is capable of reading / writing data. A set of memories; and an error detection control circuit that reads / writes data to / from the memories under the control of the CPU and detects / repairs a defect such as a soft error that has occurred in the memories. The apparatus includes a wireless interface unit connected to the CPU and capable of performing wireless communication, and a wired interface unit connected to the CPU and capable of performing wired communication. If a fault such as a soft error occurring in the memory cannot be repaired, the CPU Alternatively, the wired interface unit is activated to connect to a server installed outside the device, download the error repair data stored and held by the server to the device, and store the error repair data in the memory. In this case, a defect such as a soft error occurring in the memory is repaired by re-writing.
[0014]
Further, the server stores and retains a history of defects such as soft errors occurring in the memory in the server.
[0015]
An automatic soft error recovery method according to the present invention is an automatic soft error recovery method for a memory device having a set of three memories capable of storing and holding data and capable of reading / writing data. A user data area for storing data of a user who uses the memory device and a redundant data area for storing redundant data for soft error detection of data stored in the user data area, When a write request for writing data by designating an address is issued, the write-requested data is stored in a corresponding address in the user data area of any one of the three memories. Write, generate redundant data of the data, and write the redundant data to a corresponding address portion of the redundant data area of the memory. And, the data and the redundant data, overwrite copied to the other two of the address corresponding portion of memory of said memory, characterized in that.
[0016]
When a read request for reading data in the memory by designating an address is issued, the read-requested data is stored in one of the three memories (first memory). While reading from the corresponding address in the user data area, the redundant data of the data is read from the corresponding address portion of the redundant data area of the memory (first memory). A first test is performed to determine whether or not a defect such as a soft error has occurred in the data. As a result of the first test, if no defect such as a soft error is detected in the data, the data has no error. The data is sent as legitimate data to the request source of the read request, and as a result of the first inspection, if a defect such as a soft error is detected in the data, the address of the data is changed. Notifying the error repair means, characterized in that.
[0017]
Further, the error repairing means stores the data of the address in the user data area of any one of the other two memories (the second memory) from which the data has been read (the first memory). At the same time as reading from the address, the redundant data of the data is read from the corresponding portion of the redundant data area of the memory (second memory) at the corresponding address, and the data and the redundant data are added to the data. A second check is performed to determine whether or not an error has occurred. If no defect is detected in the data as a result of the second check, the data is sent to the request source of the read request as legitimate data without errors. Sending the data and the redundant data in the memory (second memory) to the user data area and the redundant data area in the read memory (first memory). By re-writing in, to repair of the lead already memory (first memory), characterized in that.
[0018]
Further, when a defect is detected in the data as a result of the second inspection by the error repairing means, the error repairing means reads the data at the address into the memory that has already read the data (the first memory and the first memory). The data is read from the corresponding address in the user data area of another memory (third memory) of the second memory), and the redundant data of the data is read from the corresponding address of the redundant data area of the memory (third memory). The data is read from the address corresponding portion, and a third check is performed from the data and the redundant data to determine whether or not a defect such as a soft error has occurred in the data. As a result of the third check, If no defect is detected, the data is sent to the request source of the read request as normal data without error, and the data in the memory (third memory) and the redundant data are transmitted. And restoring the first memory and the second memory by rewriting the user data area and the redundant data area of the first memory and the second memory, respectively, and performing the third inspection. When a defect is detected in the data, the source of the read request is notified that the error cannot be repaired.
[0019]
Further, the request source of the read request notified that the error cannot be repaired is connected to an external server by wireless communication or wired communication, and the error repair data stored and held by the server is downloaded. By rewriting the data for error repair to the memory, a defect such as a soft error occurring in the memory is repaired.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0021]
FIG. 1 is a block diagram showing an embodiment of a memory system with a soft error automatic recovery function according to the present invention.
[0022]
The present embodiment shown in FIG. 1 includes a memory device 80 that stores and retains computer programs and data, and a CPU (Central Processing Unit: Central Processing Unit) that accesses the memory device 80 and executes processing such as calculation, operation, and control. ) 35, a control device 90 including a wireless I / F (interface) 40 connected to the CPU 35, and a wired I / F 50 connected to the CPU 35, and stores and holds computer programs and data. And a server 60, which is an information processing device having a function that can be distributed upon request.
[0023]
When the control device 90 accesses the server 60, a method of accessing the server 60 from the wireless I / F 40 of the control device 90 via the wireless line 70, the wireless terminal 45, and the wireless network 65, or Two access routes are prepared: a method of accessing the server 60 from the wired I / F 50 of the device 90 via the wired network 55.
[0024]
That is, the wireless I / F 40 is a communication interface device having a function of communicating with the outside through a wireless connection, and the wired I / F 50 is a communication interface device having a function of communicating with the outside through a wired connection.
[0025]
The control device 90 may be a device having any function as long as the device includes the CPU 35 and the memory device 80. For example, a communication device, a monitoring control device, a personal computer or various servers, a mobile phone or a mobile terminal Or, in the present embodiment, devices and devices not related to the present invention, such as peripheral devices and input / output devices included in these devices, are not shown in the present embodiment. I have.
[0026]
The memory device 80 included in the control device 90 stores and holds computer programs and data (hereinafter, these are simply referred to as data), and is capable of reading (reading) / writing (writing) these data. And a set of memories 10-1, 10-2, and 10-3 to read / write data to / from the memory 10 and detect / repair defects such as soft errors occurring in the memory 10. And an error detection control circuit 20 for performing the following.
[0027]
Next, a detailed configuration of the memory device 80 of the present embodiment will be described with reference to FIG.
[0028]
FIG. 2 is a detailed block diagram illustrating an example of the memory device according to the present embodiment. In FIG. 2, components corresponding to those shown in FIG. 1 are denoted by the same reference numerals or symbols, and description thereof will be omitted.
[0029]
In FIG. 2, first, a set of three memories 10 includes a user data area 11 (11-1, 11-2, 11-3) and a redundant data area 12 (12-1, 12-2, 12-12). -3). The user data area 11 is an area that can be freely accessed by a user using the memory device 80, and is an area where data can be freely read / written under the control of the CPU 35. The unit of data read / write may be any unit of data depending on the usage mode of the memory device 80, such as a byte unit, a word unit, or a record (storage of a plurality of bytes or words). Unit).
[0030]
The redundant data area 12 is an area for recording redundant data for detecting a soft error generated in the memory 10, and is an area that cannot be used by a user. The redundant data recorded in the redundant data area 12 can be any type of redundant data according to the usage of the memory device 80. For example, it may be a parity bit of 1 bit corresponding to each byte of the user data area 11, or may be a byte, a word, or a record (a storage unit composed of a plurality of bytes or a plurality of words) of the user data area 11. ) May be a multi-bit error detection code or a multi-bit error correction code.
[0031]
Next, the error detection control circuit 20 reads data from the memory 10 in response to a data write request from the CPU 35 and a memory write unit 21 that writes data to the memory 10 in response to a data write request from the CPU 35. When the memory read unit 22 reads data, when the memory read unit 22 reads data, if a soft error occurs in the data, the error read unit 22 repairs the data in which the error occurred. Have been.
[0032]
The memory write unit 21 writes the data requested to be written to, for example, a corresponding address in the user data area 11-1 of the memory 10-1, automatically generates redundant data of the data, and writes the redundant data. The data is written to the corresponding address corresponding portion of the redundant data area 12-1 and accumulated. Then, the data and the redundant data are copied and overwritten in the corresponding addresses of the other two memories 10-2 and 10-3. That is, at the time of data writing, the data requested to be written and the redundant data of the data are the same in the three memories 10 (10-1, 10-2, 10-3).
[0033]
At the time when the writing of data to the three memories 10 (10-1, 10-2, 10-3) is completed, the consistency of the data stored and held in the three memories 10 is confirmed. If this is the case, it is possible to store and hold data with even higher reliability.
[0034]
The memory read unit 22 reads the data requested to be read, for example, from a corresponding address in the user data area 11-1 of the memory 10-1, and also converts redundant data of the data into a corresponding address of the redundant data area 12-1. Lead from the part. Then, based on the data and the redundant data, an inspection is performed to determine whether a defect such as a soft error has occurred in the data.
[0035]
As a result of the inspection, if a defect such as a soft error is not detected in the data, there is no error in the data, and the data is sent to the CPU 35.
[0036]
When a defect such as a soft error is detected in the data as a result of the inspection by the memory read unit 22, the memory read unit 22 notifies the address of the data to the error repair unit 23.
[0037]
The error repair unit 23 reads the data at the address from the corresponding address in the user data area 11-2 of the memory 10-2, for example, instead of from the memory 10-1 to which the data has already been read. The data is read from the corresponding address portion of the redundant data area 12-2. Then, based on the data and the redundant data, an inspection is performed to determine whether a defect such as a soft error has occurred in the data. As a result of the inspection, if no defect is detected in the data, the data, that is, the data read from the memory 10-2 is sent to the memory read unit 22. Further, the error repair unit 23 rewrites the data in the memory 10-2 and the redundant data to the user data area 11-1 and the redundant data area 12-1 in the memory 10-1 to thereby write the data in the memory 10-2. 1 is repaired.
[0038]
When the error recovery unit 23 reads the memory 10-2 and detects an error from the memory 10-2, the error recovery unit 23 reads the data at the address from the memory 10-1 that has already read the data. 10-2, and from the corresponding address in the user data area 11-3 of the memory 10-3, and the redundant data of the data is read from the corresponding address in the redundant data area 12-3. Then, based on the data and the redundant data, an inspection is performed to determine whether a defect such as a soft error has occurred in the data. As a result of the inspection, if no defect is detected in the data, the data, that is, the data read from the memory 10-3 is sent to the memory read unit 22. Further, the error repair unit 23 stores the data in the memory 10-3 and the redundant data in the user data areas 11-1 and 11-2 and the redundant data areas 12-1 and 12- in the memories 10-1 and 10-2. 2, the memories 10-1 and 10-2 are restored.
[0039]
When the error repair unit 23 detects an error from both the memory 10-2 and the memory 10-3, the error repair unit 23 cannot repair the error. Notify that it is possible.
[0040]
Next, the operation of the present embodiment shown in FIGS. 1 and 2 will be described in detail.
[0041]
When writing data of a user who uses the memory device 80 to the memory 10, the CPU 35 of the control device 90 sends a write request to the memory device 80 so as to write the data to an address designated by the memory 10. I do. The write request can be made in any of a byte unit, a word unit, and a record unit, depending on the usage mode of the memory device 80. If the write request is a byte unit, the memory device 80 can write redundant data in byte units. When a write request is generated in units of words, redundant data is generated in units of words, and in the case of a write request in units of records, redundant data is generated in units of records.
[0042]
The memory device 80 that has received the data write request sends the write request to the memory write unit 21 of the error detection control circuit 20, and the memory write unit 21 stores the write request data in the user data of the memory 10-1. The data is written to the corresponding address in the area 11-1 and redundant data of the data is automatically generated, and the redundant data is written to the corresponding address corresponding portion of the redundant data area 12-1 and accumulated. Then, the data and the redundant data are copied and overwritten in the corresponding addresses of the other two memories 10-2 and 10-3. When the data writing to the three memories 10 (10-1, 10-2, and 10-3) is completed, the memory write unit 21 checks the consistency of the data stored and held in the three memories 10. And sends a data write end notification to the CPU 35.
[0043]
When there is data to be written to the memory 10 next, the CPU 35 that has received the data write completion notification sends a write request for the next data to the memory device 80 so that the memory device 80 By performing the same operation, the same data is stored and held in the three memories 10 (10-1, 10-2, 10-3).
[0044]
Next, when reading data from the memory 10, the CPU 35 sends a data read request specifying an address of the memory 10 to the memory device 80.
[0045]
The memory device 80 that has received the data read request sends the read request to the memory read unit 22 of the error detection control circuit, and the memory read unit 22 stores the read requested data in the user data area of the memory 10-1. At the same time as reading from the corresponding address in 11-1, the redundant data of the data is read from the corresponding address portion of the redundant data area 12-1. Then, based on the data and the redundant data, an inspection is performed to determine whether a defect such as a soft error has occurred in the data.
[0046]
As a result of the inspection, if a defect such as a soft error is not detected in the data, since there is no error in the data, the data is transmitted to the CPU 35 together with a read end notification.
[0047]
When a defect such as a soft error is detected in the data as a result of the inspection by the memory read unit 22, the memory read unit 22 notifies the address of the data to the error repair unit 23.
[0048]
The error repair unit 23 reads the data at the address from the corresponding address in the user data area 11-2 of the memory 10-2, not from the memory 10-1 to which the data has already been read. From the corresponding address in the redundant data area 12-2. Then, based on the data and the redundant data, an inspection is performed to determine whether a defect such as a soft error has occurred in the data. As a result of the inspection, if no defect is detected in the data, the data, that is, the data read from the memory 10-2 is sent to the memory read unit 22, and the memory read unit 22 sends the data to the CPU 35 together with a read end notification. Send out. Further, the error repair unit 23 rewrites the data in the memory 10-2 and the redundant data to the user data area 11-1 and the redundant data area 12-1 in the memory 10-1 to thereby write the data in the memory 10-2. 1 is repaired.
[0049]
When the error recovery unit 23 reads the memory 10-2 and detects an error from the memory 10-2, the error recovery unit 23 reads the data at the address from the memory 10-1 that has already read the data. 10-2, and from the corresponding address in the user data area 11-3 of the memory 10-3, and the redundant data of the data is read from the corresponding address in the redundant data area 12-3. Then, based on the data and the redundant data, an inspection is performed to determine whether a defect such as a soft error has occurred in the data. As a result of the inspection, if no defect is detected in the data, the data, that is, the data read from the memory 10-3 is sent to the memory read unit 22, and the memory read unit 22 sends the data to the CPU 35 together with the read end notification. Send out. Further, the error repair unit 23 stores the data in the memory 10-3 and the redundant data in the user data areas 11-1 and 11-2 and the redundant data areas 12-1 and 12- in the memories 10-1 and 10-2. 2, the memories 10-1 and 10-2 are restored.
[0050]
When the error repair unit 23 detects an error from both the memory 10-2 and the memory 10-3, the error repair unit 23 cannot repair the error. Notifying that the error is possible, the memory read unit 22 sends an error repair impossible notification to the CPU 35 together with the address where the error has occurred.
[0051]
When the CPU 35 receives the read end notification from the memory read unit 22, the CPU 35 executes a necessary process using the data transmitted together with the read end notification, that is, the data without error.
[0052]
When the CPU 35 receives the error recovery impossible notification from the memory read unit 22, the CPU 35 activates the wired I / F 50 and instructs the server 60 to transmit the address information of the data in which the error has occurred. The wired I / F 50 is connected to the wired network 55, and sends address information of the data in which the error has occurred to the server 60 via the wired network 55. The server 60 stores the history of the occurrence of the error in the corresponding address as a history, retrieves the data of the corresponding address from the storage device stored therein, distributes the data via the wired network 55, and / F50. The wired I / F 50 sends the corresponding data distributed from the server 60 to the CPU 35.
[0053]
The CPU 35 that has received the relevant data distributed from the server 60 from the wired I / F 50 sends a write request to the memory device 80 to write the relevant data again to the corresponding address of the memory 10. The memory device 80 performs the same operation as that of receiving the above-described normal write request, and writes the corresponding data to the corresponding addresses of the memory 10 (three memories of 10-1, 10-2, and 10-3). As a result, the data at the corresponding address is restored as the original error-free data. The CPU 35 sends an inquiry to the server 60 again via the wired I / F 50 for the corresponding data rewritten to the memory 10 and causes the server 60 to distribute the relevant data again and check the validity of the relevant data. By doing so, the reliability of data restoration can be further enhanced.
[0054]
Next, the operation when the CPU 35 activates the wired I / F 50 but the wired network 55 to which the wired I / F 50 tries to connect is abnormal or the network is busy will be described.
[0055]
When the CPU 35 receives the error recovery impossible notification from the memory read unit 22 and the wired network 55 is abnormal or the network is busy, the CPU 35 sets the wireless I / F 40 And instructs the server 60 to transmit the address information of the data in which the error has occurred. The wireless I / F 40 connects to the wireless line 70 and sends out the address information of the data in which the error has occurred to the server 60 via the wireless terminal 45 and the wireless network 65. The server 60 stores the history of the occurrence of the error in the corresponding address as a history, retrieves the data of the corresponding address from the storage device stored therein and retrieves the data from the wireless network 65, the wireless terminal 45, and the wireless line 70. And sends it out to the wireless I / F 40. The wireless I / F 40 sends the corresponding data distributed from the server 60 to the CPU 35. The operation of the CPU 35 thereafter is exactly the same as the case where the above-described wired I / F 50 is activated, and the CPU 35 rewrites the corresponding data to the memory 10 to restore the corresponding data.
[0056]
The operation of the present embodiment has been described above in detail. According to the present embodiment, since three memories 10 (10-1, 10-2, 10-3) having the same storage contents are provided, "1" and "1" of a small number of bits of about 1 bit in the memories are provided. The probability that a so-called soft error in which the “0” level is inverted occurs at the same address in the three memories 10 at a time is very small. Therefore, even if a soft error occurs in any of the memories 10, This can be easily repaired only in the memory device. Further, even if the error cannot be repaired in the memory device, the error-free data can be easily recovered because the error-free data can be downloaded from the external server 60 by the wired I / F 50 or the wireless I / F 40. It becomes. Further, since the history information of the occurrence of the error in the memory 10 is stored and stored in the external server 60, it is possible to perform the statistical analysis on the error from the history information of the server 60 and to provide the maintenance information. It becomes.
[0057]
In this embodiment, if the data in each memory 10 is read at regular intervals, checked for errors, and then rewritten, the amount of charge stored in each memory 10 gradually decreases. Can be prevented, and the soft error itself is less likely to occur.
[0058]
Further, since the present embodiment includes the external server 60, not only can the data having an error be downloaded from the external server 60, but also the computer program and the entire data can be easily corrected and upgraded. It is possible to do.
[0059]
【The invention's effect】
As described above, the memory device and system with the soft error automatic repair function and the soft error automatic repair method according to the present invention include the memory device having three memories having the same storage contents. It has the effect of being able to automatically repair itself, and has a communication interface to an external server, so if necessary, access the external server and download data to automatically repair errors. This has the effect of making it possible to achieve this.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a memory system with a soft error automatic recovery function according to the present invention.
FIG. 2 is a detailed block diagram illustrating an example of a memory device according to the embodiment;
[Explanation of symbols]
10 memory
11 User data area
12 Redundant data area
20 Error detection control circuit
21 Memory write section
22 Memory read section
23 Error restoration unit
35 CPU
40 Wireless I / F
45 wireless terminal
50 Wired I / F
55 Wired Network
60 servers
65 Wireless Network
70 wireless line
80 Memory device
90 Control device

Claims (13)

In a device having a CPU (Central Processing Unit) and a memory device as a data storage unit, the memory device stores and holds data and can read / write data in a set of three memories. And an error detection control circuit that reads / writes data from / to the memory under the control of the CPU and detects / repairs a defect such as a soft error occurring in the memory. Memory device with automatic error recovery function. Each of the memories includes a user data area that stores data of a user who uses the memory device, and a redundant data area that stores redundant data for soft error detection of data stored in the user data area, An error detection control circuit includes a memory write unit that writes data to the memory in response to a data write request from the CPU, and a memory read unit that reads data from the memory in response to a data read request from the CPU. An error repair unit that, when the memory read unit reads data from the memory, detects that a soft error has occurred in the data, and repairs the data in which the error has occurred. The memory device with a soft error automatic repair function according to claim 1. The memory write unit writes data requested to be written by specifying an address from the CPU to a corresponding address in the user data area of any one of the three memories, and And writing the redundant data to a corresponding address corresponding portion of the redundant data area of the memory, and copying the data and the redundant data to a corresponding address corresponding portion of the other two memories of the memory. 3. The memory device with a soft error automatic repair function according to claim 2, wherein the memory device is copied and overwritten. The memory read unit reads data requested to be read by designating an address from the CPU from a corresponding address in the user data area of any one of the three memories (first memory). At the same time, the redundant data of the data is read from the corresponding portion of the redundant data area of the memory (first memory) at the corresponding address, and a defect such as a soft error occurs in the data from the data and the redundant data. A first test is performed to determine whether or not a defect such as a soft error is detected in the data as a result of the first test. 4. The soft error according to claim 3, wherein when a defect such as a soft error is detected in the data, the address of the data is notified to the error repair unit. Dynamic repair function with a memory device. The error repairing unit stores the data at the address notified from the memory reading unit in one of the other two memories (first memory) of the memory (first memory) to which the memory reading unit has read. 2) read from a corresponding address in the user data area, and read redundant data of the data from a corresponding portion of the redundant data area in the memory (second memory), and read the data and the redundant data. Then, a second check is performed to determine whether or not a defect such as a soft error has occurred in the data. If the result of the second check indicates that no defect is detected in the data, the data is read into the memory read. And the memory read unit sends the data to the CPU, and the error repair unit compares the data in the memory (second memory) and the redundant data with the previous data. The memory read unit restores the read memory (first memory) by rewriting the user data area and the redundant data area of the read memory (first memory). The memory device with a soft error automatic recovery function according to claim 4, wherein: When a defect is detected in the data as a result of the second inspection by the error repair unit, the error repair unit reads the data at the address from the memory that has already read the data (the first memory and the second memory). The memory is read from a corresponding address in the user data area of another memory (third memory), and redundant data of the data is read from a corresponding address of the redundant data area of the memory (third memory). From the data and the redundant data, a third check is performed as to whether or not a defect such as a soft error has occurred in the data. As a result of the third check, a defect is detected in the data. If it is not detected, the data is sent to the memory read unit, and the memory read unit sends the data to the CPU. The data and the redundant data are rewritten to the user data area and the redundant data area of the first memory and the second memory, respectively, thereby restoring the first memory and the second memory, As a result of the third inspection, when a defect is detected in the data, the memory read unit is notified that the error cannot be repaired, and the memory read unit indicates that the error cannot be repaired. The memory device with an automatic soft error recovery function according to claim 5, wherein the memory device is notified to a CPU. In a device having a CPU and a memory device as a data storage unit, the memory device stores and holds data and can read / write data, and a set of three memories, wherein the memory is controlled by the CPU. An error detection control circuit for reading / writing data to / from the memory and detecting / restoring a defect such as a soft error occurring in the memory, wherein the device performs wireless communication connected to the CPU. A wireless interface unit capable of performing wired communication connected to the CPU, and the error detection control circuit cannot repair defects such as soft errors occurring in the memory. In such a case, the CPU activates the wireless interface unit or the wired interface unit and activates the device. By connecting to the server installed in the unit, downloading the error repair data stored and held by the server to the device, and rewriting the error repair data to the memory, thereby generating the error repair data in the memory. A memory system with an automatic soft error repair function that repairs malfunctions such as soft errors that have occurred. The memory system according to claim 7, wherein the server stores a history of a defect such as a soft error occurring in the memory in the server. A method for automatically recovering soft errors in a memory device having a set of three memories capable of storing and holding data and capable of reading and writing data, wherein each of the memories is replaced with data of a user who uses the memory device. And a redundant data area for storing soft error detection redundant data of data stored in the user data area, and writing data to the memory by specifying an address. When a write request is issued, the write-requested data is written to a corresponding address in the user data area of any one of the three memories, and redundant data of the data is written. And writing the redundant data to a corresponding address portion of the redundant data area of the memory. Soft error auto repair method to overwrite copied to another area of the address corresponding portion of the two memory Mori, characterized in that. When a read request for reading data in the memory by designating an address is issued, the read-requested data is stored in the user of any one of the three memories (the first memory). At the same time as reading from the corresponding address in the data area, the redundant data of the data is read from the corresponding address portion of the redundant data area of the memory (first memory), and the data and the redundant data are converted to the data. A first check is performed to determine whether or not a defect such as a soft error has occurred. If the first test does not detect a defect such as a soft error in the data, the data is replaced with a regular error-free data. The data is sent to the request source of the read request, and if a defect such as a soft error is detected in the data as a result of the first inspection, the address of the data is set to an error. Soft error auto repair method of claim 9, notifies the recovery unit, it is characterized. The error repair means converts the data at the address from a corresponding address in the user data area of any one of the other two memories (the second memory) that have been read (the first memory). At the same time, the redundant data of the data is read from a corresponding address portion of the redundant data area of the memory (second memory), and a defect such as a soft error occurs in the data from the data and the redundant data. A second check is performed to determine whether the data is correct. If no defect is detected in the data as a result of the second check, the data is sent to the request source of the read request as legitimate data without errors. Further, the data and the redundant data of the memory (second memory) are written to the user data area and the redundant data area of the read memory (first memory). By re-performs repair of the lead already memory (first memory), a soft error auto repair method of claim 10, characterized in that. When a defect is detected in the data as a result of the second inspection by the error repair unit, the error repair unit reads the data at the address into the memory that has already read the data (the first memory and the second memory). The memory is read from a corresponding address in the user data area of another memory (third memory), and redundant data of the data is read from a corresponding address of the redundant data area of the memory (third memory). From the data and the redundant data, a third check is performed as to whether or not a defect such as a soft error has occurred in the data. As a result of the third check, a defect is detected in the data. If not detected, the data is sent to the request source of the read request as normal data without error, and the data in the memory (third memory) and the redundant data are transmitted to the previous memory. The first memory and the second memory are restored by respectively rewriting the user data area and the redundant data area of the first memory and the second memory, and as a result of the third inspection, 12. The soft error automatic repair method according to claim 11, wherein when a defect is detected in the data, the request source of the read request is notified that the error cannot be repaired. The request source of the read request, which is notified that the error cannot be repaired, connects to an external server by wireless or wired communication, downloads the error repair data stored and held by the server, and executes the error repair. The automatic error recovery method according to claim 12, wherein a defect such as a soft error occurring in the memory is repaired by rewriting data for use in the memory.

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