JP2004038350A - Acceleration testing process for computer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the acceleration testing method of a computer for specifying a part where any failure is generated by reducing the reproducing period of any latent failure such as memory leak due to memory release leakage. <P>SOLUTION: The set value N of a register 210 for setting a timer interrupting interval set by an operating system 301 is changed by a program using a register access function 303 in computer hardware to shorten a timer interrupting interval, and to perform an acceleration test. Thus, it is possible to shorten a CPU resource assignment interval to a program on an operating system, and to shorten a period required for a reproduction test. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a test method for reproducing a software defect on a computer, and more particularly to a computer accelerated test method suitable for identifying a defective software item by shortening the reproduction time.
[0002]
[Prior art]
Normally, a potential problem such as a memory leak due to a memory release leak becomes apparent only when a program having the problem is operated on a computer for a long time. As a conventional technique for detecting this memory leak, Japanese Patent Application Laid-Open No. 2001-331368 describes a change in the memory usage of software when executing the software, which is longer than a normal cycle of increase and decrease of the usage. A memory release omission determination method for determining that a memory release omission has occurred when a tendency to increase over a predetermined analysis period is detected is disclosed. Japanese Patent Application Laid-Open No. 2000-293400 discloses that, when a request for securing memory occurs during processing, an application program calls a memory management library to secure a predetermined memory area and store dump information in a management table. When a request to release the memory allocated after processing occurs, the memory management library is called to release the memory area and delete the dump information by the memory management library, but when it is determined that the dump information is recorded after the application program is completed Discloses a memory leak detection method for displaying a stack frame included in dump information.
[0003]
[Problems to be solved by the invention]
In the memory release omission determination method described in Japanese Patent Application Laid-Open No. 2001-331368, a memory release omission occurs when a tendency to increase over a predetermined analysis period longer than a normal cycle of increase / decrease in usage is detected. Therefore, it takes a long time to determine the memory release omission. In addition, the memory leak detection method described in Japanese Patent Application Laid-Open No. 2000-293400 requires management of dump information, is difficult to apply to a general OS, and has a black box for a user. If the problem occurs in software, the source program cannot be seen by the user, and therefore, there is a problem that the location of the problem cannot be specified. Therefore, in particular, there is a problem that a user needs a long-term reproduction test in order to identify a program having a defect from programs running on a computer including a program which is a black box.
[0004]
A first object of the present invention is to provide an accelerated test method for a computer, which can shorten a reproduction period and specify a portion where a problem occurs.
[0005]
A second object of the present invention is to provide an accelerated test method for a computer in which an interval of CPU resource allocation to a program on an operating system is shortened and a period required for a reproduction test can be shortened.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, an acceleration test method for a computer according to the present invention sets the interval of allocation of a CPU to a defective program by setting a short interval of a timer interrupt signal used by the operating system to keep time. Is shortened.
[0007]
Further, the interval between timer interrupt signals is shortened by using a test time reduction program for shortening the interval between timer interrupt signals. The test time reduction program shortens a timer interrupt interval by changing a numerical value set in a register using an access function to a register in computer hardware provided by an operating system.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
One embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a hardware configuration diagram of a computer according to the present embodiment.
[0009]
As shown in FIG. 1, the computer according to the present embodiment includes a CPU 102, a memory 106 connected to the CPU 102 via a chipset 103, an input device 107 connected to the chipset 103, and a display device 108. The computer operates in synchronization with a clock transmitted from the transmitter 101. The chipset 103 has a data transfer control function 104 and a time measurement function 105. The data transfer control function 104 controls transmission and reception of data among the CPU 102, the memory 106, the input device 107, and the display device 108. The time measurement function 105 generates a timer interrupt signal by counting the clock from the transmitter 101, and notifies the software running on the computer of the lapse of time.
[0010]
FIG. 2 shows a configuration diagram of the time measurement function 105. The time measurement function 105 includes a register 201 for setting a timer interrupt interval, a selector 202 for inputting the output of the register 201, a counter 203 connected to the selector 202, and an output of the counter 203, and a subtracter 204 for outputting to the selector 202. , A comparator 205 to which the output of the counter 203 is input. The selector 202 is connected to the selection signal line 206 on the output side of the comparator 205, and the output of the comparator 205 is used as a timer interrupt signal.
[0011]
In the normal mode, the number of clocks N is set in the register 201, and the time interval for generating the timer interrupt signal is determined by the number of clocks. Two signals, input 1 from the subtractor 204 and input 2 from the register 201, are input to the selector 202. When no selection signal is input from the selection signal line 206, this selector 202 Is output, and when the selection signal is input from the selection signal line 206, the input 2 is output. The counter 203 records the number of input clocks. The subtractor 204 subtracts 1 from the input clock number every time the clock number is input to the counter 203, and outputs the result as an input 1. The comparator 205 inputs the input 1 from the counter 203 and the input 3, which is 0, and compares them. If the input 1 and the input 3 have the same value, the comparator 205 outputs a selection signal and a timer interrupt signal.
[0012]
Next, the operation of the time measuring function 105 thus configured will be described. The number of clocks N corresponding to the timer interrupt occurrence interval is set in the register 201. Since the initial value of the counter 203 is 0, 0 is input to the comparator 205 as input 1. The input 3 of the comparator 205 is set to 0, and the input 1 and the input 3 input to the comparator 205 have the same value, so that the comparator 205 outputs a selection signal and a timer interrupt signal. When the selection signal is input to the selector 202, N, which is the input 2, is output from the selector 202, and N is set in the counter 203. Since the input 1 of the comparator 205 is N and the input 3 is 0, which is a different value, the selection signal and the timer interrupt signal are not output.
[0013]
On the other hand, since the output value N of the counter 203 is input to the subtractor 204, N−1 is output as the input 1 from the subtractor 204 and input to the selector 202. Since the selection signal is not input to the selector 202, the value N−1 of the input 1 is output from the selector 202, and N−1 is set in the counter 203. When subtraction is performed N times by the subtractor 204, the value of the counter 203 becomes 0. When the counter 203 becomes 0, the selection signal and the timer interrupt signal are output from the comparator 205 as described above, and the value N of the register 201 is set in the counter 203 again. By repeating this operation, the time measurement function 105 outputs a timer interrupt signal at the set N clock intervals.
[0014]
FIG. 3 shows a software configuration of the present embodiment. The software includes an operating system (hereinafter abbreviated as OS) 301, one or more application programs, and a test time reduction program 801.
[0015]
In this embodiment, a case where there are two application programs 305 and 306 will be described as an example. The OS 301 has a CPU resource allocation function 302, a register access function 303 in computer hardware, and a memory management function 304. The CPU resource allocation function 302 measures time by counting a timer interrupt signal from the time measurement function 105, and switches allocation of CPU resources to the application program 305 and the application program 306. The register access function 303 provides an interface for an application program to access a register in the computer hardware. The memory management function 304 secures and releases a memory area for exclusive use by the application program. The OS 301 uses the register access function 303 to set the number of clocks in the register 201 during the initialization process in order to obtain a timer interrupt signal at set time intervals.
[0016]
FIG. 4 shows a processing flow of the test time reduction program 801. The test time reduction program 801 displays an input screen for a value to be set in the register 201 on the display device 108 in step 901, and waits for an input from a computer user in step 902. The user inputs a set value using the input device 107. As the set value, a numerical value N is input when the computer is used in a normal mode, and a numerical value M (<N) is input when an acceleration test is performed. When the acceleration test numerical value M is input, the test time reduction program 801 sets a new value M in the timer interrupt interval setting register 201 by using the register access function 303 provided by the OS 301.
[0017]
As described above, since the acceleration test can be performed by the user inputting the numerical value M using the input device, the acceleration level of the acceleration test can be adjusted.
[0018]
As shown in FIG. 5, in the processing of the application program 306, the core processing 501 of the application program 306 and the sleeve 502 until the start of the next processing are repeated. If it is assumed that the application program 306 does not include a process for releasing the secured memory area, the core processing 501 includes a process for securing the memory area. Since the release processing is not included, the application program 306 repeatedly performs the same processing periodically, and the memory area is continuously secured every time the core processing 501 of the application program 306 is executed.
[0019]
FIG. 6 is a diagram showing a transition of the state of the memory area until a failure occurs due to the processing of the application program 306. In the initial state 601, only the OS, the application program 305, and the application program 306 are mapped in the memory, and there is a sufficient free area. During the operation 602, the application program 306 repeats the core processing 501 to secure a memory area. Therefore, the free area gradually decreases, and when there is no free area, the computer stops and the failure 603 occurs.
[0020]
FIG. 7 shows allocation of CPU resources to the application program 305 and the application program 306 until a failure occurs when the computer is used in the normal mode. This example shows a case where the CPU resource allocation function 302 of the OS 301 switches the allocation of the CPU resources to the application programs 305 and the application programs 306 for each timer interrupt. The basic processing and the sleeve are alternately repeated, and a failure has occurred after a lapse of _TN time.
[0021]
As shown in FIG. 7, when the application program is a black box, in the normal mode, it takes _TN time to reproduce the failure, and the application program that causes the failure is identified. Requires time T _N × (number of application programs) to verify each application program one by one.
[0022]
FIG. 8 shows the allocation of CPU resources to the application programs 305 and 306 up to the occurrence of a failure when an acceleration test is performed. As shown in FIG. 8, when the application program 305 and the application program 306 are started by changing the set value of the timer interrupt interval setting register 201 by the test time reduction program 801, the timer interrupt interval by the time measurement function 105 becomes M (<N) clocks, so that the time until a failure occurs is reduced to T _M = T _N × M / N. That is, the CPU resource allocation interval to the program on the operating system is shortened, and the period required for the reproduction test can be shortened. As a result, it is possible to reduce the time for identifying the application program that caused the failure.
[0023]
In the above description, the case where the application programs are verified one by one has been described. However, when the cause can be estimated, an application for monitoring the memory usage is provided, and the memory usage is supplementarily set based on the memory usage. Can be determined. The monitoring of the memory usage is performed, for example, by reading the OS in which the current address is stored and reading information on the current memory usage by accessing the kernel.
[0024]
【The invention's effect】
According to the present invention, even when a failure of unknown cause occurs in a computer, it is possible to reduce the time for specifying the application program that caused the failure.
[Brief description of the drawings]
FIG. 1 is a hardware configuration diagram of a computer according to an embodiment of the present invention.
FIG. 2 is a configuration diagram of a time measurement function of a chipset.
FIG. 3 is a software configuration diagram of the present embodiment.
FIG. 4 is a processing flowchart of a test time reduction program shown in FIG. 3;
FIG. 5 is a processing flowchart of an application program.
FIG. 6 is a diagram showing a change in a memory area due to processing of an application program.
FIG. 7 is a diagram showing CPU resource allocation until a failure occurs when a computer is used in a normal mode.
FIG. 8 is a diagram showing CPU resource allocation until a failure occurs when an acceleration test is performed.
[Explanation of symbols]
101: transmitter, 102: CPU, 103: chipset, 104: data transfer control function, 105: time measurement function, 106: memory, 107: input device, 108: display device, 201: register, 202: selector, 203 ... Counter, 204 ... Subtractor, 205 ... Comparator, 301 ... OS, 302 ... CPU resource allocation function, 303 ... Register access function, 801 ... Test time reduction program.

Claims (4)

An operating system having a CPU resource assignment function for switching assignment of a CPU to an application program, and a register access function for providing an interface for the application program to access a register in computer hardware; The access function sets a value smaller than the normal mode in the register for setting the timer interrupt interval, and the CPU resource allocation function switches the CPU resource allocation to the application program by the timer interrupt with a shorter time interval than the normal mode. An accelerated test method for a computer, characterized by performing the following test. The test time reduction program accesses the registers using the register access function as the operating system, sets a shorter timer interrupt interval than in the normal mode, and repeats the core processing and sleeve of the application program using the CPU resource allocation function as the operating system. A computer accelerated test method characterized by performing software tests. 3. The operating system according to claim 1, wherein the operating system has a memory management function of performing a process of securing and releasing a memory area for exclusive use by an application program, and performs an acceleration test of a memory leak of the application program. The accelerated test method for a computer according to the above. 3. The acceleration test method for a computer according to claim 2, wherein the test time reduction program displays an input screen of a set value to be set in the register on a display device, and sets the set value input by the input device in the register.

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