JP2004031785A - Semiconductor device and its designing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can increase a noise reduction effect for high frequency noise caused in a signal line. <P>SOLUTION: In the signal line 19 for propagating digital signals, intervened is a three-terminal capacitance comprising a depletion type MOS transistor (Dep-Tr11) which is formed in a substrate 12 and is so mounted that a gate capacitance and a junction capacitance may work on the signal line 19. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for designing the same, and more particularly, to a semiconductor device useful for reducing noise on digital signals.
[0002]
In recent years, a semiconductor device has been required to have a multi-bit component that handles input / output of a plurality of data (digital signals). In such a semiconductor device, the influence of unnecessary radiation (radiation noise) and high-frequency noise accompanying high-density mounting and high-speed operation increases, and it is important to reduce these noises.
[0003]
[Prior art]
2. Description of the Related Art Conventionally, in a semiconductor device, as a method for removing unnecessary radiation and high-frequency noise, for example, the following methods are available.
[0004]
First Conventional Example: As shown in FIG. 10, a capacitor C is connected between a signal line (point A in the figure) and a ground GND for a signal line for transmitting a digital signal.
Second conventional example: A signal line is surrounded and shielded by a power supply wiring of a ground potential (GND) (hereinafter, ground power supply wiring). More specifically, as shown in FIG. 11, a first ground power supply line AL2 parallel to the signal line AL1 (in the direction perpendicular to the paper of the drawing) is provided on the same wiring layer with an oxide film interposed therebetween. Is connected to the first ground power supply line AL2 via a contact.
[0005]
[Problems to be solved by the invention]
By the way, in the above-mentioned first conventional example, it is necessary to increase the capacitance of the capacitor C in order to enhance the effect of removing high-frequency noise and radiation noise (especially on the high-frequency side). That is, this method requires a large-capacity capacitor C to remove high-frequency noise. However, providing such a large-capacity capacitor C leads to an increase in chip area, and as a result, high-frequency noise cannot be effectively removed. Further, even when the second conventional example in which the signal line AL1 is shielded by the ground power supply lines AL2 and AL3 is used, the effect of removing such high-frequency noise is insufficient, and the problem cannot be solved. .
[0006]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of improving the effect of removing high-frequency noise generated in a signal line and a method of designing the same.
[0007]
[Means for Solving the Problems]
To achieve the above object, according to the first aspect of the present invention, a three-terminal capacitor formed of a MOS transistor is formed in a semiconductor chip so as to be interposed between wirings. Since a three-terminal capacitor using such a MOS transistor can produce a large capacitance with a small chip area as compared with a capacitor that is a two-terminal capacitor, high-frequency noise and radiation noise can be effectively removed. it can.
[0008]
According to the second aspect of the present invention, at least one three-terminal capacitor is formed for each wiring in the semiconductor chip.
According to the third aspect of the invention, the three-terminal capacitor is provided such that a source electrode and a drain electrode of a MOS transistor are connected to the wiring, and a gate capacitance and a junction capacitance act on the wiring. .
[0009]
According to the fourth aspect of the present invention, the three-terminal capacitor is a depletion-type MOS transistor. A depletion-type transistor can have a larger gate capacitance than an enhancement-type transistor. Thus, the effect of removing high-frequency noise can be further enhanced.
[0010]
According to the fifth aspect of the invention, the three-terminal capacitor is an enhancement-type MOS transistor in which a gate control voltage for forming a channel is applied to a gate electrode.
[0011]
According to the invention described in claim 6, the wiring in the semiconductor chip includes a first wiring provided on the same wiring layer so as to be parallel to the wiring, and a first wiring provided on an upper layer of the wiring layer. A three-terminal capacitor constituted by the wiring and the second wiring connected via the contact is formed. With this configuration, high-frequency noise can be effectively removed by the wiring capacitance of the first and second wirings that surround the wiring over substantially the entire length.
[0012]
According to the invention described in claim 7, the three-terminal capacitance is formed on a plurality of bus signal lines provided corresponding to the number of bits of input / output data.
According to the invention described in claim 8, the three-terminal type capacitor is formed on a clock signal line for supplying a clock signal to a semiconductor chip.
[0013]
According to the ninth aspect of the present invention, the three-terminal capacitor is formed on a power supply wiring. According to a tenth aspect of the present invention, the three-terminal capacitor including the MOS transistor according to any one of the first to fifth aspects is arranged in each cell column formed at the time of layout of the semiconductor device. That is, a three-terminal capacitor can be automatically arranged using a general CAD device, and a three-terminal capacitor can be easily formed in a chip.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
[0015]
FIG. 1 is a conceptual diagram of a three-terminal capacitor using a depletion type MOS transistor (hereinafter, Dep-Tr) as a noise removing unit.
As shown in FIG. 1A, the Dep-Tr 11 is, for example, an N-channel MOS transistor formed on a P-type substrate 12, and is provided on an N-type diffusion layer 13 formed on the P-type substrate 12. A gate electrode (polysilicon gate) 15 is provided via a gate oxide film 14. In the Dep-Tr 11, even when no voltage is applied to the gate electrode 15 (that is, when the gate voltage is 0 volt (V)), the voltage between the source electrode 16 and the drain electrode 17 formed in the N-type diffusion layer 13 is reduced. A conductive channel 18 is formed.
[0016]
The Dep-Tr 11 is formed so as to be interposed on a signal line 19 for transmitting a digital signal inside the semiconductor device. Specifically, as shown in FIG. 1A, the source electrode 16 and the drain electrode 17 of the Dep-Tr 11 are connected to the signal line 19.
[0017]
FIG. 1B is an equivalent circuit of the configuration shown in FIG. In the Dep-Tr 11, the gate electrode 15 and the N-type diffusion layer 13 (channel 18) act as two electrodes provided so as to face each other with the signal line 19 interposed therebetween, and the substrate potential (ground GND) is reduced. On the other hand, it functions as a three-terminal capacitor having a gate capacitance and a junction capacitance. The inductances L1 and L2 formed on the signal line 19 are parasitic inductances generated when a digital signal propagates through the source electrode 16 and the drain electrode 17 of the Dep-Tr 11.
[0018]
FIG. 2 is a schematic diagram showing a case where a three-terminal capacitor (Dep-Tr11) is inserted into the bus signal line.
As shown in FIG. 2A, a bus circuit 21 provided inside the semiconductor device is connected to an external circuit (other circuit in the figure) via a bus signal line 19a, and data (data) between the external circuit and the external circuit is provided. Digital signals). For example, the bus circuit 21 includes a flip-flop circuit 22 for supplying a signal input from an external circuit to an internal circuit and a three-state buffer circuit 23 for supplying a signal output from the internal circuit to an external circuit. Including. It should be noted that the configuration of the bus circuit 21 of the present embodiment shown in the figure is an example, and the present invention is not limited to this configuration.
[0019]
The three-terminal capacitor constituted by the Dep-Tr 11 is formed on a bus signal line 19a connecting this bus circuit 21 to an external circuit. At this time, as shown in FIG. 2B, the three-terminal type capacitor (Dep-Tr11) has buses connected to n bus circuits 21 provided corresponding to n-bit input / output data, respectively. It is formed on the signal line 19a. As described above, by providing at least one three-terminal capacitor composed of the Dep-Tr 11 for each bus signal line 19a of each bus circuit 21 that handles multi-bit input / output data, the bus signal lines 19a are generated in each bus signal line 19a. It is possible to remove bidirectional noise.
[0020]
FIG. 3 is a schematic diagram showing a case where a three-terminal capacitor (Dep-Tr11) is inserted into the clock signal line.
A clock signal generated by a clock control circuit 31 is supplied to an internal circuit of the semiconductor device via, for example, inverter circuits 32 and 33. Although the clock control circuit 31 of this embodiment shown in FIG. 1 includes a crystal oscillator 34 and capacitors 35 and 36, the present invention is not limited to this configuration. The three-terminal capacitor (Dep-Tr11) is formed on the clock signal line 19b that propagates this clock signal, and thereby it is possible to remove noise generated on the clock signal line 19b.
[0021]
FIG. 4 is a schematic diagram showing a case where a three-terminal capacitor (Dep-Tr11) is inserted into a power supply line (power supply wiring).
The semiconductor device is provided with a large number of pads 42 along the outer periphery of the chip 41, and each pad 42 is connected to a power supply line 19c (power supply wiring) for supplying power to the inside of the semiconductor device. The three-terminal type capacitor (Dep-Tr11) is formed on the power supply line 19c connected to each pad 42, so that noise generated in the power supply line 19c can be removed.
[0022]
FIG. 5 is an explanatory diagram comparing the attenuation characteristics when a three-terminal capacitor (Dep-Tr11) is used as a noise removing unit and when a two-terminal capacitor (capacitor) is used.
As shown in the figure, the three-terminal capacitor composed of the Dep-Tr 11 can effectively remove noise even in a high frequency region of about 1000 MHz or more. On the other hand, in a two-terminal capacitor using a conventional capacitor, the effect of removing noise decreases as the frequency becomes higher. That is, in the present embodiment, by using the Dep-Tr11, a large capacitance can be created while reducing the chip area as compared with the case where a normal capacitor is used, so that high-frequency noise and radiation noise can be effectively reduced. Can be removed.
[0023]
The layout design of a semiconductor device in which a three-terminal capacitor constituted by such a Dep-Tr 11 is formed on each signal line 19 (including a bus signal line 19a, a clock signal line 19b, and a power supply line 19c) is as follows. This is performed using a computer system as shown in FIG.
[0024]
The computer system 51 is composed of a general CAD (Computer Aided Design) device, and includes a central processing unit (hereinafter, CPU) 52, a memory 53, a storage device 54, a display device 55, an input device 56, and a drive device 57. , They are interconnected via a bus 58.
[0025]
The CPU 52 executes a program using the memory 53 and implements processing required for layout design of the semiconductor device. The memory 53 usually includes a cache memory, a system memory, a display memory, and the like. The display device 55 is used for displaying a layout display, a parameter input screen, and the like. For this, a CRT, an LCD, a PDP, or the like is usually used. The input device 56 is used for inputting requests, instructions, and parameters from the user, and a keyboard and a mouse device are used for this.
[0026]
The storage device 54 generally includes a magnetic disk device, an optical disk device, a magneto-optical disk device, and the like. The storage device 54 stores programs and data for a semiconductor device design process. The CPU 52 transfers a program and data to the memory 53 in response to an instruction from the input device 56, and sequentially executes them. The program executed by the CPU 52 is provided on a recording medium 59. The drive device 57 drives the recording medium 59 and accesses the stored contents. The CPU 52 reads the program from the recording medium 59 via the drive device 57 and installs the program in the storage device 54.
[0027]
As the recording medium 59, any recording medium such as a magnetic tape, a memory card, a flexible disk, an optical disk (CD-ROM, DVD-ROM,...), And a magneto-optical disk (MO, MD,...) Can be used. . Then, the above-described program can be stored in the recording medium 59, and can be used by loading it to the memory 53 as needed. The recording medium 59 includes a medium recording a program uploaded or downloaded via a communication medium, and a disk device.
[0028]
FIG. 7 is a layout diagram of a semiconductor device in which a three-terminal capacitor (Dep-Tr11) is arranged.
As shown in the figure, in the layout design of a semiconductor device, a plurality of cell columns 62a and 62b (only two are shown in the figure) are formed on a semiconductor chip 61. Each of the cell columns 62a and 62b includes various cells (regions defined in each of the cell columns 62a and 62b) for configuring a circuit mounted on the chip 61. In such a layout design, the cells 63 constituting the above-described three-terminal capacitor (Dep-Tr11) are arranged in each of the cell columns 62a and 62b.
[0029]
More specifically, the three-terminal capacitance formed in each signal line 19 is formed of a MOS transistor, and the shape of the cell 63 is the same as the other cells. For this reason, the cell 63 can be arranged at an arbitrary location, similarly to other cells arranged in each of the cell columns 62a and 62b. That is, at the time of layout design, it is possible to automatically arrange the cells 63 in the respective cell columns 62a and 62b using a general CAD device (computer system 51) as shown in FIG.
[0030]
As described above, the present embodiment has the following advantages.
(1) On the signal line 19 for transmitting a digital signal inside the semiconductor device, a three-terminal capacitor composed of the Dep-Tr 11 is formed. A three-terminal capacitor using the Dep-Tr 11 can produce a large capacitance with a small chip area as compared with a capacitor that is a two-terminal capacitor. Thereby, high frequency noise and radiation noise can be effectively removed.
[0031]
(2) The gate capacitance of the depletion-type transistor (Dep-Tr11) can be increased (compared to the case where an enhancement-type transistor described later is used). Therefore, the effect of removing high-frequency noise can be further enhanced.
[0032]
(3) The area of the three-terminal capacitor using the Dep-Tr 11 can be reduced as compared with the case of using a two-terminal capacitor, so that the cost can be reduced.
(4) By using the Dep-Tr 11, they can be automatically arranged at the time of layout design using a general CAD device. As a result, the three-terminal capacitor (Dep-Tr11) can be easily formed in the chip using the existing manufacturing process (without requiring a special manufacturing process). This also facilitates verification work after layout design and contributes to cost reduction.
[0033]
(5) By using the Dep-Tr11, it is possible to easily form a three-terminal capacitor in a chip, such as the bus signal line 19a, the clock signal line 19b, and the power supply line 19c, at any place where noise reduction measures are required. Is possible.
[0034]
(Second embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to FIG. This embodiment describes an embodiment in which the configuration of a three-terminal capacitor (Dep-Tr11) formed in each signal line 19 is partially changed. Hereinafter, the same components as those of the first embodiment will be described with the same reference numerals.
[0035]
FIG. 8 is a conceptual diagram of a four-terminal capacitor using an enhancement-type MOS transistor (hereinafter, Enh-Tr).
As shown in FIG. 8A, the Enh-Tr 71 is, for example, an N-channel MOS transistor formed on a P-type substrate 72. The P-type substrate 72 has an N-type MOS transistor forming a source electrode 73 and a drain electrode 74. A diffusion layer is formed, and a gate electrode (polysilicon gate) 76 is formed on the substrate 72 with a gate oxide film 75 therebetween. A gate control voltage VDD is applied to the gate electrode 76. That is, when a positive voltage (gate control voltage VDD) exceeding a predetermined threshold voltage is applied to the gate electrode 76, the Enh-Tr 71 has a conductive channel between the source electrode 73 and the drain electrode 74 (not shown). Abbreviation) is formed. As in the first embodiment, the Enh-Tr 71 is provided with the source electrode 73 and the drain electrode 74 connected to the signal line 19 so as to be interposed on the signal line 19.
[0036]
FIG. 8B is an equivalent circuit of FIG. The Enh-Tr 71 forms a channel between the source and the drain by the gate control voltage VDD applied to the gate electrode 76, so that the gate electrode 76 and the channel oppose each other with the signal line 19 interposed therebetween. It acts as two electrodes provided. Thus, the Enh-Tr 71 substantially functions as a three-terminal capacitor having a gate capacitance and a junction capacitance with respect to the substrate potential (ground GND), as in the first embodiment (Dep-Tr 11). The inductances L11 and L12 formed on the signal line 19 are parasitic inductances generated when a digital signal propagates through the source electrode 73 and the drain electrode 74 of the Enh-Tr 71.
[0037]
As in the first embodiment, such a four-terminal capacitor composed of the Enh-Tr 71 can be easily formed in a chip by using an existing manufacturing process, and when a normal capacitor is used. It is possible to produce a large capacity with a small area as compared with the case. Therefore, the same effects as in the first embodiment can be obtained.
[0038]
(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to FIG. In this embodiment, another form is described as a noise removing unit formed on the signal line 19. Hereinafter, the same components as those in the above embodiments will be described with the same reference numerals.
[0039]
FIG. 9 is a conceptual diagram of a three-terminal capacitor using a wiring capacitor.
In the present embodiment, as shown in FIG. 9A, a first wiring 81 is provided on the same wiring layer with an oxide film 82 interposed therebetween so as to be parallel to the signal line 19 (in the drawing, in a direction perpendicular to the paper surface). Then, a second wiring 83 provided above the wiring layer is connected to the first wiring 81 via a contact 84. The first and second wirings 81 and 83 are wirings having a potential other than the ground potential (GND).
[0040]
In such a configuration, as shown in FIG. 9B, first and second wirings 81 and 83 surrounding the signal line 19 are provided so as to face each other with the signal line 19 interposed therebetween. It functions as an electrode and substantially functions as a three-terminal capacitor due to the wiring capacitance of each of the wirings 81 and 83 with respect to the substrate potential (ground GND). That is, when this configuration is used, high-frequency noise can be effectively removed by the wiring capacitances of the first and second wirings 81 and 83 that surround the signal line 19 over substantially the entire length.
[0041]
Each of the above embodiments may be implemented in the following manner.
In the first embodiment, the N-type diffusion layer 13 is formed on the P-type substrate 12 to form the N-channel type Dep-Tr 11, but the N-type substrate is used to form the P-channel type Dep-Tr 11. Is also good. Further, it may be formed using a well structure. That is, a method of forming a three-terminal capacitor using a depletion-type transistor is not limited to FIG. 1A described in the first embodiment.
[0042]
In the second embodiment, an N-type diffusion layer (a source electrode 73 and a drain electrode 74) is formed on a P-type substrate 72 to form an N-channel type Enh-Tr 71. May be formed. Further, it may be formed using a well structure. That is, a method for forming a three-terminal capacitor using an enhancement-type transistor is not limited to FIG. 8A described in the second embodiment.
[0043]
As the noise removing means formed inside the semiconductor device, Dep-Tr11, Enh-Tr71, or wiring capacitance according to the signal line 19 (bus signal line 19a, clock signal line 19b, power supply line 19c, etc.) into which it is inserted. May be used to form a three-terminal capacitor.
[0044]
【The invention's effect】
As described in detail above, according to the present invention, it is possible to provide a semiconductor device and a method of designing a semiconductor device that can enhance the effect of removing high-frequency noise generated in a signal line.
[Brief description of the drawings]
FIG. 1 is a conceptual diagram of a three-terminal capacitor using a depletion-type transistor.
FIG. 2 is a schematic diagram showing a case where a three-terminal capacitor is inserted into a bus signal line.
FIG. 3 is a schematic diagram showing a case where a three-terminal capacitor is inserted into a clock signal line.
FIG. 4 is a schematic diagram showing a case where a three-terminal capacitor is inserted into a power supply line.
FIG. 5 is an explanatory diagram showing a comparison of attenuation characteristics between a three-terminal capacitor and a two-terminal capacitor.
FIG. 6 is a schematic configuration diagram of a computer system.
FIG. 7 is a layout diagram of a semiconductor device in which three-terminal capacitors are arranged.
FIG. 8 is a conceptual diagram of a four-terminal capacitor using an enhancement transistor.
FIG. 9 is a conceptual diagram of a three-terminal capacitor using a wiring capacitor.
FIG. 10 is a conceptual diagram showing a conventional noise removal method.
FIG. 11 is a conceptual diagram showing a conventional noise removal method.
[Explanation of symbols]
11 Depletion-type MOS transistor 19 as a three-terminal capacitance 19 Signal line 19a as a wiring Bus signal line 19b Clock signal line 19c Power supply line 71 as a power supply wiring Enhancement-type MOS transistor 81 as a three-terminal capacitance 81 First Wiring 83 of the second wiring

Claims (10)

In a semiconductor device including a noise removing unit for removing noise generated in a wiring in a semiconductor chip,
2. The semiconductor device according to claim 1, wherein the noise removing unit is a three-terminal capacitor including a MOS transistor formed in the semiconductor chip so as to be interposed between the wirings. 2. The semiconductor device according to claim 1, wherein at least one of said three-terminal capacitors is formed for each wiring in said semiconductor chip. 3. The three-terminal capacitor according to claim 1, wherein a source electrode and a drain electrode of a MOS transistor are connected to the wiring, and a gate capacitance and a junction capacitance act on the wiring. Semiconductor device. 4. The semiconductor device according to claim 1, wherein the three-terminal capacitor is a depletion-type MOS transistor. 5. 4. The semiconductor device according to claim 1, wherein the three-terminal capacitor is an enhancement-type MOS transistor in which a gate control voltage for forming a channel is applied to a gate electrode. . In a semiconductor device including a noise removing unit for removing noise generated in wiring in a semiconductor chip,
The noise removing unit includes a first wiring provided on the same wiring layer in parallel with the wiring, and a second wiring provided on the wiring layer and connected to the first wiring via a contact. And a wiring having a three-terminal capacitor. 7. The semiconductor device according to claim 1, wherein the three-terminal capacitance is formed on a plurality of bus signal lines provided corresponding to the number of bits of input / output data. 8. The semiconductor device according to claim 1, wherein the three-terminal capacitance is formed on a clock signal line for supplying a clock signal into the semiconductor chip. 9. The semiconductor device according to claim 1, wherein the three-terminal capacitor is formed in a power supply line. A method of designing a semiconductor device according to claim 1, wherein:
A method of designing a semiconductor device, wherein the three-terminal type capacitor is arranged in each cell column formed at the time of layout of the semiconductor device.

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