JP2004030578A - 仮想入出力の相互接続メカニズム - Google Patents

仮想入出力の相互接続メカニズム Download PDF

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Publication number
JP2004030578A
JP2004030578A JP2003063486A JP2003063486A JP2004030578A JP 2004030578 A JP2004030578 A JP 2004030578A JP 2003063486 A JP2003063486 A JP 2003063486A JP 2003063486 A JP2003063486 A JP 2003063486A JP 2004030578 A JP2004030578 A JP 2004030578A
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Japan
Prior art keywords
module
address
computer system
transaction
original
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Pending
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JP2003063486A
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English (en)
Japanese (ja)
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JP2004030578A5 (enExample
Inventor
Debendra Das Sharma
ディベンドラ・ダス・シャルマ
Ashish Gupta
アシシ・グプタ
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HP Inc
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Hewlett Packard Co
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Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2004030578A publication Critical patent/JP2004030578A/ja
Publication of JP2004030578A5 publication Critical patent/JP2004030578A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2005—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication controllers

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
JP2003063486A 2002-03-08 2003-03-10 仮想入出力の相互接続メカニズム Pending JP2004030578A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/092,603 US6832270B2 (en) 2002-03-08 2002-03-08 Virtualization of computer system interconnects

Publications (2)

Publication Number Publication Date
JP2004030578A true JP2004030578A (ja) 2004-01-29
JP2004030578A5 JP2004030578A5 (enExample) 2006-04-27

Family

ID=31186094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003063486A Pending JP2004030578A (ja) 2002-03-08 2003-03-10 仮想入出力の相互接続メカニズム

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US (1) US6832270B2 (enExample)
JP (1) JP2004030578A (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7861158B2 (en) * 2001-07-26 2010-12-28 Irise System and process for gathering, recording and validating requirements for computer applications
US7096306B2 (en) * 2002-07-31 2006-08-22 Hewlett-Packard Development Company, L.P. Distributed system with cross-connect interconnect transaction aliasing
JP4202709B2 (ja) * 2002-10-07 2008-12-24 株式会社日立製作所 ストレージ装置を有するネットワークにおける、ボリューム及び障害管理方法
US7793287B2 (en) * 2003-10-01 2010-09-07 Hewlett-Packard Development Company, L.P. Runtime virtualization and devirtualization of I/O devices by a virtual machine monitor
US7913226B2 (en) * 2003-10-01 2011-03-22 Hewlett-Packard Development Company, L.P. Interposing a virtual machine monitor and devirtualizing computer hardware at runtime
US7512836B2 (en) * 2006-12-11 2009-03-31 International Business Machines Corporation Fast backup of compute nodes in failing midplane by copying to nodes in backup midplane via link chips operating in pass through and normal modes in massively parallel computing system
US7827333B1 (en) * 2008-02-04 2010-11-02 Nvidia Corporation System and method for determining a bus address on an add-in card
EP2625606A4 (en) 2010-10-08 2014-11-26 Irise SYSTEM AND METHOD FOR EXTENDING A VISUALIZATION PLATFORM
US8593918B1 (en) * 2011-06-30 2013-11-26 Emc Corporation Maintaining tape emulation consistency
US8601209B1 (en) * 2011-06-30 2013-12-03 Emc Corporation Maintaining dasd and tape continuous availability
US9817709B2 (en) * 2011-11-11 2017-11-14 Level 3 Communications, Llc Systems and methods for automatic replacement and repair of communications network devices
US8924779B2 (en) * 2012-03-30 2014-12-30 Lsi Corporation Proxy responder for handling anomalies in a hardware system
US9645766B1 (en) 2014-03-28 2017-05-09 EMC IP Holding Company LLC Tape emulation alternate data path

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
US6233702B1 (en) * 1992-12-17 2001-05-15 Compaq Computer Corporation Self-checked, lock step processor pairs
US5784625A (en) * 1996-03-19 1998-07-21 Vlsi Technology, Inc. Method and apparatus for effecting a soft reset in a processor device without requiring a dedicated external pin
US6742136B2 (en) * 2000-12-05 2004-05-25 Fisher-Rosemount Systems Inc. Redundant devices in a process control system
US6717909B2 (en) * 2001-06-05 2004-04-06 Marconi Communications, Inc. Ethernet protection system providing fault tolerence for communication lines and interface cards according to classified failure states

Also Published As

Publication number Publication date
US20040078647A1 (en) 2004-04-22
US6832270B2 (en) 2004-12-14

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