JP2004028870A - Level display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the trouble caused by the mismatching between the sampling period of input signals and the displaying period of levels. <P>SOLUTION: A level display device which displays the level of input signals by means of a plurality of display segments is provided with a sampling means which samples the input signals in accordance with a first clock and a control means which is constituted to display the level of the input signals in the display segments in accordance with a second clock which is lower in frequency than the first clock. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a level display device including a plurality of display segments.
[0002]
[Prior art]
In general, many level meters used to display the level of an input signal such as an audio signal use an LED, LCD, FL tube, or the like as a display element, and as shown in FIG. The segment corresponding to the level to be displayed is lit, and the signal level is expressed by the number and length of the lit segments.
[0003]
In the case of this type of display format, if the signal processing is digital, the digital data obtained by A / D conversion of the input signal indicates the amplitude value as it is, so that the digital data corresponding to the input signal and the display segment are lit. It can be realized by comparing the thresholds and controlling the lighting and extinguishing.
[0004]
FIG. 9 is a block diagram showing the processing, 101 is a signal input terminal, 102 is an A / D converter, 103 is an absolute value converter, 104 is the threshold value of each segment and A / D converted data. 105, a segment display group for displaying the result of the comparator group 104, and 106, a clock for A / D conversion.
[0005]
In this configuration, the input analog signal is A / D converted for each clock corresponding to the sampling frequency of 106. If the input signal is an audio signal, the signal is an AC signal having a positive / negative amplitude. Therefore, when A / D conversion is performed, if the data has a negative value, the amplitude does not directly indicate the magnitude of the amplitude.
[0006]
Therefore, it is necessary to convert a negative signal into a positive amplitude value. This is performed by the absolute value conversion of 103. The data converted into the absolute value is compared with the threshold value of each segment displayed at 104, and if it exceeds the threshold value, a lighting signal is output. This comparison is performed for each new digital data.
[0007]
That is, since the data becomes new for each sampling frequency, control is performed with the clock of 106, and the level display is updated for each sample value to enable continuous display.
[0008]
The operation of this process will be described using a specific waveform. FIG. 10 shows a signal waveform of an audio signal, and FIG. 10A shows an input waveform of the audio signal, in which the horizontal axis represents time and the vertical axis represents amplitude. The vertical line indicates the timing for each sampling frequency, and the circles in the figure indicate sample values. In this example, there are 33 pieces of data from sample values 0 to 32.
[0009]
As described above, since the audio signal is an AC signal, a negative signal is turned upside down and only the positive direction is used as shown in FIG. That is, take the absolute value.
[0010]
FIG. 3C shows that the signal is put into one of 11 divided frames in the amplitude direction and converted into data in the process of quantization of the signal. FIG. 11 shows a display for each time on the eleven segment displays corresponding to the quantized data.
[0011]
[Problems to be solved by the invention]
However, in the above-described conventional method, the updating of display is processing at each timing determined by the sampling frequency. Therefore, when the sampling frequency is 48 kHz, for example, when the sampling frequency is 48 kHz, 48000 data per second are updated. Occurs. Therefore, the processing itself becomes complicated, and a processing circuit having a high speed is required.
[0012]
Further, the response of the display device, for example, the liquid crystal is not as fast as the sampling frequency, and the display is not reflected on each data.
[0013]
In addition, when the response of the display device is fast, the response of the eyes of the viewer cannot catch up with the response, and a momentary peak may be missed. On the other hand, a display device such as an LCD having a low lighting speed as a display means may not light up in some cases, so that there is a problem that the level display function cannot be realized.
[0014]
For example, consider a case where an LCD is used as a display device. It is known that the response speed of LCD is about several hundred milliseconds. When the sampling clock is 48 KHz, if the cycle of one clock is about 20 μsec and the response of the LCD is 100 msec, the display will not be correct unless the duration of 4800 sampling clocks is maintained.
[0015]
In order to solve such a problem, an LED having a fast response is added only to the maximum level, and this is not an effective means in terms of cost.
[0016]
[Means for Solving the Problems]
In order to solve such a problem, according to the first aspect of the present invention, in a level display device for displaying the level of an input signal by a plurality of display segments, the input signal is sampled in accordance with a first clock. Sampling means for
Control means for displaying on the display segment in accordance with a second clock having a lower frequency than the first clock.
[0017]
According to the ninth aspect of the present invention, the level display means for displaying the level of the input signal by a plurality of display segments, the sampling means for sampling the level of the input signal at a predetermined cycle, and the sampling means Attenuating means for obtaining an attenuation level value obtained by attenuating a level value detected from a sampled input signal based on a predetermined attenuation characteristic; a level value detected from the input signal sampled by the sampling means; A level display device comprising: display control means for comparing a level value detected from a sampled input signal with an attenuation level value attenuated by the attenuation means, and displaying a larger one on the level display means. And
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a case where the level display device according to the present invention is applied to a recording / reproducing device will be described with reference to the drawings.
[0019]
The recording / reproducing apparatus needs to adjust the input signal to a level suitable for recording and record the input signal. For example, in a well-known analog tape recorder, when the recording level is low, a lot of noise, that is, so-called S / N is bad, and when the recording level is high, the tape as a recording medium is saturated, and distortion occurs. It becomes a sound.
[0020]
Also, even in the case of the digital recording method, if the recording level is low, quantization noise when digitizing is increased, and if the recording level is high, digital data is saturated and the sound is distorted.
[0021]
That is, in either system, a means for adjusting the recording level and a level display device for visually monitoring the level are required, and FIG. 1 shows an example including the device.
[0022]
In the figure, 101 is a signal input terminal, 102 is an A / D converter, 103 is an absolute value converter, 105 is a display composed of a segment display group consisting of a plurality of segments, and 104 is provided for each segment. A driver including a group of comparators for determining whether each segment is turned on or off by comparing the threshold value thus obtained with the A / D converted data. The driver 106 samples an input signal input from the input terminal 101. 107 is a first clock for A / D conversion, 107 is a peak hold circuit for holding the peak of data in the absolute value converter 103, 108 is a second clock for determining the cycle of updating the display on the display 105, Reference numeral 109 denotes a level adjuster for adjusting the recording level of the input signal.
[0023]
The second clock for determining the display update cycle is supplied to the arithmetic circuit 111 and also to the peak hold circuit 107, and resets the peak hold circuit 107. As a result, the peak hold circuit 107 outputs the peak values of a plurality of sample values sampled at the first clock cycle at the second clock cycle.
[0024]
An arithmetic circuit 111 controls the display of the segment group on the display 105 based on the peak value of the sample value of the input signal output from the peak hold circuit 107.
[0025]
The peak hold circuit 107 and the arithmetic circuit 111 are realized by software by the CPU 112 through the processing shown in the flowchart of FIG.
[0026]
Reference numeral 110 denotes recording / reproducing means for recording / reproducing the A / D-converted digital signal. In this configuration, the signal input from the input terminal 101 passes through the level adjuster 109 for performing the above-described level adjustment while the user looks at the level display 105, and the digital data is output by the A / D converter 102. Is converted to
[0027]
The digital data is recorded on a recording medium (not shown) by the recording / reproducing means 110. The clock that gives the conversion cycle of the A / D converter 102 is given from the clock 1 of 106, and is determined based on the sampling cycle corresponding to the audio band to be recorded. Since the input signal is an AC signal, it is treated as a positive number in the absolute value conversion of 103, and the value is used as data indicating the magnitude of the level.
[0028]
The peak value of this data is accumulated for a half cycle of the second clock. The half cycle of the frequency of the second clock is a cycle for updating the level display. From the viewpoint of reducing the amount of data to be processed for display, which is the object of the present invention, it is advantageous to use a lower frequency. The response of the display to the display becomes worse.
[0029]
When the frequency is increased with an emphasis on responsiveness, the degree of improvement in the complexity of the processing decreases. Since the detection capability of human eyes for a changing object is limited to several tens of msec, and a television broadcast using this is reproducing smooth movement at an interval of 30 frames (60 fields) per second, Regarding the frequency of the second clock, the frequency of the field of the television broadcast is considered to be the lowest frequency.
[0030]
Here, the A / D converter 102 driven by the first clock 106 corresponds to the sampling means in the claims of the present invention, and the peak value of the sampling value of the input signal is changed by the second clock 108 every field period. Is calculated according to the flowchart shown in FIG. 6 described below, and the CPU 112 that outputs the calculated result to the level indicator corresponds to the display control means.
[0031]
Next, processing executed in the CPU 112 will be described with reference to the flowchart in FIG. In the figure, the process is started in step 601 and the counter relation of the flow is reset in step 602. In order to explain with an example in which the display update cycle is a field cycle, the above-mentioned second clock 2 has a field frequency. In step 603, the end of the field is detected. In step 604, it is determined whether each sampling value in the current field is larger than the previous maximum value, and in step 605, the larger value is stored as DATAmax.
[0032]
When the end of the field comes, the process proceeds to step 606, where the number of display segments seg. Convert to DATA. By repeating the processing of these steps 603 to 604, the maximum value of the sampling value, that is, the peak value within one field period is output as DATAmax, and seg. It is converted to DATA and output at the field period.
[0033]
In step 607, seg. With respect to DATA, a level attenuated based on a predetermined attenuation characteristic is calculated using the time axis as a parameter, and in step 608, the calculation result is delayed by one field, and consequently, one field later should be taken according to the attenuation characteristic. Data on the number of display segments corresponding to the level is obtained. This attenuation processing corresponds to the control means of the present invention.
[0034]
Here, the attenuation characteristic will be described. Specifically, the dynamic range of the level display is set to a dB, and the time required for turning off all the lamps from the time of the maximum lighting is set to bsec. Since it has been confirmed that a logarithmic linear display attenuation characteristic can give a natural appearance without a sense of incongruity, the display update cycle is every field time. b = c fields, and it is better to provide an attenuation characteristic for each a / c dB. That is, if the real number corresponding to a / c dB is multiplied by the current display segment number, the next attenuated segment number to be displayed can be calculated.
[0035]
As described above, the peak value of the sample value supplied in the field period is not used as it is, but the peak value of the previous field is compared with the signal delayed by one field using the attenuation characteristic, and the higher level is displayed. , The actual signal level can be appropriately displayed in consideration of the attenuation level of the previous field.
[0036]
Step 609 is a memory variable seg. For storing the next display segment number. Next, data of the number of attenuated segments attenuated according to the attenuation characteristic and delayed by one field is stored in next.
[0037]
Step 610 is a display segment number data seg. Representing the peak value of the current field supplied from step 606. DATA and seg. DATA is the data seg. Of the number of display segments corresponding to the level to be attenuated after one field according to the attenuation characteristic. Next is compared.
[0038]
That is, seg. DATA is attenuated according to the attenuation characteristic, and the number of display segments to be taken one field later and the seg. DATA and compare seg. DATA is seg. If it is greater than next (yes), at step 612, the seg. DATA is set to the number of segments SEG to be actually displayed, the number of segments is turned on, and the level is displayed.
[0039]
On the other hand, in step 610, seg. next is seg. If it is not less than DATA (no), in step 611, the number of segments SEG to be actually displayed is changed to seg. Next, display is performed.
[0040]
By the processing of steps 610 to 612, the data seg. Of the display segment number corresponding to the peak value in the current field is displayed. DATA, seg., Which is a predicted value when the display segment number data one field before is attenuated for one field period. Next, the larger data is used as the actual number of display segments SEG, and the number of segments is turned on to display the level.
[0041]
DISP1: SEG in steps 611 and 612 indicates that the display segment number SEG is actually displayed on the level display. The display content is the peak value of the sample value of the input signal in the field period which is the update period, and is displayed in real time at the field period.
[0042]
Subsequently, in step 613, the peak hold value that has been displayed, that is, the number of display segments actually displayed is compared with the number of segments SEG to be displayed this time.
[0043]
As a result, seg. If DATA is large (yes), in step 616, the time for holding the number of display segments for displaying the level, that is, the hold counter (HOLD count) in which the number of fields is set, is reset. In step 617, the segment of the peak value to be displayed is displayed. The value (number) HOLD is set to the number of display segments seg. Replace with DATA.
[0044]
Subsequently, at step 615, the hold counter (HOLD count) is advanced by one, and at step 618, the peak hold value and the peak value of the previous field are displayed, and the process returns to step 603.
[0045]
That is, if the number of segments corresponding to the new signal level peak value exceeds the peak value before the step, the number of displayed segments is updated to the new number of segments, and the time to hold the peak value is set. Resets the counter to keep the hold state.
[0046]
If it is determined in step 613 that the previously displayed peak hold value HOLD, that is, the number of display segments actually displayed is larger than the number of segments SEG to be displayed this time (no), step 614 described later is performed. Move to the processing of.
[0047]
On the other hand, in step 610, seg. next is seg. If it is not less than DATA (no), in step 611, the number of segments SEG to be actually displayed is set to seg. Next, the process proceeds to step 614, and it is determined whether or not the time held by the hold counter, that is, the number n of fields has reached.
[0048]
As a result, if it has reached (yes), the process moves to the above-mentioned steps 616 and 617, and the hold counter (HOLD count) is reset to set a new display period.
[0049]
If it is determined in step 614 that the hold counter has not reached the holding time, that is, the number of fields n has not reached (no), the hold counter (HOLD count) is advanced by one in step 615, and in step 618 the peak hold value is set to the actual display segment number. Is converted to the data HOLDSEG corresponding to the above, and displayed on the level indicator as the display DISP2 of the peak hold value (DISP2: HOLDSEG), and the process returns to step 603.
[0050]
By the above processing, updating of the level display using a plurality of display segments is performed in the field cycle in consideration of the visual characteristics of the display, and the sampling value of the sampled input signal is the peak value in the display updating cycle. Since supply is performed as the number of display segments, optimum and efficient level display can be performed regardless of the sampling frequency.
[0051]
The above processing will be specifically described using a signal waveform.
[0052]
FIG. 2 shows a signal waveform of an audio signal in one field period which is an update cycle of the level display. In the figure, the horizontal axis represents time, and the vertical axis represents amplitude. The vertical line indicates the timing for each sampling frequency, and the circles in the figure indicate sample values.
[0053]
In this example, there are 33 pieces of data with sample values 0 to 32. As described above, since the audio signal is an AC signal, as shown in FIG. 3, a negative signal is turned upside down by the absolute value converter 103 and only the positive direction is used. That is, take the absolute value.
[0054]
FIG. 4 is a diagram showing a process of sampling the signal, converting the signal into a digital signal by the A / D converter 102, and quantizing the digital signal.
[0055]
In the figure, the sampling value is stored in one of 11 frames divided in the amplitude direction, quantized, and changed into digital data. Each sample value is peak-held, and as the new sample value exceeds the peak value, the peak value is updated. Thus, it is understood that the peak value is held for one field period, that is, for each cycle of the update cycle of the level display.
[0056]
FIG. 5 is a diagram showing a case where the peak value output at the field cycle is displayed as a level over a period of 32 fields as an example. The horizontal axis represents time, and the vertical axis represents a plurality of segments for display. The number of segments corresponding to the level is displayed for each field.
[0057]
In the figure, a level display segment (SEG) in which a gray segment 501 is actually turned on, and a white segment 502 are turned off. The segment with a circle indicates the peak value DATAmax detected for each field in the processing of steps 603 to 605, and the segment 503 displayed in black is a segment displaying the peak hold.
[0058]
A diagonal line 504 descending to the lower right from the peak value of each field indicates the attenuation characteristic of the peak value (step 607). In each field, the peak value DATAmax detected in that field and the DATAmax one field before are attenuated according to the attenuation characteristics in seg. Next is compared (step 610), and the larger segment is lit. For example, taking the field 3 as an example, the peak value of the field is the level corresponding to the segment 5, but since the level at which the peak value of the previous field is attenuated is the segment 7, the larger segment 7 is turned on. Have been.
[0059]
In addition, the peak value is displayed in real time for each field, and at the same time, the peak hold value is displayed. If no level exceeding that level is reached, the peak hold value is held for 5 fields after lighting (in this example, the peak hold time is 5 fields, and the count value n = 5 of the hold counter (HOLD count)). In FIG. 5, for example, fields 2 to 7) are updated (for example, fields 10 and 18) when a higher level peak value arrives within 5 field periods. If the peak value does not exceed the previous peak value even after the lapse of five field periods (fields 8, 16 and 26), the peak held level display is reset and a new peak value can be displayed. Understand. These processes correspond to the processes of steps 613 to 618.
[0060]
By the above-described processing, the peak value of the level is output for each field which is the display update cycle, the corresponding segment is turned on, the level is displayed in real time, and the peak is held at the same time with the five-field period being the longest. .
[0061]
FIG. 7 shows the level display state of FIG. 5 with the vertical axis replaced by the time axis of the field number.
[0062]
As described above, by updating the display every predetermined time period longer than the sampling period of the input signal, it is possible to reduce the complexity of signal processing, select a device that does not require high-speed processing, Software processing is also possible.
[0063]
In addition, the peak level can be displayed for a certain period of time. Furthermore, even in the case of an LCD having a slow response of the display device, it is possible to surely make the user recognize the digital full scale value display without adding a high-speed response element such as an LED to the display, thereby reducing cost. But it is advantageous.
[0064]
For example, when the display update cycle, that is, the second clock is 30 Hz and the sampling frequency is 48 kHz, the number of sample values in the clock is 1600, and the display processing is reduced to 1/1600. If the peak hold duration is 1 second, even a display element such as an LCD having a slow response speed retains 900 msec display even if the response is 100 msec, so that sufficient recognition is possible. .
[0065]
【The invention's effect】
As described above, according to the present invention, by updating the display every predetermined time period longer than the sampling period of the input signal, signal processing can be simplified, device selection that does not require high-speed processing, and microcomputer Software processing is also possible.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of the present invention.
FIG. 2 is a diagram showing a waveform of an input signal.
FIG. 3 is a diagram illustrating an absolute value of an input waveform.
FIG. 4 is a diagram used for describing a level display operation in the present invention.
FIG. 5 is a diagram used for explaining a level display operation in the present invention.
FIG. 6 is a level processing flowchart according to the present invention.
FIG. 7 is a diagram showing a change in level display in the level display device.
FIG. 8 is a diagram illustrating a configuration of a conventional level indicator.
FIG. 9 is a diagram illustrating a configuration of a level display device.
FIG. 10 is a diagram showing processing of an input signal waveform in a conventional level indicator.
FIG. 11 is a diagram showing a level display in a conventional level indicator.
[Explanation of symbols]
101 input terminal 102 A / D converter 103 absolute value detection 104 level comparison group 105 display element group 106 clock 1
107 Peak hold 108 Clock 2
109 level adjuster 110 recording / reproducing means

Claims (9)

In a level display device for displaying the level of an input signal by a plurality of display segments,
Sampling means for sampling an input signal according to a first clock;
Display control means for displaying on the display segment according to a second clock having a lower frequency than the first clock;
A level display device comprising: In claim 1,
The sampling means includes an A / D converter for digitizing an input signal and a peak detection means, and a sampling value of the input signal sampled in accordance with the first clock is used for a period of the second clock. A level display device, wherein a peak value is output from the device. In claim 2,
The level display device, wherein the peak detecting means holds a maximum value of an absolute value of a sample value of the input signal. In claim 1,
The display control means compares a level value output at the cycle of the second clock with an attenuation level value having a predetermined attenuation characteristic with respect to a previous level value, and displays a higher level value. A level display device, characterized in that the level display device is configured to: In claim 4,
The level display device, wherein the display control means performs display for holding the displayed level value for a predetermined period. In claim 5,
The level display unit is configured to update the held level value when a level value exceeding the held level value is output within the predetermined period. apparatus. In claim 1,
The display control means performs a first display for displaying a level value at a cycle of the second clock and a second display for holding the first display for a predetermined period in parallel. Display device. In claim 7,
The first indication is a peak value of the input signal output at the cycle of the second clock, and the second indication is to hold the peak value for a predetermined period longer than the cycle of the second clock. A level display device characterized by a peak hold display. Level display means for displaying the level of the input signal by a plurality of display segments;
Sampling means for sampling the level of the input signal at a predetermined cycle;
Attenuating means for obtaining an attenuation level value obtained by attenuating a level value detected from the input signal sampled by the sampling means based on a predetermined attenuation characteristic;
A level value detected from the input signal sampled by the sampling means is compared with an attenuated level value obtained by attenuating a level value detected from a previously sampled input signal by the attenuating means. Display control means for displaying on the level display means,
A level display device comprising:

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