JP2004015406A - Digital filter circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital filter circuit configured in multi-stages with its circuit scale reduced so that parameter setting and degree of the filter can be changed. <P>SOLUTION: The digital filter circuit comprises: a digital filter arithmetic circuit comprising multipliers 1 to 5, adders 7, 9, 19, and registers 8, 9; a register 10 for latching an output of the digital filter arithmetic circuit; a selector 17 for selecting a sample value input or an output of a feedback register as an input to the digital filter arithmetic circuit; and registers 11 to 15 the number of which is the same as that of the multipliers holding multiplication coefficients given to the multipliers, values held in the registers 8, 9 are saved after activating the digital filter arithmetic circuit, and the values saved in the registers 8, 9 are restored before activating the digital filter arithmetic circuit. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a digital filter configuration method, and more particularly to a digital filter circuit capable of reducing the circuit scale in a multistage digital filter.
[0002]
[Prior art]
Conventionally, when a bandpass filter is configured by an IIR (infinite impulse response) type subfilter, a plurality of highpass filters and lowpass filters are connected in series. Filter parameters of individual high-pass filters and low-pass filters are determined at the time of design and are hardened as semiconductor chips.
[0003]
FIG. 3 is a circuit diagram showing a configuration of a conventional bandpass filter in which such IIR type sub-filters are connected in multiple stages. In FIG. 3, sub-filters 31 and 32 are standard second-order IIR high-pass filters or low-pass filters. Here, N second-order IIR filters are used to form a 2 × N-order bandpass filter.
[0004]
The circuit configurations of the high-pass filter and the low-pass filter are the same, except that the multiplication coefficients for providing the parameters of the filter are different. The sub-filters 31 and 32 are respectively composed of multipliers 41 to 45 and 61 to 65, adders 46, 47, 51 and 66, 67, 71, data latch registers 48 to 50 and 68 to 70, and multiplication coefficients Is fixed by hardware in the semiconductor chip for each multiplier.
[0005]
[Problems to be solved by the invention]
In the above-described conventional band-pass filter configuration, a multiplier and an adder are included in each of the high-pass filters and the low-pass filters. If the required order is 2 × N, the multiplier and the adder are N times larger than one sub-filter. Vessel was required. For this reason, the number of transistors of these multipliers and adders becomes very large, leading to an increase in the cost of the semiconductor chip.
[0006]
In designing the filter, the parameters of the sub-filter and the order of the sub-filter (in this case, 2 × N) are designed so as to realize the desired filter characteristics, but the characteristics vary during the manufacturing process of the semiconductor chip. When such a problem occurs, it is impossible to change the parameter or the order even if the desired characteristics are not obtained.
[0007]
The present invention has been made in view of the problems of the conventional example, and has as its object to provide a digital filter circuit capable of reducing a circuit scale in a digital filter configured in multiple stages. Still another object of the present invention is to provide a digital filter circuit capable of setting and changing the parameters of a filter even after a semiconductor chip is manufactured and changing the filter order.
[0008]
[Means for Solving the Problems]
In order to achieve this object, a digital filter circuit according to claim 1 of the present invention comprises a multiplier (1 to 5), an adder (6, 7, 19) and a delay latch circuit (registers 8, 9). A digital filter operation circuit, a feedback register (10) for latching an output of the digital filter operation circuit, and a selector (17) for selecting a sample value input or an output of the feedback register as an input of the digital filter operation circuit And the same number of registers (11 to 15) as the multipliers for holding the multiplication coefficients to be given to the multipliers, and saving the values held in the delay latch circuit after operating the digital filter operation circuit. Before operating the digital filter operation circuit, the value saved in the delay latch circuit is restored. That the control means (microcomputer 16), in which comprises a.
[0009]
According to the above configuration, the digital filter operation circuit is repeatedly used, the sample value input is selected as the input of the digital filter operation circuit for the first time, the output of the feedback register is selected for the next time, and the register for holding the multiplication coefficient every time is selected. After updating the value and operating the digital filter operation circuit, the value held in the delay latch circuit is saved to a storage location corresponding to the number of times each time the digital filter operation circuit is operated. By restoring the stored value from the storage location corresponding to the number of times, the same operation as a cascade-connected digital filter with the number of repetitions can be performed, so that the digital filter can be used as a multistage digital filter. Greatly reduces the circuit size compared to a conventional multi-stage digital filter circuit. It is possible.
[0010]
Furthermore, according to the above configuration, the value of the register holding the multiplication coefficient is updated each time the digital filter operation circuit is repeatedly used. Even after the manufacture, the characteristics of the digital filter can be changed or adjusted.
[0011]
A digital filter circuit according to a second aspect of the present invention is the digital filter circuit according to the first aspect, wherein the setting of the multiplication coefficient in the register holding the multiplication coefficient is controlled by a microcomputer.
[0012]
According to the above configuration, since the setting of the multiplication coefficient is controlled by the microcomputer, it is possible to arbitrarily change or adjust the characteristics of the digital filter by software executed by the microcomputer.
[0013]
A digital filter circuit according to claim 3 of the present invention is the digital filter circuit according to claim 1 or 2, wherein the digital filter operation circuit is an infinite-length impulse response type digital filter circuit.
[0014]
According to the above configuration, in the digital filter circuit of the infinite-length impulse response type having the multi-stage configuration, the circuit scale can be significantly reduced as compared with the conventional one, and the characteristics can be changed even after the semiconductor chip is manufactured. You can make adjustments.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a digital filter circuit according to one embodiment of the present invention. In FIG. 1, 1, 2, 3, 4, and 5 are multipliers, 6, 7, and 19 are adders, and 8, 9 are registers for data latches. These constitute a standard IIR type filter circuit. I do.
[0016]
Further, in FIG. 1, reference numerals 11, 12, 13, 14, and 15 denote registers for holding multiplication coefficients to be applied to the multipliers 1, 2, 3, 4, and 5, respectively, 16 a microcomputer for controlling a filter circuit, and 17 a filter circuit. Is a flip-flop that controls the input selection of the selector 17, 20 is an input terminal, and 21 is an output terminal.
[0017]
In this embodiment, the data width to be filtered is 14 bits, the registers 11, 12, 13, 14, and 15 have a 14-bit configuration, and the data latch registers 8, 9, and 10 have a 30-bit configuration. The reason that 30 bits are required is that the input data is 14 bits, the multiplication coefficient is 14 bits, the carry that may be required after the multiplication is 1 bit, and the sign is 1 bit, for a total of 30 bits. However, the embodiment does not limit the number of bits, and it goes without saying that only the number of bits can be increased or decreased without changing the basic configuration.
[0018]
The data latch registers 8 and 9, the flip-flop 18, and the multiplier coefficient setting registers 11, 12, 13, 14, and 15 are provided with an address bus, a data bus, and a control signal for reading / writing data. It is connected to the microcomputer 16 and can be written by software executed by the microcomputer. The contents of the data latch registers 8 and 9 can be read out by software executed by a microcomputer.
[0019]
The input of the selector 17 is connected to the filter input from the input terminal 20 and the output of the register 10, and one of the inputs is selected by setting or resetting the flip-flop 18 from the microcomputer 16. In this embodiment, when the flip-flop 18 is 0, the filter input of the input terminal 20 is selected, and when the flip-flop 18 is 1, the output of the register 10 is selected.
[0020]
The output of the selector is connected to multipliers 1, 2, and 3, and the operation is performed by an IIR filter circuit including multipliers 1, 2, 3, 4, 5, adders 6, 7, 19, and registers 8, 9. The output is latched in the register 10 for feedback. The output of the register 10 is connected to the output terminal 21 and connected to the selector 17 as described above, so that the operation result of the filter circuit is fed back to the input.
[0021]
The operation of the digital filter circuit configured as described above will be described with reference to the flowchart shown in FIG. In order to use the circuit of FIG. 1 as a digital filter having a multi-stage configuration, first, in step 201, the number N of stages of the filter is set.
[0022]
In the present embodiment, instead of connecting the N-stage sub-filters in series, the digital filter of FIG. 1 is used N times to operate the digital filter having the multi-stage configuration. For this purpose, the contents of the registers 8 and 9 are saved each time the filtering operation of each stage is completed, and the saved values are restored in the registers 8 and 9 before the filtering operation of each stage is started.
[0023]
Since a storage location for saving the contents of the registers 8 and 9 is required at each stage, these storage locations are designated as R (k, 1) and R (k, 2) (k = 1 to N). In step 202, the initial values of R (k, 1) and R (k, 2) are set to 0.
[0024]
Next, in step 203, the process waits for the input of the sample value Si to the digital filter circuit. Each time the sample value Si is input, the processing of step 204 and subsequent steps is repeated N times to perform an N-stage filter operation. In order to perform the repetition control, the repetition variable k is set to 1 indicating the initial stage in step 204.
[0025]
Since the sample value Si is input to the digital filter circuit in the first stage, the flip-flop 18 is reset to 0 in step 205 so that the input of the selector 17 is set to Si. It is assumed that the value of the sample value Si is held by a latch circuit (not shown).
[0026]
Next, since k = 1, the multiplication coefficient of the first stage is set in registers 11 to 15 in step 206, and R (1,1) and R (1,2) are stored in registers 8 and 9 in step 207, respectively. To load. Thus, the digital filter circuit of FIG. 1 is ready to operate as the first stage digital filter. In step 208, a clock is supplied to the digital filter circuit to operate the filter circuit.
[0027]
In step 209, the contents of the registers 8 and 9 after the filter operation are saved to R (1,1) and R (1,2) to prepare for the first-stage operation when the next sample value Si is input. In step 210, the variable k is repeatedly compared with N. If k <N, the process proceeds to step 211, where 1 is added to k in preparation for the next-stage filter operation. In step 212, the flip-flop 18 is set to 1 so as to select the value fed back from.
[0028]
Returning again to step 206, k-stage multiplication coefficients are set in registers 11 to 15, and in step 207, R (k, 1) and R (k, 2) are loaded into registers 8 and 9, respectively. Thus, the digital filter circuit of FIG. 1 is ready to operate as a k-stage digital filter. In step 208, a clock is applied to the digital filter circuit to operate the filter circuit.
[0029]
In step 209, the contents of the registers 8 and 9 after the filter operation are saved in R (k, 1) and R (k, 2), and the operation of the k-th stage when the next sample value Si is input is prepared. In step 210, the variable k is repeatedly compared with N. If k <N, the process proceeds to step 211, and if k = N, the process returns to step 203 to wait for input of the next sample value Si.
[0030]
In this way, every time the sample value Si is input to the input terminal 20, the N-stage filter operation is performed, and the output terminal 21 obtains a 2 × N-order digital filter output time series.
[0031]
As is apparent from the above description, in the present embodiment, the parameters of the digital filter can be arbitrarily set by a microcomputer using software. Also, the number N of filters can be arbitrarily set by software. This makes it possible to arbitrarily change the characteristics of the filter even after the semiconductor chip is manufactured.
[0032]
Conventionally, the parameters and order of digital filters are calculated at the time of chip design, and are manufactured with the hardware in the semiconductor chip.Therefore, the characteristics designed in the event of being affected by characteristic fluctuations and manufacturing variations in the manufacturing process are affected. There was a problem that it could not be obtained. As described above, the present invention can solve this problem.
[0033]
Further, the conventional bandpass filter is configured by connecting a plurality of sub-filters in cascade, and the number of transistors constituting the filter has increased. According to the present invention, since it can be configured with only one circuit of a conventional sub-filter and a group of registers, the number of transistors can be significantly reduced.
[0034]
【The invention's effect】
As described above, according to the present invention, since the digital filter operation circuit can be used repeatedly, it can be used as a multi-stage digital filter, and the circuit scale is larger than that of a conventional multi-stage digital filter circuit. An excellent effect of greatly reducing the above can be obtained.
[0035]
Further, according to the present invention, the characteristics of the digital filter can be changed or adjusted even after the semiconductor chip is manufactured by changing the setting of the multiplication coefficient and the number of repetitions of the multiplier. An excellent effect that the characteristics of the filter can be arbitrarily changed can be obtained.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a digital filter circuit according to one embodiment of the present invention.
FIG. 2 is a flowchart illustrating an operation of the digital filter circuit according to one embodiment of the present invention.
FIG. 3 is a circuit diagram showing a configuration of a conventional multi-stage bandpass filter.
[Explanation of symbols]
1 to 5, 41 to 45, 61 to 65 Multipliers 6, 7, 19, 46, 47, 51, 66, 67, 71 Adders 8 to 10, 48 to 50, 68 to 70 Data latch registers 11 to 11 15 Register for multiplication coefficient 16 Microcomputer 17 Selector 18 Flip-flop 20, 52 Input terminal 21, 72 Output terminal 31, 32 Sub-filter

Claims (3)

A digital filter operation circuit including a multiplier, an adder and a delay latch circuit;
A feedback register for latching an output of the digital filter operation circuit;
A selector for selecting a sample value input or an output of the feedback register as an input of the digital filter operation circuit;
The same number of registers as the multiplier that holds a multiplication coefficient given to the multiplier;
Control means for saving the value held in the delay latch circuit after operating the digital filter arithmetic circuit and restoring the saved value in the delay latch circuit before operating the digital filter arithmetic circuit When,
A digital filter circuit comprising: 2. The digital filter circuit according to claim 1, wherein the setting of the multiplication coefficient in the register holding the multiplication coefficient is controlled by a microcomputer. 3. The digital filter circuit according to claim 1, wherein the digital filter operation circuit is an infinite-length impulse response type digital filter circuit.

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