JP2004014779A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, which is capable of restraining the reverse short channel characteristics of a first MOS element while preventing a second MOS element (high Vth MOS element) from deteriorating its short channel characteristics. <P>SOLUTION: A threshold voltage adjustment layer 9 for the second MOS element (high Vth MOS element) is formed after a first region 30 as a first MOS element forming region is masked with a resist film 8. Thereafter, a punch-through preventive layer 10 is formed by the use of the mask which is used when the threshold voltage adjusting layer is formed. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly, to a semiconductor device in which a first MOS element and a second MOS element operating at a higher gate voltage than the first MOS element are formed on one semiconductor substrate. The present invention relates to a technology that is effective when applied to the manufacture of a device.
[0002]
[Prior art]
In a peripheral circuit of an SRAM (Static Random Access Memory) memory cell, a MOS (Metal Oxide Semiconductor) element (low VthMOS element) operating at a relatively low gate voltage is used, while a peripheral cell is used in the memory cell. A MOS element (high VthMOS element) that operates at a higher gate voltage than a MOS element used in a circuit is used.
[0003]
Therefore, in order to manufacture an SRAM, it is necessary to form a low VthMOS element for a peripheral circuit of a memory cell and a high VthMOS element for a memory cell on a semiconductor substrate.
[0004]
These MOS elements having different operating gate voltages (also referred to as threshold voltages) are formed by injecting different concentrations of impurities into the channel formation region.
[0005]
In addition, a punch-through stopper structure is formed in the MOS element to prevent punch-through. As the punch-through stopper structure, for example, a two-stage halo structure in which an impurity is individually implanted into a shallow region where a channel is formed and a deeper region to suppress punch-through in a shallow region and punch-through in a deep region is used. Are known. In the two-stage halo structure, both the low VthMOS type device and the high VthMOS type device are formed under the same conditions (impurity concentration and energy to be implanted).
[0006]
2. Description of the Related Art In recent years, individual semiconductor elements have been miniaturized for higher integration of semiconductor devices. For example, MOS-type elements have been shortened in gate length. When the gate length of a MOS element is reduced, punch-through tends to occur because the source region and the drain region of the transistor are close to each other. For this reason, the dose of impurities for preventing punch-through has been increased.
[0007]
[Problems to be solved by the invention]
With an increase in impurities implanted to prevent punch-through, an inverse short-channel characteristic has emerged in which the threshold voltage of a short-gate-length MOS device becomes larger than that of a long-gate-length MOS device. In particular, the inverse short channel characteristic is more conspicuous in a low VthMOS device than in a high VthMOS device. This inverse short channel characteristic is empirically considered to decrease the current driving capability of the element, and is considered to adversely affect the performance improvement of the entire semiconductor device.
[0008]
Therefore, in order to suppress the above-described reverse short channel characteristic, it is conceivable to reduce the dose of the impurity implanted for preventing punch-through.
[0009]
However, the reverse short channel characteristic of the low VthMOS element is more remarkable than that of the high VthMOS element. However, the structure for suppressing the punch-through in the high VthMOS element and the low VthMOS element requires the same conditions (impurity concentration and (Implantation energy). Therefore, when the dose of the impurity is reduced so that the reverse short channel characteristic of the low VthMOS element can be suppressed, in the high VthMOS element, a short channel characteristic (short channel characteristic means that a channel is formed when the gate length is reduced). However, there is a problem that deterioration of the threshold voltage is greatly increased.
[0010]
In other words, if the impurity for punch-through prevention is dosed at a concentration at which the deterioration of the short channel characteristics (Vth-Lowering characteristics) of the high VthMOS device does not become large and conspicuous, the reverse short channel characteristics generated in the low VthMOS device cannot be suppressed. There was a point.
[0011]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device and a method of manufacturing a semiconductor device capable of suppressing the reverse short-channel characteristic of a low VthMOS element while preventing the short channel characteristic of a high VthMOS element from deteriorating.
[0012]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0013]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0014]
The method of manufacturing a semiconductor device according to the present invention includes a step of forming a first MOS-type element in a first region of a semiconductor substrate, wherein the first MOS-type element has the same conductivity type as the first MOS-type element. Forming a second MOS element operating at a higher gate voltage than the first MOS element in a second region of the semiconductor substrate, wherein the step of forming the second MOS element comprises Forming a resist film for masking one region on the semiconductor substrate; adjusting a threshold value of a gate voltage of the second MOS element by impurity implantation using the resist film as a mask; Forming a punch-through preventing layer for preventing punch-through by implanting impurities using the mask used in the step of adjusting the gate voltage threshold of the second MOS element. It is intended.
[0015]
In addition, the semiconductor device according to the present invention includes a semiconductor substrate, an element isolation layer separating a first region and a second region of the semiconductor substrate, a first MOS element formed in the first region, A second MOS-type element having the same conductivity type as the first MOS-type element, the second MOS-type element being formed in the second region and operating at a higher gate voltage than the first MOS-type element; A punch-through preventing structure formed on the first MOS element for preventing punch-through and a punch-through preventing structure formed on the second MOS element for preventing punch-through are different from each other. It is.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.
[0017]
(Embodiment 1)
FIG. 14 is a sectional view showing a section of an element portion of a semiconductor device according to an embodiment of the present invention.
[0018]
14, the element portion of the semiconductor device according to the embodiment includes a P-type semiconductor substrate 1, (an example of a semiconductor substrate), an element isolation layer 4, and a first region 30 formed in the first region 30 of the P-type semiconductor substrate 1. It comprises a MOS (Metal Oxide Semiconductor) element and a second MOS element formed in the second region 40 of the P-type semiconductor substrate 1.
[0019]
The P-type semiconductor substrate 1 is configured such that, for example, an impurity (boron or the like) is added to single-crystal silicon, and conductivity is mainly performed using holes on the valence band as carriers.
[0020]
The element isolation layer 4 is configured to separate the formation region (first region 30) of the first MOS type device from the formation region (second region 40) of the second MOS type device. It is composed of an insulator such as silicon.
[0021]
The first MOS-type element is an NMOS-type element in which an N-type channel is formed when a voltage equal to or higher than a threshold voltage is applied. Impurity diffusion layers 13a and 13b, high-concentration N-type impurity diffusion layers 18a and 18b, and two-stage punch-through stopper layers 15a and 15b are formed.
[0022]
A gate electrode 12 is formed above the threshold voltage adjusting layer 7 with a gate insulating film 11 interposed therebetween. A side spacer 17 is formed on a side surface of the gate electrode 12. Note that a cobalt silicide film 20 is formed on the high concentration N-type impurity diffusion layers 18a and 18b and on the gate electrode 12.
[0023]
The threshold voltage adjustment layer 7 is formed by implanting a P-type impurity (for example, boron), and has a threshold voltage (Vth) lower than a threshold voltage of a second MOS element described later. Impurities have been implanted to operate. Therefore, it can be said that the first MOS element is a low Vth MOS element compared to the second MOS element.
[0024]
The two-stage punch-through stopper layers 15a and 15b are formed over two stages so as to prevent punch-through at a shallow portion where the threshold voltage adjustment layer 7 is formed and at a deeper portion where the threshold voltage adjusting layer 7 is formed. Of the MOS type element is formed. The two-stage punch-through stopper layers 15a and 15b are formed by implanting a P-type impurity, and are formed with an optimum concentration capable of suppressing the reverse short channel characteristic in the first MOS element.
[0025]
Next, the second MOS-type element is an NMOS-type element in which an N-type channel is formed when a voltage equal to or higher than the threshold voltage is applied. A punch-through prevention layer 10, low-concentration N-type impurity diffusion layers 14a and 14b, high-concentration N-type impurity diffusion layers 19a and 19b, and two-stage punch-through stopper layers 16a and 16b are formed.
[0026]
A gate electrode 12 is formed above the threshold voltage adjustment layer 9 with a gate insulating film 11 interposed therebetween. A side spacer 17 is formed on a side surface of the gate electrode 12. Note that a cobalt silicide film 20 is formed on the high concentration N-type impurity diffusion layers 19a and 19b and on the gate electrode 12.
[0027]
The threshold voltage adjusting layer 9 is formed by implanting a P-type impurity (for example, boron), and operates at a threshold voltage (Vth) higher than the threshold voltage of the first MOS element. As shown in FIG. That is, the threshold voltage adjusting layer 9 has more impurities implanted than the threshold voltage adjusting layer 7 of the first MOS type device. Therefore, it can be said that the second MOS element is a high Vth MOS element compared to the first MOS element.
[0028]
The two-stage punch-through stopper layers 16a and 16b are formed over two stages so as to prevent punch-through at a shallow portion where the threshold voltage adjusting layer 9 is formed and at a deeper portion where the threshold voltage adjusting layer 9 is formed. Is formed by injecting impurities. The two-stage punch-through stopper layers 16a and 16b are formed under the same conditions (concentration and energy to be implanted) as the two-stage punch-through stopper layers 15a and 15b of the first MOS type device.
[0029]
The punch-through prevention layer 10 is configured to suppress punch-through, and is formed by implanting a P-type impurity. This punch-through prevention layer 10 is formed using the mask used when forming the threshold voltage adjustment layer 9. Therefore, the punch-through prevention layer 10 can be formed without increasing the number of masks.
[0030]
The punch-through prevention layer 10 is formed only on the second MOS type element, and is not formed on the first MOS type element.
[0031]
The punch-through prevention structure of the second MOS element is formed by two-stage punch-through stopper layers 16a and 16b and a punch-through prevention layer 10, and is formed by two-stage punch-through stopper layers 15a and 15b. This is different from the punch-through stopper structure of the MOS type element. Therefore, in each element, a punch-through stopper structure can be formed under independent optimum conditions (such as concentration).
[0032]
In other words, the two-stage punch-through stopper layers 16a and 16b are formed with an optimum concentration capable of suppressing the reverse short-channel characteristic in the first MOS element, but have a short-channel characteristic in the second MOS element. It is formed at a concentration at which the deterioration becomes apparent. However, by providing the anti-punch-through layer 10 in the second MOS element, it is possible to prevent short channel characteristics from deteriorating.
[0033]
As described above, according to the semiconductor device in the embodiment, the first MOS element (low-voltage characteristic) is prevented from deteriorating the short channel characteristic (Vth-Lower characteristic) of the second MOS element (high-Vth MOS element). VthMOS type device) can be suppressed.
[0034]
Hereinafter, steps of manufacturing an element portion of a semiconductor device according to the embodiment will be described with reference to FIGS.
[0035]
First, as shown in FIG. 1, a P-type semiconductor substrate 1 (an example of a semiconductor substrate) is prepared. Next, a silicon nitride film 2 is deposited on one surface (main surface) of the P-type semiconductor substrate 1 by using a CVD method, and thereafter, is patterned by a photolithography technique and an etching technique. The patterning is performed so that the silicon nitride film 2 does not remain in a region where an element isolation groove 3 (Shallow Groove Isolation) is to be formed.
[0036]
Next, the P-type semiconductor substrate 1 is etched as shown in FIG. Then, an insulating film made of, for example, silicon oxide is deposited on the P-type semiconductor substrate 1 in which the element isolation grooves 3 are formed by using the CVD method. After that, the P-type semiconductor substrate 1 is polished by using a CMP (Chemical Mechanical Polishing) method. Then, the element isolation layer 4 is formed by removing the patterned silicon nitride film 2 as shown in FIG. The first region 30 and the second region 40 of the P-type semiconductor substrate 1 are separated by the element isolation layer 4.
[0037]
Next, as shown in FIG. 4, an impurity (for example, boron) is implanted into the first region 30 and the second region 40 of the P-type semiconductor substrate 1 by using an ion implantation method, and the P well 5 and the P well 6 are formed. Form. Note that an N well is formed in another region of the P-type semiconductor substrate 1, but is omitted here, and only the P well is illustrated.
[0038]
Then, as shown in FIG. 5, for example, boron is implanted near the surfaces of the first region 30 and the second region 40 by using an ion implantation method to form the threshold voltage adjusting layer 7. This threshold voltage adjustment layer 7 is formed so as to adjust the threshold of the first MOS element (low VthMOS element).
[0039]
Next, after a resist is applied on the P-type semiconductor substrate 1, exposure and development are performed to form a patterned resist film 8. The patterning is performed so that the resist film 8 remains in the first region 30 as shown in FIG.
[0040]
Then, as shown in FIG. 6, using the resist film 8 formed in the first region 30 as a mask, boron fluoride (BF ₂ ) is implanted near the surface of the second region 40, for example, at about 21 nm from the surface at 25 keV. A threshold voltage adjusting layer 9 for two MOS devices (high VthMOS devices) is formed. This threshold voltage adjusting layer 9 is formed by injecting the above-mentioned boron fluoride into the threshold voltage adjusting layer 7 for the first MOS element (low VthMOS element). The dose of the impurity in the threshold voltage adjusting layer 9 is on the order of 10 ¹² / cm ² .
[0041]
Next, a punch-through prevention layer 10 is formed in a region (for example, 82 nm) deeper than the threshold voltage adjustment layer 9 using the same mask as that used when the threshold voltage adjustment layer 9 is formed as shown in FIG. I do. That is, the punch-through prevention layer 10 is formed by changing the energy for implanting impurities while using the same mask. Therefore, when the punch-through layer 10 is formed in the second MOS element (high VthMOS element), there is an advantage that the number of masks is not increased.
[0042]
The implanted impurity is, for example, B (boron) implanted with an energy of 20 to 25 KeV, and the dose of the impurity in the anti-punchthrough layer 10 is, for example, about 1 × 10 ¹³ / cm ² .
[0043]
Next, after removing the resist film 8 formed in the first region 30, a gate insulating film 11 made of an oxynitride film is formed as shown in FIG. The oxynitride film can be formed, for example, by performing a heat treatment on the P-type semiconductor substrate 1 in a gas atmosphere containing nitrogen, such as nitrogen monoxide (N0), nitrogen dioxide (NO ₂ ), or ammonia (NH ₃ ).
[0044]
Thereafter, an N-type polysilicon film is deposited on the gate insulating film 11 by using the CVD method. Then, as shown in FIG. 9, a gate electrode 12 (for example, a gate length of 80 nm) made of N-type polysilicon is formed in the first region 30 and the second region 40 by using a photolithography technique and an etching technique.
[0045]
Next, as shown in FIG. 10, an N-type impurity (for example, P (phosphorus)) is implanted into the source formation region and the drain formation region of the first region 30 and the second region 40 by using an ion implantation method. The low concentration N-type impurity diffusion layers 13a and 13b and the low concentration N-type impurity diffusion layers 14a and 14b are formed.
[0046]
Next, as shown in FIG. 11, a two-stage punch-through stopper layers 15a and 15b and two-stage punch-through stopper layers 16a and 16b are formed by implanting a P-type impurity using an ion implantation method.
[0047]
The two-stage punch-through stopper layers 15a, 15b, 16a, and 16b are formed by implanting a P-type impurity vertically into the P-type semiconductor substrate 1 and then changing the energy and implanting the P-type impurity at an angle. .
[0048]
Here, the two-stage punch-through stopper layers 15a, 15b, 16a, and 16b are formed under the same conditions, and have an optimum concentration that can suppress the reverse short-channel characteristic in the first MOS element (low VthMOS element). Is formed.
[0049]
Therefore, deterioration of short channel characteristics of the second MOS element (high VthMOS element) cannot be suppressed only by the two-stage punch-through stopper layers 16a and 16b. However, as described above, since the punch-through prevention layer 10 is separately formed in the second region 40, which is the second MOS element formation region, it is possible to prevent short channel characteristics from deteriorating.
[0050]
Next, after depositing silicon oxide on the surface of the P-type semiconductor substrate 1 on which the gate electrode 12 is formed by using the CVD method, the deposited silicon dioxide is removed by anisotropic etching. Then, as shown in FIG. 12, silicon oxide remains on the side surface of the gate electrode 12, and a side spacer 17 is formed.
[0051]
Thereafter, as shown in FIG. 13, an N-type impurity (for example, P (phosphorus)) is implanted into the source formation region and the drain formation region of the first region 30 and the second region 40 by using an ion implantation method. The concentration N-type impurity diffusion layers 18a and 18b and the high concentration N-type impurity diffusion layers 19a and 19b are formed.
[0052]
Next, after forming Co (cobalt) on the first region 30 and the second region 40 by using the sputtering method, a heat treatment is performed to form the cobalt silicide film 20.
[0053]
Thus, the first MOS element (low VthMOS element) can be formed in the first region 30 and the second MOS element (high VthMOS element) can be formed in the second region 40.
[0054]
According to the method of manufacturing the semiconductor device in the first embodiment, punch-through prevention layer 10 is formed using the mask used for forming threshold voltage adjusting layer 9 as it is, so that the mask is not increased. The punch-through stopper structure of the first MOS element (low-Vth MOS element) and the punch-through stopper structure of the second MOS element (high-Vth MOS element) can be made different, and the performance of each element can be improved. be able to.
[0055]
That is, the punch-through stopper structure of the first MOS-type element (low-Vth MOS-type element) and the punch-through stopper structure of the second MOS-type element (high-VthMOS-type element) can be made different from each other. The reverse short channel characteristic of the first MOS element (low VthMOS element) can be suppressed while preventing the short channel characteristic of the element (high VthMOS element) from deteriorating.
[0056]
In the first embodiment, the case where the first MOS element and the second MOS element are NMOS elements has been described as an example, but they may be PMOS elements. In this case, the threshold voltage adjustment layer 9 is formed by implanting P (phosphorus) at 20 keV, and the dose of the impurities in the threshold voltage adjustment layer 9 is on the order of 10 ¹² / cm ² .
[0057]
The punch-through prevention layer 10 is formed by implanting P (phosphorus) at 55 keV to 60 keV, and the dose of impurities in the punch-through prevention layer 10 is about 1 × 10 ¹³ / cm ² .
[0058]
(Embodiment 2)
In the first embodiment, the example in which the threshold voltage adjustment layer 9 and the punch-through prevention layer 10 are formed separately has been described. In the second embodiment, however, the threshold voltage adjustment layer and the punch-through prevention layer are once formed. An example will be described. The description of the same parts as in the first embodiment is omitted.
[0059]
As shown in FIG. 5, for example, boron is implanted in the vicinity of the surfaces of the first region 30 and the second region 40 by ion implantation to form the threshold voltage adjusting layer 7. This threshold voltage adjustment layer 7 is formed so as to adjust the threshold of the first MOS element (low VthMOS element).
[0060]
Next, after a resist is applied on the P-type semiconductor substrate 1, exposure and development are performed to form a patterned resist film 8. The patterning is performed so that the resist film 8 remains in the first region 30 as shown in FIG.
[0061]
Then, as shown in FIG. 15, using the resist film 8 formed in the first region 30 as a mask, ion implantation of a P-type impurity is performed to form the punch-through prevention layer 21. The ion implantation of the P-type impurity is performed such that the impurity concentration peaks at a position deeper than usual (for example, 21 nm). That is, the punch-through prevention layer 21 is a layer into which impurities are implanted from a normal depth to a deeper position, prevents punch-through, and also serves as a threshold voltage adjustment layer.
[0062]
Specifically, the impurity implanted in the punch-through prevention layer 21 is, for example, B (boron) implanted with an energy of 15 to 20 KeV, and the dose of the impurity in the punch-through prevention layer 21 is, for example, about 1 ×. 10 ¹³ / cm ² . Subsequent steps are the same as the steps described in the first embodiment, and a description thereof will be omitted.
[0063]
As described above, by applying the process of forming the threshold voltage adjusting layer, the punch-through prevention layer 21 existing only in the second MOS element (high VthMOS element) can be formed.
[0064]
Therefore, the punch-through stopper structure of the first MOS-type element (low-Vth MOS-type element) and the punch-through stopper structure of the second MOS-type element (high-VthMOS-type element) can be made different from each other. The reverse short channel characteristic of the first MOS element (low VthMOS element) can be suppressed while preventing the short channel characteristic of the element (high VthMOS element) from deteriorating.
[0065]
In the second embodiment, the case where the first MOS-type element and the second MOS-type element are NMOS-type elements has been described as an example, but they may be PMOS-type elements. In this case, the punch-through prevention layer 21 is formed by implanting P (phosphorus) at 55 keV to 60 keV, and the dose of impurities in the punch-through prevention layer 10 is about 1 × 10 ¹³ / cm ² .
[0066]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Needless to say.
[0067]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0068]
Since the punch-through stopper structure of the first MOS element (low VthMOS element) and the punch-through stopper structure of the second MOS element (high VthMOS element) can be different, the second MOS element ( The reverse short channel characteristic of the first MOS element (low VthMOS element) can be suppressed while preventing the short channel characteristic of the high VthMOS element from deteriorating.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an example of a manufacturing process of a semiconductor device.
FIG. 2 is a diagram illustrating an example of a manufacturing process of the semiconductor device.
FIG. 3 is a diagram illustrating an example of a manufacturing process of the semiconductor device.
FIG. 4 is a diagram illustrating an example of a manufacturing process of the semiconductor device.
FIG. 5 is a diagram illustrating an example of a manufacturing process of the semiconductor device.
FIG. 6 is a diagram illustrating an example of a manufacturing process of the semiconductor device.
FIG. 7 is a diagram illustrating an example of a manufacturing process of the semiconductor device.
FIG. 8 is a diagram illustrating an example of a manufacturing process of the semiconductor device.
FIG. 9 is a diagram illustrating an example of a manufacturing process of the semiconductor device.
FIG. 10 is a diagram illustrating an example of a manufacturing process of the semiconductor device.
FIG. 11 is a diagram illustrating an example of a manufacturing process of the semiconductor device.
FIG. 12 is a diagram illustrating an example of a manufacturing process of the semiconductor device.
FIG. 13 is a diagram illustrating an example of a manufacturing process of the semiconductor device.
FIG. 14 is a diagram illustrating an example of a manufacturing process of the semiconductor device.
FIG. 15 is a diagram showing another example of the manufacturing process of the semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 P-type semiconductor substrate 2 Silicon nitride film 3 Element isolation groove 4 Element isolation layer 5 P well 6 P well 7 Threshold voltage adjustment layer 8 Resist film 9 Threshold voltage adjustment layer 10 Punch through prevention layer 11 Gate insulating film 12 Gate electrode 13a Low-concentration N-type impurity diffusion layer 13b Low-concentration N-type impurity diffusion layer 14a Low-concentration N-type impurity diffusion layer 14b Low-concentration N-type impurity diffusion layer 15a Two-stage punch-through stopper layer 15b Two-stage punch-through stopper layer 16a 2 Step punch-through stopper layer 16b Two-step punch-through stopper layer 17 Side spacer 18a High concentration N-type impurity diffusion layer 18b High concentration N-type impurity diffusion layer 19a High concentration N-type impurity diffusion layer 19b High concentration N-type impurity diffusion layer 20 Cobalt silicide Film 21 Punch-through prevention layer 30 First region 40 Second region

Claims (4)

Forming a first MOS-type element in a first region of a semiconductor substrate;
Forming a second MOS element having the same conductivity type as the first MOS element and operating at a gate voltage higher than that of the first MOS element in a second region of the semiconductor substrate; And a step of
The step of forming the second MOS type device includes:
Forming a resist film for masking the first region on the semiconductor substrate;
Adjusting the threshold value of the gate voltage of the second MOS element by implanting impurities using the resist film as a mask;
Forming a punch-through preventing layer for preventing punch-through by implanting impurities using the mask used in the step of adjusting the gate voltage threshold of the second MOS element. A method for manufacturing a semiconductor device, comprising: Forming a first MOS-type element in a first region of a semiconductor substrate;
Forming a second MOS element having the same conductivity type as the first MOS element and operating at a gate voltage higher than that of the first MOS element in a second region of the semiconductor substrate; And a step of
The step of forming the second MOS type device includes:
Forming a resist film for masking the first region on the semiconductor substrate; and implanting impurities using the resist film as a mask to prevent punch-through and to set a threshold voltage of the gate voltage of the second MOS element. Forming a punch-through prevention layer for adjusting a value. A semiconductor substrate;
An element isolation layer for isolating a first region and a second region of the semiconductor substrate;
A first MOS type element formed in the first region;
A second MOS-type element having the same conductivity type as the first MOS-type element, the second MOS-type element being formed in the second region and operating at a higher gate voltage than the first MOS-type element; ,
What is different from the punch-through preventing structure formed on the first MOS-type element for preventing punch-through and the punch-through preventing structure formed on the second MOS-type element for preventing punch-through. A semiconductor device characterized by the above-mentioned. A semiconductor substrate;
An element isolation layer for isolating a first region and a second region of the semiconductor substrate;
A first MOS type element formed in the first region;
A second MOS element that is of the same conductivity type as the first MOS element and that is formed in the second region and that operates at a higher gate voltage than the first MOS element;
The second MOS element includes a threshold voltage adjustment layer formed by impurity implantation with the first region being masked;
And a punch-through prevention layer formed by using a mask used when forming the threshold voltage adjustment layer.

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