JP2004014633A - Locos offset type transistor and reference voltage generating circuit using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To overcome a problem that an impurity concentration is not the same within a gate depending on a position since an impurity is doped into the neighboring end of a gate also when the impurity is doped into a source region. <P>SOLUTION: Offsets are arranged by forming LOCOS regions 9 between the ends of an electrode of the gate G and a first diffusion region 8 to be the source/drain region. When the impurity is doped into the gate G, due to the offsets, the impurity can be doped only into the gate G. Since the offsets are arranged, the channel region under the electrode of the electrically isolated gate G is connected with the first diffusion region 8 through a second diffusion region 10. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a circuit for generating a reference voltage and a voltage having a desired temperature coefficient.
[0002]
[Prior art]
Japanese Patent Application Laid-Open No. 20001-228464 discloses a reference voltage generation circuit to which the principle of the work function difference between gates is applied, and the circuit is shown again in FIG.
[0003]
Referring to FIG. 10, a block composed of n-type channel field effect transistors (hereinafter simply referred to as transistors) M1, M2, M5 and resistors R1, R2 will be described. The transistors M1 and M2 have the same impurity concentration in the substrate and channel doping, and are both formed in the P well of the n-type substrate. The substrate potential of both transistors M1 and M2 is equal to the source potential (substrate terminal W is connected to the source), and the ratio (W / L) of gate channel width W to channel length L is also equal to each other. On the other hand, the transistor M1 has a high-concentration n-type gate, and the transistor M2 has a high-concentration p-type gate. Thus, both transistors M1 and M2 are a pair of transistors that differ only in the conductivity type of the gate.
[0004]
The transistor M1 has a constant current source by connecting the gate to the source. An output from a source follower circuit including an n-channel transistor M5, a resistor R1, and a resistor R2 is supplied to the gate of the transistor M2. By connecting the pair transistors M1 and M2 in series and flowing the same current, a voltage Vpn having a negative temperature coefficient is obtained as the gate-source voltage V1 of the field-effect transistor M2.
[0005]
Next, a block including n-channel transistors M3 and M4 will be described. The transistors M3 and M4 also have the same impurity concentration of the substrate and channel doping, and are both formed in the P well of the n-type substrate. The substrate potential of each of the transistors M3 and M4 is equal to the source potential, and the ratio (W / L) of the gate channel width W to the channel length L is also equal to each other. On the other hand, the transistor M3 has a high-concentration n-type gate, and the transistor M4 has a low-concentration n-type gate. As described above, the transistors M3 and M4 are a pair of transistors that differ only in the impurity concentration of the gate.
[0006]
The transistor M3 receives V2 (= R2 / (R1 + R2) * Vpn) as a gate voltage. The transistor M4 serves as a constant current source by connecting the gate to the source. By connecting the pair of transistors M3 and M4 in series and passing the same current to both transistors, a voltage -Vnn having a positive temperature coefficient is obtained as the gate-source voltage Vgs of the transistor M3.
[0007]
Therefore, the source potential V3 of the transistor M3 becomes
V3 = V2-Vgs = R2 / (R1 + R2) * Vpn-(-Vnn)
= R2 / (R1 + R2) * Vpn + Vnn
By adjusting the resistances of R1 and R2, a reference power supply having no temperature coefficient can be obtained.
[0008]
[Problems to be solved by the invention]
FIG. 7 shows a process of forming the transistor (M1, M3) having a high-concentration n-type (n +) gate and the transistor (M4) having a low-concentration n-type (n-) gate used in FIG. As shown in FIG. 7A, polysilicon 2 is deposited on the upper surface of P well region 1, and phosphorus is implanted only into a portion where polysilicon 2 is used as gate G using mask 3. The gate G is formed as a high-concentration n-type (n +) gate or a low-concentration n-type (n−) gate depending on the difference in the concentration of phosphorus implantation.
[0009]
Next, as shown in FIG. 7 (B), the polysilicon 2 other than the gate G is removed, and the gate G is covered with a mask 5 and then phosphorus implantation is performed, and the source region 6 and the drain region 7 are formed in the P well 1. Create At this time, phosphorus implantation is performed with the size of the mask 5 smaller than the original channel length L so that the formation of the source / drain regions is not hindered by the displacement of the mask 5. For this reason, phosphorus is implanted into both ends of the gate G, and high-concentration n-type (n +) is formed at both ends of the gate G.
[0010]
When the gate G is of a high concentration n-type (n +) as in the transistors M1 and M3, there is no problem because the entire gate becomes a high-concentration n-type (n +) and its concentration is the same as that of the source / drain region (n +). . However, when the gate G is a low-concentration n-type (n−) like the transistor M4, only the both ends are high-concentration n-type (n +), and the entire gate does not have a uniform concentration.
[0011]
FIG. 8 shows a process for forming the high-concentration p-type (p +) gate transistor (M2) used in FIG. FIG. 8A is the same process as FIG. 7B. At this point, the polysilicon 2 other than the gate G has already been removed. Although nothing is implanted into the gate G itself, both ends are made to be a high concentration n-type (n +) by phosphorus implantation.
[0012]
Next, in FIG. 8B, boron is implanted in order to form source and drain regions of another p-type channel field-effect transistor present on the substrate other than the reference power supply generating circuit. By this boron implantation, the gate G of the transistor M2 is made high-concentration p-type (p +) at the same time.
[0013]
However, the source region 6 and the drain region 7 of the transistor M2 have already been formed, and the region is covered with the mask 3 so that boron is not implanted into these regions. Or boron implantation must be performed narrower than the original channel length L. Therefore, since both ends of the gate G are not implanted with boron, the gate G remains n + and the entire gate G of the transistor M2 is not a high-concentration p-type (p +) gate.
[0014]
FIGS. 9A and 9B are experimental results showing the output Vpn and the output Vnn of the conventional paired field effect transistors M1 and M2 and the paired field effect transistors M3 and M4 manufactured as described above. The reason why the output is not constant when the channel length L is 40 μm or less is that when the channel length L is small, the influence of the gate ends of the transistors M2 and M4 becomes remarkable, and the transistors M1 and M2 and the transistors M3 and M4 do not. It is presumed that the pairing is not maintained.
[0015]
Therefore, in order to obtain stable outputs of Vpn and Vnn, that is, in order to obtain stable V3 (reference voltage), it is necessary to design each of the channel lengths L to be 40 μm or more, and the layout area increases. It has become.
[0016]
SUMMARY OF THE INVENTION An object of the present invention is to provide a field effect transistor capable of obtaining a stable output even if the channel length is made smaller in order to reduce the layout area.
[0017]
[Means for Solving the Problems]
In the field effect transistor of the present invention, as shown in the sectional structure of FIG. 1, a LOCOS region 9 as an oxide region is formed between an electrode end of a gate G and a first diffusion region 8 serving as a source / drain. Thus, an offset (LOCOS offset) is provided between the gate region G and the source / drain.
[0018]
Due to such an offset, when the impurity is implanted into the first diffusion region 8, the impurity can be implanted only into the first diffusion region 8. Impurities can be implanted only in the gate G.
[0019]
By providing the offset, the gate G and the first diffusion region 8 are electrically separated from each other, and do not function as a transistor. Therefore, in order to maintain the electrical connection between the two, a structure is adopted in which the channel region below the electrode of the gate G and the first diffusion region 8 are connected by the second diffusion region 10 located below them. Z indicates the upper surface of the substrate.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
FIGS. 2A, 2B, 3C, and 3D show a production process for realizing the configuration of the field-effect transistor in FIG. In this embodiment, a high-concentration n-type (n +) gate and a low-concentration n-type (n−) gate are formed in a P well in an N-type substrate.
[0021]
First, when fabricating a high-concentration n-type (n +) gate such as the transistors M1 and M3 and a low-concentration n-type (n−) gate such as the transistor M4, as shown in FIG. Is formed, phosphorus implantation is performed using the masks 3 and 5 to form the second diffusion region 7. The second diffusion region 7 is larger than the source region 6 and the drain region 7 in FIG. 7B, and is located below a gate G to be formed later.
[0022]
Next, as shown in FIG. 2B, the portion other than the LOCOS region 9 to be formed is covered with a nitride film 11, and the region is subjected to field oxidation to form the LOCOS region 9. The LOCOS region 9 is located between the gate G to be formed later and the source region 6 and the drain region 7, and has no conductivity even if impurities are implanted because it is an oxide insulating layer.
[0023]
Next, as shown in FIG. 2C, polysilicon 2 is deposited on the entire surface of the device including the LOCOS region 9, and phosphorus is implanted only into the portion of the polysilicon 2 to be the gate G using the mask 3. The gate G is formed as a high-concentration n-type (n +) gate or a low-concentration n-type gate (n−) depending on the concentration of phosphorus implantation.
[0024]
Finally, as shown in FIG. 3 (D), the polysilicon 2 other than the gate G is removed, the gate G is covered with a mask 5 and then phosphorus implantation is performed. Are formed, and these become the source region 6 and the drain region 7.
[0025]
At this time, (1) the size of the mask 5 is made larger than the channel length of the gate G, and (2) the size of the source region 6 and the drain or the region 7 so that the implanted phosphorus is not injected into both ends of the gate G. It is necessary to limit its size to such an extent that creation is not hindered.
[0026]
In the conventional structure, since the end of the gate G and the source / drain region are adjacent to each other, when phosphorus is implanted into one, a part thereof is also implanted into the other, but as in the present invention, Since the LOCOS region 9 is interposed between both ends of the gate G and the source / drain regions, the size of the mask 5 that can satisfy the requirements (1) and (2) can be easily set. As a result, the entire gate G of the transistors M1 and M3 can be a high-concentration n-type (n +) gate, and the entire gate G of the transistor M4 can be a low-concentration n-type (n−) gate.
[0027]
By providing the LOCOS region 9, the source region 6 / drain region 7 and the gate G are electrically insulated. Therefore, the second diffusion region 10 electrically connects them. The first diffusion region and the first diffusion region are substantially the same, so that the source region 6 (first diffusion region) functions integrally with the second diffusion region 10. The same applies to the drain region 7.
[0028]
In the process of FIG. 2C, when n + (high concentration) or n− (low concentration) phosphorus is implanted to form the gate G, a part of the second diffusion region 10 is n +. Although it is considered that there is no effect even if the GaAs is implanted into the other region, the LOCOS region 9 in the present invention makes it possible to completely eliminate the implantation into the other region.
[0029]
Next, a case where a high-concentration p-type (p +) gate such as a transistor M2 is formed in a P-well of an N-type substrate will be described. Until the LOCOS region 9 is formed, the same process as in FIGS. 2A and 2B is performed to form the second diffusion region 10 and the LOCOS region 9.
[0030]
Next, as shown in FIG. 3 (E), the portions other than the polysilicon 2 serving as the gate G are removed, and the polysilicon 2 in the region serving as the gate G is covered with a mask 5 and then phosphorus implantation is performed. A first diffusion region 8 serving as a drain region is created. However, at this time, the polysilicon itself in the region to be the gate G is not yet a high-concentration p-type (p +) gate.
[0031]
Finally, as shown in FIG. 3F, boron is implanted to form source / drain regions of other p-type channel field-effect transistors existing on the substrate other than the reference power supply generating circuit. However, at the same time when the boron is implanted, the source region 6 and the drain region 7 are covered with the mask 3, and then the gate of the transistor M2 is made high-concentration p-type (p +).
[0032]
Also in this case, in the process of FIG. 3E, when the phosphorus is implanted to form the source / drain regions, the size of the mask 5 is appropriately adjusted so that phosphorus is not implanted into both ends of the region serving as the gate G. The size of the mask 3 is appropriately adjusted so that boron is not implanted into the source / drain regions when boron is implanted to form the gate G in the process of FIG. You can choose. This makes it possible to make the entire gate G of the transistor M2 highly p-type.
[0033]
FIG. 4 is an experimental result showing the output Vpn of the field effect transistors M1 and M2 having the structure of the present invention and the output Vnn of the paired field effect transistors M3 and M4 with respect to the change of the channel length L. When fabricated as described above, the pairing is maintained between the transistors M1 and M2 and between the transistors M3 and M4. On the other hand, in the present invention, the size can be reduced to half, that is, 20 μm, and the layout area can be reduced.
[0034]
Although FIGS. 2 and 3 show an example in which an n-type channel field-effect transistor is formed, a LOCOS offset-type field-effect transistor can be obtained in the same manner with a p-type channel field-effect transistor.
[0035]
FIG. 5 shows a circuit that outputs a voltage Vpn having a negative temperature coefficient from the circuit of FIG. 10. FIG. 6 shows that the transistor M2 of a high-concentration p-type gate in FIG. It is replaced with a transistor M4 'and outputs a voltage Vnn having a positive temperature coefficient.
[0036]
Also in these circuits of FIGS. 5 and 6, if the field effect transistor according to the present invention is used, a voltage having a stable temperature coefficient can be output even if the gate channel length is reduced.
[0037]
The transistor according to the present invention can be applied not only to FIGS. 10, 5, and 6, but also to other circuits that require pairing.
[0038]
In the present invention, the LOCOS region 9 is formed in order to electrically separate the gate G from the source region 6 / drain region 7. However, any material can be used as long as the two can be separated.
[0039]
【The invention's effect】
As described above, according to the present invention, since the LOCOS region 9 is formed between the gate and the source / drain region to provide an offset, when the impurity is implanted into the source and the drain, the impurity can be prevented from being implanted into the gate. Therefore, the impurity concentration of the gate can be made uniform, and a transistor having high pairability can be formed. As a result, in a circuit such as a reference voltage generating circuit that requires a pair transistor, a highly stable reference voltage can be output even if the size is reduced.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a field-effect transistor according to the present invention. FIG. 2 is a process diagram showing an example of manufacturing the field-effect transistor of FIG. 1. FIG. 3 is a process showing an example of manufacturing the field-effect transistor of FIG. FIG. 4 is a diagram showing an output Vpn of a first voltage source circuit and an output Vnn of a second voltage source circuit using a field effect transistor having the structure of the present invention. FIG. 5 is an electric field according to the present invention. FIG. 6 is a circuit diagram for outputting a voltage having a negative temperature coefficient using a field effect transistor. FIG. 6 is a circuit diagram for outputting a voltage having a positive temperature coefficient using a field effect transistor according to the present invention. FIG. 8 is a process diagram showing a production example of a conventional field-effect transistor. FIG. 9 is a process diagram showing a production example of a conventional field-effect transistor. FIG. 9 is an output Vp of a first voltage source circuit using a conventional field-effect transistor. When, the diagram of FIG 10 shows a reference voltage generating circuit showing the output Vnn of the second voltage source circuit EXPLANATION OF REFERENCE NUMERALS
1 well region 3 mask 5 mask 6 source region 7 drain region 8 first diffusion region 9 LOCOS region 10 second diffusion region G gate

Claims (6)

A first voltage source circuit for outputting a voltage having a negative temperature coefficient by a field effect transistor pair having gates of different conductivity types;
A second voltage source circuit for outputting a voltage having a positive temperature coefficient by a pair of field effect transistors having gates of the same conductivity type and different impurity concentrations;
A reference voltage generating circuit comprising: a combining circuit that combines the two outputs at a predetermined ratio.
These field-effect transistors have a LOCOS region between a gate electrode end and a first diffusion region end, and a channel region below the gate electrode and the first diffusion region are connected by a second diffusion region. Reference voltage generation circuit. In a voltage generation circuit that outputs a voltage having a negative temperature coefficient by a field effect transistor pair having gates of different conductivity types,
These field-effect transistors have a LOCOS region between a gate electrode end and a first diffusion region end, and a channel region below the gate electrode and the first diffusion region are connected by a second diffusion region. Voltage generating circuit. In a voltage generating circuit that outputs a voltage having a positive temperature coefficient by a pair of field effect transistors having gates of the same conductivity type and different impurity concentrations,
These field effect transistors have a LOCOS region between a gate electrode end and a first diffusion region end, and connect a channel region below the gate electrode and the first diffusion region with a second diffusion region. Voltage generating circuit. In a field effect transistor having a high concentration p-type gate,
The field effect transistor has a LOCOS region between a gate electrode end and a first diffusion region end, and connects a channel region below the gate electrode and the first diffusion region with a second diffusion region. Field effect transistor. In a field effect transistor having a low concentration n-type gate,
The field effect transistor has a LOCOS region between a gate electrode end and a first diffusion region end, and connects a channel region below the gate electrode and the first diffusion region with a second diffusion region. Field effect transistor. A first voltage source circuit for outputting a voltage having a negative temperature coefficient by a field effect transistor pair having gates of different conductivity types;
A second voltage source circuit for outputting a voltage having a positive temperature coefficient by a pair of field effect transistors having gates of the same conductivity type and different impurity concentrations;
A reference voltage generating circuit comprising: a combining circuit that combines the two outputs at a predetermined ratio.
In these field-effect transistors, a LOCOS region is formed between a source region and a gate, and between a drain region and a gate region, respectively, and between a channel region below a gate electrode and a source region, and a gate electrode. A reference voltage generating circuit, wherein a second diffusion region is formed below a source region and a drain region so that a lower channel region and a drain region can be electrically connected to each other.

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