JP2004007019A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the reliability problem of a semiconductor device employing a thin and lightweight package caused by the warp of the package or the difference of thermal expansion coefficient between the device and a mounting board, e.g. the breaking of a conduction line provided in the semiconductor device or the failure of connection with a thin metal wire. <P>SOLUTION: The conduction line 40 composed of a crystal larger in the X axis-Y axis direction than in the Z axis direction is buried in an insulating resin 44 and the back of the conduction line 40 is exposed from the insulating resin 44 thus providing a sealed semiconductor device. The breaking of the conduction line 40 buried in the insulating resin 44 can thereby be suppressed. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a semiconductor device and a semiconductor module, and more particularly to a technique for preventing a failure due to a mismatch in a coefficient of thermal expansion when a semiconductor device is mounted on a mounting board.

2. Description of the Related Art Conventionally, in a hybrid integrated circuit device set in an electronic device, for example, a conductive pattern is formed on a printed circuit board, a ceramic substrate or a metal substrate, and an active element such as an LSI or a discrete TR, a chip capacitor, a chip A passive element such as a resistor or a coil is mounted. Then, the conductive pattern and the element are electrically connected to realize a circuit having a predetermined function.

FIG. 24 shows an example of the circuit. This circuit is an audio circuit, and the elements shown therein are mounted as shown in FIG.

In FIG. 25, the outermost rectangular line is the mounting substrate 1 on which at least the surface is insulated. On top of this, a conductive pattern 2 made of Cu is adhered. The conductive pattern 2 includes an external extraction electrode 2A, a wiring 2B, a die pad 2C, a bonding pad 2D, an electrode 4 for fixing the passive element 3, and the like.

ＴＲTR, a diode, a composite element, an LSI, or the like is fixed to the die pad 2C via a solder in the form of a bare chip. The electrodes on the fixed chip and the bonding pads 2D are electrically connected to each other through the thin metal wires 5A, 5B, and 5C. The thin metal wires are generally classified into a small signal and a large signal, and the small signal portion employs an Au line or an Al line 5A having a diameter of about 40 μmφ, and the large signal portion includes an Au line or an Al line having a diameter of about 100 to 300 μmφ. Has been adopted. In particular, since the large signal has a large wire diameter, the cost is taken into consideration, and the 150 μmφ Al wire 5B and the 300 μmφ Al wire 5C are selected.

{Circle around (2)} The power TR6 for flowing a large current is fixed to the heat sink 7 on the die pad 2C in order to prevent the temperature of the chip from rising.

{Circle around (2)} The wiring 2B is extended to various places in order to make the external extraction electrode 2A, the die pad 2C, the bonding pad 2D, and the electrode 4 into circuits. When the wirings cross each other due to the position of the chip and the way the wirings extend, jumping lines 8A and 8B are employed.

On the other hand, as a semiconductor device mounted on the mounting board 1, there is a semiconductor device packaged with an insulating resin. For example, a lead frame type semiconductor device in which a semiconductor chip is mounted on a lead frame and packaged with an insulating resin, a ceramic substrate, a printed circuit board or a flexible sheet is used as a support substrate, and the semiconductor chip is mounted thereon and the insulating resin is mounted. There is a support substrate type semiconductor device packaged in the above, and a plating type semiconductor device in which a semiconductor chip is mounted on a plating electrode and packaged including a plating electrode (see Patent Document 1 below).

A schematic diagram of this is shown in FIG. 26A. Reference numerals 10A to 10D denote conductive paths formed of a plating film. On the die pad 10A, a semiconductor chip 11 is fixed, and a bonding pad of the semiconductor chip 11 and a bonding pad 10B formed by plating are electrically connected by a thin metal wire 12. Connected. A passive element 13 is fixed between the electrode 10C and the electrode 10D via a brazing material. This semiconductor device. Since the plating film is embedded in the insulating resin without using the supporting substrate, a thin semiconductor device can be realized.
JP-A-3-94431

As described above, the semiconductor devices packaged by various methods are mounted on the mounting board 1. However, the lead frame type semiconductor device has a problem that the area occupied by the mounting substrate becomes large because the lead protrudes from the package, and there is a problem that the mounting substrate becomes large. Further, there are problems that the lead frame is cut or burrs are generated on the leads. Further, the supporting substrate type semiconductor device has a problem that the thickness of the semiconductor device is increased due to the use of the supporting substrate, and the weight is increased accordingly. Further, the plating type semiconductor device does not use a supporting substrate and the leads do not protrude from the package, so that a thin and small semiconductor device can be realized. However, there are problems in the following points.

FIG. 26B is a diagram for explaining this, and is a schematic enlarged view of a portion indicated by a circle in FIG. 26A. Reference numeral 10B indicated by an aggregate of triangular pyramids is a conductive path formed by plating, and reference numeral 17 is solder. Reference numeral 15 denotes a mounting substrate, and reference numeral 16 denotes a conductive pattern adhered to the mounting substrate 15.

メ ッ キ This plating film is generally formed by electrolytic plating and has a columnar crystal structure with a narrowed tip. This is indicated by a triangular pyramid in the figure. Since this film is thin and has a polycrystalline structure, it has a disadvantage that mechanical strength is weak and cracks are easily generated due to a difference in thermal expansion coefficient between the film and the insulating resin. Moreover, the crystal grain boundaries easily diffuse substances from the outside. For example, there is a problem that an external atmosphere gas such as a flux or moisture used for solder infiltrates the connection portion of the fine metal wire 12 through the crystal grain boundary, thereby deteriorating the connection strength. Further, when the electrode 11B is formed by Cu plating, there is a problem that the solder in the lower layer is diffused, the plated film itself is eaten by the solder, and the connection strength with the fine metal wire is deteriorated.

(4) If the plating film is formed to be thin and long as the wiring, the wiring may be disconnected due to a mismatch with the thermal expansion coefficient of the insulating resin. Similarly, when this plated semiconductor device is mounted on a mounting board, there is also a problem that cracks are generated in the wiring due to a mismatch with the thermal expansion coefficient of the mounting board, resulting in disconnection and an increase in wiring resistance. In particular, when an elongated wiring is formed on the plating electrode 10B, the stress is generated in proportion to the length. Therefore, there is a problem that the difference in the thermal expansion coefficient between the insulating resin 14 and the mounting substrate 15 makes the defect of the plating film more redundant and accelerates the reduction in reliability.

The present invention has been made in view of the above-described problems, and firstly, a plurality of conductive paths made of a conductive material having a large crystal growth in the X and Y directions, a semiconductor chip electrically connected to the conductive paths, The problem is solved by providing an insulating resin which covers the semiconductor chip and is filled in the separation groove between the conductive paths to expose the back surface of the conductive path and integrally support the same.

Here, as shown in FIG. 1A, a film whose growth in the Z-axis direction is larger than growth in the X-axis-Y axis direction is called a Z film, and a film whose growth in the X-axis direction is larger than that in the Z-axis direction. It is called an XY film. For example, the Z film is a plating film grown by electrolysis and electroless, and the XY film is a film formed by rolling, for example, a rolled copper foil.

As shown in FIG. 1C, when the XY film is viewed in cross section, since the crystals are stacked in such a manner that the respective crystals spread in the XY axis direction, the area of the crystal grain boundary is larger than that of the Z film in FIG. 1A. Is also suppressed. Accordingly, the phenomenon of diffusion or transmission through the crystal grain boundaries is significantly suppressed. Further, the Z film in FIG. 1B has a structure that is extremely weak against a stress caused by an external force that bends and extends left and right. However, as shown in FIG. 1C, the XY film becomes stronger than the Z film against warpage and breakage of the XY film itself. Therefore, cracks in the conductive path can be prevented from occurring due to a difference in thermal expansion coefficient of the insulating resin that seals the conductive path itself. Further, since the size of the crystal is large, the resistance of the entire conductive path itself can be reduced. In particular, when the thickness of the package is 0.5 mm or less and a conductive path is embedded in the package, the plane size is larger than the thickness. Stress is applied in the Y direction. However, since each crystal grows largely in the X-Y direction, the structure becomes strong against the stress.

For example, when an electrode made of rolled Cu foil is embedded in an insulating resin and when an electrode is embedded by Cu plating, the strength against the above-mentioned stress is better in a rolled copper foil, and contamination of a contact portion due to diffusion is also superior. Also, rolled copper foil is better.

Second, the problem is solved by drawing the back surface of the insulating resin and the side surface of the conductive path with substantially the same etched surface.

明瞭 As will become clear in the later manufacturing method, the insulating resin is embedded after the half etching, so that the half-etched curved structure has the shape of the insulating resin. This is characterized in that the anchor effect is generated and at the same time the contact resistance on the back surface is reduced. Therefore, the movement and self-alignment of the semiconductor device itself are facilitated.

Third, the problem is solved by forming the back surface of the conductive path so as to be recessed rather than the back surface of the separation groove.

(4) Since the conductive path is formed to be concave, the thickness of the solder formed on the conductive path can be increased, and the formation of the convex portion of the insulating resin prevents the adjacent solders from contacting each other.

Fourth, the problem is solved by forming an oxide of the conductive material on the surface of the conductive path in contact with the insulating resin.

銅 By forming copper oxide on the conductive path, particularly on the surface of a metal mainly composed of Cu, it is possible to improve the adhesion to the insulating resin.

Fifth, the problem is solved by the fact that the thickness of the insulating resin is substantially less than 1 mm, and the conductive path has a thickness that can be obtained by a rolling method.

Sixth, a plurality of conductive paths formed of crystals whose X and Y directions are larger than the Z axis, and conductive paths formed on the upper surface of the conductive paths and mainly formed of crystals whose Z axis directions are larger than the X axis and Y axis directions. A coating, a semiconductor chip electrically connected to the conductive coating, and an insulating resin that covers the semiconductor chip and is filled in a separation groove between the conductive paths to expose the back surface of the conductive path and integrally support the semiconductor chip. This is solved by providing

In principle, if the conductive patterns serving as electrodes and wirings are formed of an XY film, and a Z film is grown only in portions where electrical connection is required, it is better than forming all the conductive patterns with a Z film. Characteristics can be exhibited. For example, a semiconductor device excellent in disconnection and contamination of a connection portion is obtained.

Seventh, a plurality of conductive paths made of a crystal in which the X and Y directions are larger than the Z axis, and a conductive film formed on the upper surface of the conductive paths and mainly having a Z axis direction larger than the X axis and the Y axis direction; A semiconductor chip electrically connected to the conductive film, and an insulating resin that covers the semiconductor chip and is filled in a separation groove between the conductive paths to expose the back surface of the conductive path and integrally support the semiconductor chip. ,
The problem is solved by drawing substantially the same etched surface on the back surface of the insulating resin and the side surface of the conductive path.

Eighth, a plurality of conductive paths made of a crystal in which the X and Y directions are larger than the Z axis, a conductive film formed on the upper surface of the conductive path and having a large crystal growth mainly in the Z axis direction by plating, A semiconductor chip that is electrically connected to the semiconductor chip, and an insulating resin that covers the semiconductor chip and fills the separation groove between the conductive paths to expose and expose the back surface of the conductive path and integrally support the semiconductor chip;
The problem is solved by etching the side surface of the conductive path into a curved shape and drawing at least a part of the back surface of the insulating resin in a curve that is continuous with the etched surface.

Ninth, the problem is solved by drawing a continuous curve with the surface formed by non-anisotropic etching.

Tenth, the problem is solved by forming the back surface of the conductive path so as to be recessed rather than the back surface of the insulating resin.

Eleventh, the conductive path in contact with the insulating resin can be solved by forming an oxide on the surface.

１２Twelfth, the problem is solved by forming a conductive film on the back surface of the conductive path.

酸化 By coating the back surface of the conductive path with, for example, a metal film, solder, or the like, the oxidation of the conductive path can be prevented. Therefore, even if the circuit pattern on the mounting board is connected to the conductive path with a brazing material, the defect can be greatly suppressed because there is no oxide in the conductive path.

Thirteenth, the conductive film can be solved by forming an eave on the surface of the conductive path.

(4) Since the shape of the eaves can be realized by the conductive path and the conductive film or the conductive path itself, an anchor effect is generated, and detachment and peeling of the conductive path can be suppressed.

Fourteenth, the problem is solved by covering the conductive path exposed from the insulating resin with an insulating film except for an electrical connection portion.

場合 If there are various shapes of conductive paths, the brazing material will wet all areas. Therefore, at the same time as the amount of solder is different, the thickness of the solder is also different due to its size, surface tension, and its own weight. Therefore, by forming a film having poor solder wettability on the exposed conductive path, the area where the solder is wetted can be controlled, and a solder having a desired thickness can be formed on the back surface of the conductive path.

Fifteenth, the problem is solved by providing a wiring as the conductive path, and covering the conductive path exposed from the insulating resin with an insulating coating except for an electrical connection portion.

構造 In the structure of the semiconductor device, the back surface of the conductive path is exposed from the insulating resin. Therefore, the wiring as shown in FIG. 6, FIG. 7, and FIG. Therefore, when this semiconductor device is mounted on the mounting board, the conductive pattern and the wiring of the mounting board are short-circuited. However, the short circuit can be prevented by forming the insulating film.

Sixteenth, a plurality of conductive paths made of a conductive material whose crystal growth in the X and Y directions is larger than the Z axis; a conductive film formed on the upper surface of the conductive paths and mainly formed by crystal growth in the Z axis direction; A semiconductor chip electrically connected to the conductive film; and an insulating resin that covers the semiconductor chip and is filled in a separation groove between the conductive paths to expose the back surface of the conductive path and integrally support the semiconductor chip. The problem is solved by mounting the semiconductor device on the mounting board via the exposed portion.

Seventeenth, a plurality of conductive paths made of a conductive material whose crystal growth in the X and Y directions is larger than the Z axis, a conductive film formed on the upper surface of the conductive path and mainly formed by crystal growth in the Z axis direction, A semiconductor chip electrically connected to the conductive film, and an insulating resin covering the semiconductor chip and filling the separation groove between the conductive paths and exposing the back surface of the conductive path to integrally support the semiconductor chip, The problem is solved by mounting a semiconductor device in which the back surface of the insulating resin and the side surface of the conductive path draw a substantially continuous curve on the mounting substrate via the exposed portion.

Eighteenth, a plurality of conductive paths made of a conductive material whose crystal growth in the X and Y directions is larger than the Z axis, and a conductive film formed on the upper surface of the conductive paths and having a large crystal growth mainly in the Z axis direction by plating. A semiconductor chip electrically connected to the conductive film, and an insulating resin that covers the semiconductor chip and is filled in a separation groove between the conductive paths and exposes the back surface of the conductive path to integrally support the semiconductor chip. A side surface of the conductive path is etched into a curve, and at least a part of the back surface of the insulating resin is mounted on the mounting substrate via the exposed portion, with a semiconductor device substantially corresponding to the etched surface. This is the solution.

Nineteenth, the back surface of the conductive path and the mounting board are connected via a brazing material, and the back surface of the conductive path and / or the connection pattern on the mounting board are provided with a coating for preventing the flow of the brazing material. This is the solution.

When a plurality of conductive paths having different sizes are employed, the brazing material spreads so as to wet the entire conductive path, and the thickness of the brazing material formed on the back surface of the semiconductor device differs. The same phenomenon occurs in the conductive pattern on the mounting board side. Due to this phenomenon, the gap between the mounting board and the conductive path may be narrowed. However, by forming a film having poor wettability with respect to at least one of the brazing materials, the spread of the brazing materials can be suppressed, and the gap can be kept constant.

Twentiethly, the problem is solved by drawing substantially the same curve as the surface formed by the non-anisotropic etching.

Twenty-first, the problem is solved by forming the back surface of the conductive path so as to be recessed rather than the back surface of the insulating resin.

Twenty-second, the conductive path in contact with the insulating resin can be solved by forming an oxide on the surface.

Twenty-third problem is solved by forming a conductive film on the back surface of the conductive path.

Twenty-fourth, the conductive film can be solved by forming an eave on the surface of the conductive path.

As is clear from the above description, according to the present invention, a thin semiconductor device can be mounted in a wide range of forms such as a discrete type, a BGA type, a multi-chip type, and a hybrid type. In addition, since the semiconductor device is thin, warpage of the semiconductor device poses a problem. However, since the rolled XY film is used as the conductive path, it is possible to prevent the conductive path from being broken due to warpage or resin shrinkage. The electrical connection portion used as a semiconductor device employs an XY film as a lower layer to prevent contamination of the connection portion and to be resistant to aging or failure after packaging. Can be supplied to the user. In addition, the thin and long wiring is more easily subjected to the stress than other conductive paths. However, the adoption of the XY film makes it possible to suppress the disconnection of the wiring.

(4) The same etched surface is drawn on the back surface of the insulating resin and the side surface of the conductive path in order to adopt this manufacturing method. In particular, the back surface of the insulating resin is curved, and an empty area is formed in a portion adjacent to the curved portion. Therefore, it is possible to form a relief area for the melted solder and to reduce the friction coefficient of the back surface of the semiconductor device.

(4) After the half-etching, the conductive foil undergoes a heat treatment step of forming an oxide film, so that a Cu oxide is formed on the surface thereof. This oxide can improve the adhesion between the conductive foil and the insulating resin.

First, the size of the semiconductor device will be described with reference to FIG. The semiconductor chip 30 employed here is about 0.55 × 0.55 mm and 0.24 mm in thickness because a TR chip is used here. The size of the plane of the semiconductor device 31 is 1.6 × 2.3 mm and the thickness is 0.5 mm. The plane size of the semiconductor device is at least twice the plane size of the chip, and the thickness of the package is about twice or less the thickness of the chip, especially when mounted face-down, the thin metal wire does not extend upward. The thickness can be further reduced. That is, although it is thin, the plane size can be developed in various sizes from about 1 mm × 2 mm to a size far exceeding this size depending on the combination of the semiconductor element and the passive element described below.

As will be described later, as can be understood from consideration of FIGS. 6B, 7, 10, and 11, the semiconductor device can be used from a discrete package to a package constituting a circuit or a system, and can be made thin. Semiconductor device.

In the present semiconductor device, the conductive paths 32 to 34 are exposed on one surface, and the insulating resin 35 is coated from the conductive paths 32 to 34 to the other surface. Therefore, the insulating resin 35 has a larger shrinkage ratio and has a structure that is easily warped as a whole. Therefore, the use of the conductive paths 32 to 34 that can withstand this stress is required. In particular, the longer the wiring, the more important this problem becomes.

Furthermore, considering the increase in cost of the semiconductor device, the conductive paths 32 to 34 are as thin as about 30 to 50 μm or less, so that impurities and gases diffuse through the interface of the crystal grain boundaries and the electrical connection parts deteriorate. Needs to be comprehensively considered and adopted. In the case of mounting the power semiconductor element, the thickness of the conductive path is preferably 100 to 200 μm in consideration of current capacity and generated heat.

Generally, there are two types of materials used for the electrodes, a Z film shown in FIG. 1A and an XY film shown in FIG. 1C. As described in the section of the problem, the back surface of the conductive path 40 made of the Z film has a large number of interfaces, and as shown by arrows, a structure in which contaminants from the outside easily diffuse through the crystal grain boundaries 41. have. For example, the contaminant is a gas in an external atmosphere, such as moisture. When a brazing material is used, flux and the like are contaminants. This means that the fixing force of the thin metal wire 42 fixed to the Z film is deteriorated, and that the fixing force of the chip 43 die-bonded to the Z film is deteriorated.

Further, as shown in FIG. 1B, in response to the warpage caused by the contraction of the insulating resin 44, the Z film 40 causes the disconnection 49, or the gap between the respective crystal grains 45 even if the disconnection 49 does not occur. There is a problem that the resistance increases due to the spread. To prevent this, it is necessary to increase the thickness of the Z film 40 or to stack several layers of the Z film. However, this has a problem that the film formation time becomes long and the cost rises.

On the other hand, as shown in FIG. 1C, the exposed amount of the interface 47 on the back surface of the conductive path 46 made of the XY film is smaller than that of the Z film 40. In addition, since the crystal growth in the XY direction is large and the crystal grains 48 are stacked in multiple layers, diffusion of contaminants from the outside via the crystal grain boundaries 47 can be prevented as shown by arrows. Has features. This means that contamination of the surface of the conductive path 46 caused by the diffusion can be significantly suppressed.

{Circle around (4)} The XY film 46 is characterized in that the XY film 46 is less likely to cause disconnection and has a smaller resistance to warpage caused by contraction of the insulating resin 44. For example, a conductive foil made of a metal material processed by rolling is listed as the XY film.

FIG. 2 shows the bending characteristics of a rolled conductive foil (XY film) mainly composed of Cu and an electrolytic foil (Z film) treated by electrolysis. It can be seen that the conductive foil annealed after rolling and the conductive foil only rolled are much more resistant to breakage than the electrolytic foil.

In other words, as shown in FIG. 1D, it can be seen that by adopting the XY film for a conductive path having a large length and area, for example, a die pad, a bonding pad, or a wiring, the conductive path has excellent characteristics. In other words, it can be seen that the use of the XY film as the wiring shown in FIGS. 6 to 11 provides better characteristics than the wiring using the Z film.

In view of cost and resistance, rolled copper foil containing Cu as a main material is preferable. However, considering the fact that Cu is easily oxidized on the surface, the bondability of the fine metal wire is poor, and the bondability with the Au bump is poor, as shown in FIG. It is important to arrange 40. Further, even if warpage occurs and cracks 49 occur in the Z film 40, disconnection can be prevented because the XY film 46 is stably arranged in the lower layer.

In addition, it is said that a thickness of about 2 to 10 μm is excellent in bonding property in the Ag plating film, and it is said that the bonding property is deteriorated if the thickness exceeds this thickness. Also, it has been found that good bonding can be obtained with an Au plating film at a thickness of about 0.2 μm. This is said to be because as the film thickness increases, the growth rate of each crystal grain starts to differ greatly, and irregularities occur on the surface. It is said that between the Z film and the ball to be connected by bonding, only the Z film and the ball having irregularities are joined, and the connection strength between them is low and the connection resistance is high. However, even if a thin Z film is used to improve the bonding property, cracks and breaks are likely to occur in the wiring and the die pad, and the reliability is reduced on the contrary.

Therefore, in the present invention, the XY film 46 that is resistant to breakage is used as a conductive path such as the wiring 50, the die pad, and the bonding pad 51, and the XY film 46 is used as a support film if necessary. A Z film 40 is formed on the film 46. For example, a plating film of Ag, Au, Ni, Pd, or the like is used as necessary for a portion requiring bonding or solderability. However, considering the connection strength and cost, the Z-axis growth film 40 has a small thickness as described above. Therefore, all the conductive paths are not formed only by the Z film, and the XY film 46 functions as a support film and a protective film, and the Z film 40 is provided thereon, thereby deteriorating characteristics such as disconnection of the conductive path and increase in resistance. Has been prevented.

FIG. 3 illustrates this point. In FIG. 3, a crack 49 is generated in the Z film 40 and divided into two regions 40A and 40B. However, since the two Z-axis growth films 40A and 40B are electrically connected by the XY film 46, the two Z-axis growth films are equivalently electrically connected, resulting in a disconnection failure. It is explained that it does not become. The arrows also indicate that the XY film 46 serves as a barrier film against intrusion from the external atmosphere, thereby preventing the surface of the Z film 40 from being contaminated.

Ｄ In FIG. 1D and FIG. 3B, the following features occur in addition to the features described above. A curved structure 52 or an eave 53 is provided on the side surface of the XY film 46, and the XY film 46 embedded in the insulating resin 44 is not peeled off by this structure, and is embedded in a stable state. . Therefore, the Z film 40 provided thereon is maintained in a more stable state.

FIG. 4 shows the conductive foil 54 that has been half-etched before being sealed with the insulating resin 44. A Cu oxide film (Cu2O, CuO) 55 is generated on the surface excluding the region where the Z film 40 is formed, and this oxide film 55 improves the chemical bonding with the insulating resin 44 as a sealing material. Describes that the adhesion between the conductive path and the insulating resin is improved.

4A, the Z film 40 is formed on the entire upper surface of the conductive path 56, and in FIG. 4B, the oxide film 55 is exposed except for the main region. In FIG. 4B, since the copper oxide 55 is exposed more than in FIG. 4A, the adhesiveness of the upper surface of the conductive path 56 is further improved.

{Circle around (5)} When the isolation groove 57 is formed in the conductive path 56 by half-etching, the following effects also occur by performing non-anisotropic etching. First, since the curved structure 52 and the eaves 53 are generated, the anchor effect is generated, and at the same time, the area of the copper oxide 55 is expanded more than the straight separation groove, and there is an advantage that the adhesiveness with the insulating resin is improved.

Finally, the rigidity will be described with reference to FIG. 2B. The lower diagram of FIG. 2B shows that the present conductive foil 54A is handled in a shape like a lead frame and is attached to a mold. A semiconductor maker adopts a lead frame to perform transfer molding, and has an advantage in that the present semiconductor device can be manufactured using a mold employed here. Although the present invention will be apparent from the description of FIGS. 14 to, since the conductive foil 54 is half-etched and attached to a mold, the rigidity is considered in consideration of ease of handling and the point of being sandwiched between upper and lower molds. Is required. Impurities can be easily added to the conductive foil by rolling due to the manufacturing method, and the rigidity can be increased. The table in FIG. 2B shows the weight percentage of the impurities. In type A, Ni, Si, Zn, and Sn are mainly used as impurities. Type B contains Zn, Sn, and Cr as impurities. Further, in the type C, Zn, Fe, and P are mixed. The types and weight percentages of the impurities shown in this table are merely examples, and may be any as long as the conductive foil containing Cu as a main material has rigidity.

On the other hand, if an attempt is made to form a conductive foil only with a plating film, it is difficult to add impurities due to the manufacturing method, and the conductive foil is made of substantially pure Cu. Therefore, the conductive foil has a problem that it is soft and the workability is reduced, and a support substrate for supporting the conductive foil is required.

Generally, the larger the size of the lead frame, the more semiconductor devices are required. However, as the size increases, the workability is reduced due to warping or bending. In the present invention, a rectangular conductive foil having a length of 220 mm, a width of 45 mm, and a thickness of 70 μm is employed. In addition, generally adopted lead frames have a length of up to about 250 mm, a width of up to about 75 mm, a thickness of up to about 0.5 mm. Can be adopted.

Now, the structure of the semiconductor device will be specifically described. The present invention provides a discrete type in which one TR is sealed, a BGA type in which one IC or LSI is sealed, a multi-chip type in which a plurality of TRs or a plurality of ICs are mounted, or a plurality of TRs, ICs and / or passive elements are mounted, wiring is used as a conductive path, and a desired circuit can be roughly classified into a hybrid type or the like. In other words, it is important that most packages of a semiconductor device can be realized by one method.

First Embodiment for Explaining Discrete Semiconductor Device FIG. 5 shows a package of a TR, which is embedded in an insulating resin 35 and the back surfaces of the conductive paths 32 to 34 are exposed.

Reference numerals 32 to 34 denote conductive paths serving as a collector electrode, a base electrode, and an emitter electrode, and the surface thereof is coated with Ag as a Z film 36 as shown in FIG. 5C. The Z film 36 is a film that enables wire bonding and die bonding, and may be Au, Pd, Ni, or the like. Since the conductive paths 32 to 34 are etched non-anisotropically, the side surfaces thereof have a curved structure 52, and an eave 53 can be formed on the surface of the conductive path. Therefore, by adopting at least one of them, an anchor effect with the insulating resin 35 can be generated. Further, the insulating resin 35 is embedded in the separation groove 57 formed by half-etching, and the insulating resin 35 exposed from the back surface of the semiconductor device 31 has the outer shape of the package. Since the separation groove 57 is formed by half-etching and the bottom is curved, there is also a feature that the friction coefficient of the chip can be reduced. Further, since the bottom of the separation groove 57 protrudes from the back surfaces of the conductive paths 32 to 34, a short circuit between the conductive paths can be prevented, and further, there is an advantage that a thicker connection material such as solder can be formed.

FIG. 5E shows a semiconductor device in which the semiconductor chip 30 is mounted face down. For example, a solder ball is formed on the surface of a semiconductor element and is melted in a conductive path. When the gap between the semiconductor chip 30 and the conductive path becomes very narrow and the permeability of the insulating resin 35 is poor, an underfill material 37 having a low viscosity and easily penetrating into the gap is employed. In this case, unlike FIG. 5D, the underfill material 37 is filled in the separation groove 57 and becomes one element of the outer shape. Further, as shown in FIGS. 5D and 5E, the conductive path is exposed. Therefore, an appropriate conductive material is selected and covered to electrically connect to the circuit pattern of the mounting board. For example, as shown in FIG. 5F, a brazing material SL such as solder, a plating material such as Au or Ag, a conductive paste, or the like is formed on the exposed portion.

(5) Since the thickness of the brazing material differs because the exposed conductive paths have different areas, the insulating film 38 may be coated on the back surface as shown in FIG. 5G to make the exposed shape substantially constant.

As described at the beginning of the embodiment of the present invention, even when a semiconductor chip having a thickness of about 0.55 × 0.55 mm and a thickness of 0.24 mm is molded, the semiconductor device 31 has a size of 1.6 × 2.3 mm, It can be seen that a very thin semiconductor device having a thickness of 0.5 mm or less can be realized and is suitable for use in portable equipment, computer equipment, and the like.

Second Embodiment Explaining Multi-Chip (or Hybrid) Semiconductor Device Next, FIG. 6 shows a hybrid or multi-chip semiconductor device 60. Since it is composed of only transistor chips, it is a multichip type, and if passive elements such as capacitors and resistors are mounted therein, it becomes a hybrid type.

FIG. 24 shows an audio circuit, in which, from left, an Audio Amp 1ch circuit unit, an Audio Amp 2ch circuit unit, and a switching power supply circuit are surrounded by a bold dashed line.

In each circuit section, a circuit surrounded by a solid line is formed as a semiconductor device.

First, in the Audio {Amp} 1ch circuit unit, three types of semiconductor devices and two semiconductor devices integrated with the 2ch circuit unit are prepared.

Here, the semiconductor device 60 is shown in FIG. 6 as an example. As shown in FIG. 60A, a current mirror circuit including TR1 and TR2 and a differential circuit including TR3 and TR4 are integrally configured. This semiconductor device 60 is shown in FIGS. 6B to 6E. Here, four transistor chips each having a size of 0.55 × 0.55 mm and a thickness of 0.24 mm are employed, and are bonded with fine Au wires. The size of the semiconductor device 60 is 2.9 × 2.9 mm and the thickness is 0.5 mm. FIG. 6C illustrates a die pad 61 on which the Z film 36 is formed, a bonding pad 62 on which the Z film 36 is formed, and a wiring 63 for electrically connecting the die pad and the bonding pad. In particular, the wiring 63 is provided very short in the drawing, but may actually be formed long as shown in FIG.

The wiring 63 is a feature of the present invention, and is characterized by using a rolled copper foil as a main material of the wiring. Although depending on the scale of the circuit shown in FIG. 6A, as the planar size of the entire package increases, the length of the wiring arranged therein also increases. Further, due to the difference in thermal expansion coefficient between the insulating resin 35 and the conductive path, each time heat is applied, the wiring is warped. However, as shown in FIG. 2A, the rolled copper foil (XY film) has durability against the repetition of this warpage (flexibility), so that disconnection of the wiring can be suppressed.

Third Embodiment Explaining BGA Type Semiconductor Device First, a semiconductor device 70 will be described with reference to FIG. In the figure, the following components are embedded in an insulating resin 71. That is, the bonding pads 72A, the wiring 72B integral with the bonding pads 72A, and the wiring 72B are integrated with the external connection electrode 72C provided at the other end of the wiring 72B. Further, a radiating electrode 72D provided in one region surrounded by the conductive patterns 72A to 72C and a semiconductor element 73 provided on the radiating electrode 72D are embedded. The semiconductor element 73 is fixed to the heat radiation electrode 72D via the insulating adhesive means AD, and is shown by a dotted line in FIG. 7A. In order to enable bonding, the bonding pad 72A is patterned so as to be located around the semiconductor element 73. The bonding electrode 74 of the semiconductor element 73 and the bonding pad 72A are electrically connected via a thin metal wire W. ing.

The side surfaces of the conductive patterns 72A to 72D are non-anisotropically etched and formed here by wet etching, so that they have a curved structure, and this curved structure generates an anchor effect.

This structure is composed of a semiconductor element 73, a plurality of conductive patterns 72A to 72C, a radiation electrode 72D, a thin metal wire W, an insulating bonding means AD, and an insulating resin 71 for embedding these. In the arrangement region of the semiconductor element 73, the insulating adhesive means AD is formed on the conductive patterns 72B to 72D and in the separating groove 75 therebetween. In particular, the insulating groove 75 is formed in the separating groove 75 formed by etching. An adhesive means AD is provided. Then, the conductive patterns 72A to 72D are sealed with the insulating resin 71 so that the back surfaces thereof are exposed.

As the insulating adhesive means, an adhesive made of an insulating material and an adhesive insulating sheet are preferable. As will be apparent from a later manufacturing method, a material that can be attached to the entire wafer and that can be patterned by photolithography is preferable.

Further, as the insulating resin 71, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, or polyphenylene sulfide can be used. As the insulating resin, any resin can be adopted as long as the resin can be hardened using a mold, or can be coated by dipping or coating.

In addition, as the conductive patterns 72A to 72D, a conductive material mainly made of Cu formed by rolling and a rolled copper foil are preferable in consideration of half-etching property, formability of plating, heat stress, and bending resistance.

According to the present invention, since the insulating resin 71 and the insulating bonding means AD are also filled in the separation groove 75, the conductive pattern can be prevented from coming off. Further, by performing non-anisotropic etching using dry etching or wet etching as the etching, the side surface of the conductive pattern can have a curved structure and an anchor effect can be generated. As a result, a structure in which the conductive patterns 72A to 72D do not fall out of the insulating resin 71 can be realized.

In addition, the back surfaces of the conductive patterns 72A to 72D are exposed on the back surface of the package. Therefore, the back surface of the heat radiation electrode 72D can be fixed to the electrode on the mounting substrate, and with this structure, the heat generated from the semiconductor element 73 can be radiated to the electrode on the mounting substrate and the temperature of the semiconductor element 73 is prevented from rising. As a result, a structure capable of increasing the drive current of the semiconductor element 73 can be realized. As a method for thermally connecting the electrode 72D for heat radiation and the electrode on the mounting board, the electrode 72D may be connected with a brazing material or a conductive paste, or an insulating material having excellent heat conductivity such as silicone may be disposed therebetween. Is also good.

In the present semiconductor device, since the conductive patterns 72A to 72D are supported by the insulating resin 71 which is a sealing resin, a support substrate is not required. This configuration is a feature of the present invention. A conductive path of a conventional semiconductor device is supported by a support substrate (a flexible sheet, a printed circuit board, or a ceramic substrate) or supported by a lead frame, and thus a configuration that may not be necessary is added. However, the circuit device has a feature that it is composed of the minimum necessary components and does not require a support substrate, so that it is thin and lightweight, and it is inexpensive because the material cost can be suppressed.

(4) The conductive patterns 72A to 72D are exposed on the back surface of the package. When this region is covered with a brazing material such as solder, the electrode 72D for heat dissipation has a larger area, and the brazing material is thickly wet. Therefore, in the case where the external connection electrode 72C is fixed on the mounting substrate, the brazing material on the back surface of the external connection electrode 72C may not be wet with the electrode on the mounting substrate, and a connection failure may be caused.

(4) To solve this, an insulating film 76 is formed on the back surface of the semiconductor device 70. The dotted line circles shown in FIG. 7A indicate the external connection electrodes 72C,... Exposed from the insulating film 76, and the electrodes 72D for heat radiation. That is, the portions other than the circles are covered with the insulating coating 76, and the size of the circles is substantially the same size, so that the thickness of the brazing material formed here is substantially the same. This is the same after solder printing and after reflow. The same can be said for conductive pastes such as Ag, Au and Ag-Pd. With this structure, poor electrical connection can also be suppressed. Also, the exposed portion 77 of the heat radiation electrode 72D may be formed larger than the exposed size of the external connection electrode 72C in consideration of the heat radiation of the semiconductor element. Since the external connection electrodes 72C are all substantially the same size, the external connection electrodes 72C are exposed over the entire area, and a part of the rear surface of the heat radiation electrode 72D is substantially the same size as the external connection electrode 72C and is insulated. It may be exposed from the coating 76.

Further, by providing the insulating film 76, the wiring provided on the mounting substrate can be extended to the back surface of the semiconductor device. Generally, the wiring provided on the mounting substrate side is arranged so as to bypass the fixing region of the semiconductor device, but can be arranged without bypassing by forming the insulating film 18. Moreover, since the insulating resin 71 and the insulating bonding means AD protrude from the conductive pattern, a gap can be formed between the wiring on the mounting board side and the conductive pattern, and a short circuit can be prevented.

Fourth Embodiment for Explaining BGA-Type Semiconductor Device 78 First, in FIG. 8, the semiconductor element 73 is mounted face down, the flow prevention film DM is arranged on the conductive pattern, and the insulating bonding means is used. Except that the underfill material AF is used instead of the AD, it is substantially the same, and therefore, this point will be described.

First, the bonding electrode 74 of the semiconductor element 73 and the pad 72A are electrically connected via an electrical connection means SD such as a brazing material such as solder, a conductive paste, or an anisotropic conductive resin.

(4) In order to prevent the flow of the electric connection means SD, the conductive pattern is provided with a flow prevention film DM. For example, taking solder as an example, a flow prevention film DM is formed on at least a part of the conductive patterns 72A to 72C, and the flow of the solder is blocked by this film. The flow prevention film is a film having poor wettability with solder, for example, a polymer film (solder resist) or an oxide film formed on the surface of Ni.

The flow prevention film is provided at least around a region where the solder is arranged, and prevents the flow of a brazing material such as solder, a conductive paste such as an Ag paste, or a conductive resin. It has poor wettability to water. For example, when the solder is provided, when the solder is melted, it is blocked by the flow prevention film DM, and a clean hemispherical solder is formed by the surface tension. Further, since a passivation film is formed around the bonding electrode 74 of the semiconductor element to which the solder is attached, the solder wets only the bonding electrode. Therefore, when the semiconductor element and the pad are connected via the solder, the solder is maintained at a constant height in a shell shape. In addition, since the height can be adjusted by the amount of solder, a certain gap can be provided between the semiconductor element and the conductive pattern, and a cleaning liquid can be penetrated between the gap and a low-viscosity adhesive (here, an underfill material). Can also be infiltrated. Further, by covering the entire area other than the connection area with the flow prevention film DM, it is possible to improve the adhesiveness with the underfill material AF.

This structure is composed of a semiconductor element 73, a plurality of conductive patterns 72A to 72C, a radiation electrode 72D, an underfill material AF, and an insulating resin 71 for embedding them. Further, as described above, in the arrangement region of the semiconductor element 73, the above-mentioned underfill material AF is filled into the conductive patterns 72A to 72D and the separation grooves therebetween. In particular, the underfill material AF is filled in the separation groove 75 formed by etching, and the entire portion including the underfill material AF is sealed with the insulating resin 71. The conductive patterns 72A to 72D and the semiconductor element 73 are supported by the insulating resin 71 and the underfill material AF.

ア ン ダ ー As the underfill material AF, a material that can penetrate into the gap between the semiconductor element and the conductive pattern is preferable, and a filler that functions as a spacer and contributes to heat conduction may be mixed.

According to the present invention, since the insulating resin 71 and the underfill material AF are also filled in the separation groove 75, the conductive pattern can be prevented from coming off by the anchor effect. By performing dry etching or wet etching as a non-anisotropic etching, the side surfaces of the pads 72A can have a curved structure. As a result, a structure in which the conductive patterns 72A to 72D do not fall out of the package can be realized.

In addition, the back surfaces of the conductive patterns 72A to 72D are exposed from the insulating resin 71. In particular, the back surface of the radiation electrode 72D can be fixed to a circuit pattern on a mounting board (not shown). With this structure, the heat generated from the semiconductor element 73 can be radiated to the second circuit pattern on the mounting board, the temperature of the semiconductor element 73 can be prevented from rising, and the driving current of the semiconductor element 73 can be increased accordingly. When the heat radiation property is not considered, the heat radiation electrode 72D may be omitted. At this time, the circuit pattern of the mounting board is omitted.

In the present semiconductor device, the conductive patterns 72A to 72D are supported by the insulating resin 71 as the sealing resin and the underfill material AF, so that a support substrate is not required. This configuration is a feature of the present invention. As described in the section of the related art, the copper foil pattern of the conventional semiconductor device is not required because it is supported by a support substrate (a flexible sheet, a printed board or a ceramic substrate) or supported by a lead frame. Even so, a good configuration is added. However, this circuit device has a feature that it is composed of a minimum number of necessary components and does not require a supporting substrate, so that it is thin and lightweight, and it is inexpensive because it does not require material cost.

Further, the present semiconductor device has an external connection electrode 72C, a first heat radiation path via a brazing material, an electrode 72D for heat radiation, and a second heat radiation path via a brazing material, and thereby the driving capability of the semiconductor element is improved. It can be improved further.

Further, the back surface of the semiconductor element 73 may be exposed from the insulating resin film 71. By exposing, the thermal coupling between the heat radiating means and the semiconductor element 73 can be further improved. However, if it is difficult to electrically couple the heat radiating means to the semiconductor element 73, an insulating material such as a silicone resin is provided between them. This silicone resin is resistant to heat and has excellent heat conduction due to inclusion of a filler, and thus has been frequently used.


Fifth Embodiment for Explaining BGA Type Semiconductor Device 79 In FIG. 8, the wiring 72B and the external connection electrode 72C are formed integrally with the pad 72A, but here, as shown in FIG. Is formed as an external connection electrode.

(4) Since the bonding pad 72A is rectangular, the pattern of the electrode 72D for heat radiation exposed from the insulating film 76 is also formed in the same pattern. Further, in consideration of the fixability of the insulating adhesive means AD, the groove 80 is formed so that the heat radiation electrode 72D is divided into a plurality. The symbol W is a thin metal wire.

Further, the semiconductor element 73 may be mounted face down. In this case, as shown in FIG. 8, an underfill material is employed. In this embodiment, since the wiring and the external connection electrode are not provided, the heat radiation electrode 72D can be enlarged, and the heat radiation of the semiconductor element is improved.

Sixth Embodiment Explaining Multi-Chip Semiconductor Device 81 A semiconductor device 81 on which a plurality of semiconductor chips 72A and 72B are mounted by utilizing the mounting method of FIG. 9 will be described with reference to FIG.

In the present embodiment, the bridge 83 is employed to electrically connect the first semiconductor chip 73A and the second semiconductor chip 73B. When the bridge 83 is formed by a lead frame, it is formed in an island shape, and therefore needs to be supported by a suspension lead or an adhesive tape. However, as will be understood from a later manufacturing method, since the conductive paths are separated after the conductive foil is half-etched and resin-molded, there is an advantage that these supporting members are not required. In addition, since the thin metal wires W connected to both the semiconductor chips 82A and 82B are connected by ball bonding and are stitch-bonded on the bridge 83 side, there is a feature that the impact of stitch-bonding is not applied to the chips.

{Circle around (5)} As shown in FIG. 7, wiring and external connection electrodes may be integrally provided on the bonding pad 72. In this case, it is preferable that the size of the first die pad 82A and the size of the second die pad 82B be smaller than the size of the semiconductor chip, and that the wiring and the extension region of the external connection electrode be enlarged. The semiconductor chip 73 and the die pad 82 are electrically connected by a brazing material such as solder. However, when the wiring and the external connection electrode extend below the semiconductor chip, it is better to provide the insulating adhesive means AD in consideration of prevention of short circuit.

On the other hand, the semiconductor chip 73 may be mounted face down. This is shown in FIG. 10C. This structure is substantially the same as FIG. Since the semiconductor chip and the pad are connected by a brazing material such as solder, an underfill material AF or the like penetrates into this gap.

Seventh Embodiment for Explaining Features and Manufacturing Method of Semiconductor Device A feature shown in FIGS. 12 to 13 is that a projecting portion 91 made of an insulating resin 90 is formed, and a conductive path 92 is larger than the projecting portion 91. It is to enter inside and form a recess 93 therein. As a result, it is possible to increase the connection strength of the solder 94, prevent short circuit between the solder or the conductive paths 92, and reduce the friction coefficient of the back surface of the semiconductor device.

In, the manufacturing method will be described with reference to FIGS.

First, as shown in FIG. 14, a sheet-shaped conductive foil 100 is prepared. The material of the conductive foil 100 is selected in consideration of the adhesiveness, bonding property, and plating property of the brazing material, and a rolled conductive foil containing Cu as a main material is used as the material. In addition, impurities are diffused to add rigidity to the conductive foil so that handling in each step is facilitated. FIG. 2B shows an example of this impurity.

と The thickness of the conductive foil is preferably about 35 μm to 300 μm in consideration of the later etching, and here, a copper foil of 70 μm (2 oz) was employed. However, it is basically good to be 300 μm or more and 35 μm or less. As will be described later, it is sufficient that the separation groove 101 shallower than the thickness of the conductive foil 100 can be formed. Also, considering the transfer mold after, the mold of the transfer mold generally used in the post-process, and the standard conductive foil used for this, the size of the conductive foil is about 220 mm in length, ~ 75 mm in width, It is better to have a thickness of about 300 mm and cut into strips. If this size is adopted, a commercially available transfer molding apparatus, a metal mold, and a conductive foil can be adopted, and the cost can be reduced.

In addition, the sheet-shaped conductive foil 100 may be prepared by being wound in a roll shape with a predetermined width, and may be transported to each step described later. (See FIG. 14 above)
Subsequently, there is a step of removing the conductive foil 100 excluding at least a region to be the conductive path 102 so as to be thinner than the thickness of the conductive foil 100.

{Circle around (1)} First, a photoresist (etching resistant mask) PR is formed on the Cu foil 100, and the photoresist PR is patterned so as to expose the conductive foil 100 excluding the region serving as the conductive path 102 (see FIG. 15).

(4) Then, as shown in FIG. 16, etching may be performed via the photoresist PR.

(4) The depth of the separation groove 101 formed by etching is, for example, 50 μm, and the side surface thereof is roughened by etching or roughening, so that the adhesiveness to the insulating resin 103 is improved.

(4) The side walls of the separation groove 101 have different structures depending on the removal method. This removal step can employ wet etching, dry etching, laser evaporation, and dicing. Also, it may be formed by pressing. In the case of wet etching, ferric chloride or cupric chloride is mainly used as an etchant, and the conductive foil is dipped in the etchant or showered with the etchant. Here, since the wet etching is generally performed non-anisotropically, the side surface has a curved structure as shown in FIGS. 16B and 16C. For example, in FIG. 16B, if a mask having good adhesion is selected as the etching resistant mask or if Ni or the like is adopted, an eave is formed. In this case, the conductive path itself constitutes an eave, or the eave is formed together with a conductive film formed on the conductive path. Further, depending on the method of forming the etching resistant mask, a semicircle may be drawn as shown in FIG. 16C. In any case, since the curved structure 104 is formed, an anchor effect can be generated.

In the case of dry etching, anisotropic and non-anisotropic etching is possible. At present, it is said that it is impossible to remove Cu by reactive ion etching, but it can be removed by sputtering. In addition, anisotropic and non-anisotropic etching can be performed depending on sputtering conditions.

In the case of a laser, a separation groove can be formed by directly irradiating a laser beam. In this case, the side surface of the separation groove 101 is formed straight.

Also, in dicing, it is impossible to form a bent complicated pattern, but it is possible to form a lattice-shaped separation groove.

In FIG. 16, a conductive film having corrosion resistance to an etchant may be selectively coated instead of the photoresist PR. When the conductive film is selectively applied to a portion to be a conductive path, the conductive film serves as an etching protective film, and the isolation groove can be etched without using a resist. Materials that can be considered as the conductive film include Ni, Ag, Au, Pt, and Pd. Moreover, these corrosion-resistant conductive films have a feature that they can be used as they are as die pads and bonding pads.

For example, the Ag film adheres to Au and also adheres to the brazing material. Therefore, if the Au film is coated on the back surface of the chip, the chip can be thermocompression-bonded to the Ag film on the conductive path 51 as it is, and the chip can be fixed via a brazing material such as solder. Since the Au thin wire can be bonded to the Ag conductive film, wire bonding is also possible. Therefore, there is an advantage that these conductive films can be used as die pads and bonding pads as they are. (See FIG. 16 above)
Subsequently, as shown in FIG. 17, there is a step of electrically connecting and mounting the circuit element 105 to the conductive foil 100 in which the separation groove 101 is formed.

As described with reference to FIGS. 1 to 13, the circuit element 105 is a semiconductor element 105A such as a transistor, a diode, or an IC chip, and a passive element 105B such as a chip capacitor or a chip resistor. Although the thickness is increased, a face-down type semiconductor element such as a CSP represented by a wafer scale CSP or a BGA can also be mounted.

Here, the transistor chip 105A as a bare semiconductor chip is die-bonded to the conductive path 102A, and the emitter electrode and the conductive path 105B, and the base electrode and the conductive path 105B are fixed by ball bonding by thermocompression bonding or wet bonding by ultrasonic waves. Are connected via the thin metal wire 106. Reference numeral 105B denotes a passive element and / or an active element such as a chip capacitor. Here, a chip capacitor is employed, and is fixed with a brazing material such as solder or a conductive paste 107. (See FIG. 17 above)
Further, as shown in FIG. 18, there is a step of attaching an insulating resin 103 to the conductive foil 100 and the separation groove 101. This can be achieved by transfer molding, injection molding, or dipping. As the resin material, a thermosetting resin such as an epoxy resin can be realized by transfer molding, and a thermoplastic resin such as a polyimide resin and polyphenylene sulfide can be realized by injection molding.

In the present embodiment, the thickness of the insulating resin coated on the surface of the conductive foil 100 is adjusted so as to cover about 100 μm from the top of the circuit element. This thickness can be increased or reduced in consideration of strength.

特 徴 The feature of this step is that the conductive foil 100 serving as the conductive path 102 becomes a support substrate until the insulating resin 103 is covered. For example, in a CSP employing a printed board or a flexible sheet, a conductive path is formed by employing a supporting substrate (printed board or flexible sheet) which is not originally required. Is a material necessary for the conductive path. Therefore, there is a merit that the operation can be performed while omitting the constituent materials as much as possible, and the cost can be reduced.

Since the separation groove 101 is formed to be shallower than the thickness of the conductive foil, the conductive foil 100 is not individually separated as the conductive path 102. Therefore, it is possible to handle from the mounting of the circuit element to the dicing, and particularly when the insulating resin is molded, it has a feature that the work of transporting to the die and mounting on the die becomes very easy. Further, as described above, since impurities are added, rigidity is added to the conductive foil, and workability is further improved.

Next, there is a step of chemically and / or physically removing the back surface of the conductive foil 100 and separating it as the conductive path 102. Here, this removing step is performed by polishing, grinding, etching, laser metal evaporation, or the like.

半導体 A semiconductor device formed by this separation method is shown in FIGS. 21A to 21C.

{Circle around (1)} First, in FIG. 21A, the back surface is finally polished so that the back surface of the conductive path 102 and the back surface of the separation groove 101 are aligned.

Next, FIG. 21B shows that etching is performed at least before the separation groove 101 is exposed. Generally, the conductive path 102 is recessed from the back surface of the separation groove 102 due to over-etching to completely separate the conductive path 102.

FIG. 21C shows a state in which an etching resistant mask is formed on the rear surface of the conductive foil 100 at a portion to be an external connection electrode at the stage of FIG. 18, and etching is performed through the mask. Thereby, a part of the conductive path 102 is formed to protrude from the back surface of the separation groove 101.

The exposed surfaces shown in FIGS. 21A and 21B are indicated by dotted lines in FIG.

FIG. 19 shows an example of a semiconductor device in which the conductive path 102 is separated. In addition, they are separated by wet etching.

Further, an insulating film 108 is formed on the back surface of the semiconductor device to prevent a short circuit with the wiring on the mounting board. Reference numeral 109 denotes a brazing material such as solder. Since the insulating coating 108 does not wet the brazing material, a clean hemispherical brazing material is formed.
As a result, the conductive paths 102 having a thickness of about 40 μm are separated. (See FIG. 20 above)
Note that a conductive film of Au or Ag may be applied to the back surface of the conductive path 102. The conductive film may be formed on the back surface of the conductive foil in FIGS. 14 to 17 in advance. The deposition method is, for example, plating. The conductive film is preferably made of a material having resistance to etching.

In the present manufacturing method, only the semiconductor chip and the chip capacitor are mounted on the conductive foil 100, but they may be arranged in a matrix as a unit. In this case, dicing is performed to separate each unit.

判 As can be seen from the above manufacturing methods, various semiconductor devices can be manufactured by this manufacturing method. A discrete type or BGA type mounting one transistor, diode, IC or LSI as an active element (semiconductor chip), a multi-chip type mounting a plurality of the active elements, and a transistor as an active element (semiconductor chip) Various semiconductor devices such as a diode, an IC or an LSI, a hybrid IC type configured by mounting a chip resistor and a chip capacitor as passive elements, and also forming a wiring as a conductive path to realize a desired circuit can be developed. .

According to the above manufacturing method, a semiconductor device in which the conductive path is embedded in the insulating resin and the back surface of the conductive path 51 is exposed on the back surface of the insulating resin can be realized.

This manufacturing method has a feature that the conductive path can be separated using the insulating resin as the supporting substrate. The insulating resin is a necessary material for embedding the conductive path, and does not require an unnecessary supporting substrate. Therefore, it is characterized by being able to be manufactured with a minimum of materials and realizing cost reduction.

As can be seen from the above manufacturing method, the recess 93 can be formed on the back surface of the conductive path as shown in FIG. 12A by the conductive path separating method. Moreover, the package in which the curve on the side of the conductive path and the curve on the side of the separation groove match is obtained. In addition, since the bottom of the separation groove is formed by non-anisotropic etching, a curved surface is drawn, and an empty region 93A indicated by a triangle is formed.

Due to the curved surface of the separation groove, even if melted solder is provided in the separation groove portion, the separation groove has a slope and the solder flows as shown by the arrow due to the surface tension of the solder, and the island-shaped hemisphere is completely separated. It becomes possible to form solder. In addition, since the empty area 93A is provided, a relief area for the solder is formed, and the phenomenon in which the melted solder is united next to each other and short-circuited can be suppressed.

FIG. 12B shows a configuration in which the protrusion of the separation groove is partially flattened. In the case of etching, the depth of the separation groove may vary depending on the distance between the conductive paths, and the height of the protrusion 91 may vary. In this case, it can be assumed that the semiconductor device cannot be arranged horizontally. In this case, after separating the conductive paths, the back surface of the semiconductor device is polished, and the heights of the protrusions are all uniform. The portion indicated by FL is the flat portion.

FIG. 13 shows a structure in which a semiconductor device is mounted on a mounting substrate 520. Since the circuit pattern 521 formed on the conductive path of the mounting board is coupled to the conductive path 522 connected to the semiconductor chip, it has an advantage that heat of the semiconductor chip can be released to the circuit pattern.

The symbol H shown in FIG. 12 indicates how much the top of the protrusion 91 protrudes from the back surface of the conductive path. Here, H is about 20 μm. The brazing material solidified on the back surface of the conductive path must be formed higher than the protruding portion 91 in a solidified state. However, at the time of melting, the solder 94 is crushed by its own weight and external force, and the protrusion 91 serves as a stopper, and the protrusion contacts the mounting board 520 as shown in FIG. However, since the projecting portion 91 is curved, the coefficient of friction of the back surface of the semiconductor device is also small, which facilitates movement of the semiconductor device and also facilitates self-alignment.

FIG. 22 illustrates how the size is reduced by employing the semiconductor device of the present invention. The photographs shown at the same magnification show, from the left, a single SMD employing a lead frame, a composite SMD employing a lead frame, and a semiconductor device of the present invention. The single SMD is molded with one TR, and the composite TR is molded with two TRs. The semiconductor device of the present invention is a semiconductor device on which the circuit shown in FIG. 6 is mounted, and four TRs are sealed. As is clear from the figure, the size of the present semiconductor device is only slightly larger than that of the composite SMD including the lead frame, although twice the element of the composite SMD is sealed. A semiconductor device in which one TR is sealed is shown on the rightmost side. As can be seen from the above, a small and thin semiconductor device can be realized by the present invention, which is most suitable for portable electronic equipment.

Finally, FIG. 23 shows a mounting board on which the semiconductor device is mounted. The circuit pattern is formed again and mounted on the conventional mounting board shown in FIG. As is clear from FIG. 23, the circuit pattern of the mounting board is simplified and the interval can be formed widely. As a result, the circuit pattern of the mounting board can be formed more densely, and the mounting board can be reduced in size. Further, the number of die bonding and the number of wire bonding of the semiconductor chip are reduced, and the number of assembling steps on the mounting board is greatly reduced. On the mounting board, some kinds of fine metal wires are used. For example, in FIG. 25, it is assumed that a 40 μm Au wire or Al wire used for a small signal system and 150 μm and 300 μm Al wires used for a large signal system are used. If all of the semiconductor elements connected to at least one of the three types of thin metal wires have this structure, the bonding of the thin metal wires becomes unnecessary. For example, an Au wire and an Al wire are connected by different bonders because the bonder mechanism is completely different. However, if all the semiconductor elements connected by the Au wire are packaged in this structure, and the portion jumped by the Au wire is replaced by the Al wire, no Au wire bonder is required in assembling the mounting board. This greatly leads to simplification of the assembly process.

で は In the case of a conventional lead frame package, hanging leads, tie bars, etc., which are cut on the side of the package, are always exposed. Therefore, the package and the package cannot be arranged in contact with each other in consideration of the contact with the exposed portion. However, according to the present invention, the entire surface except for the back surface is covered with the insulating resin, so that the semiconductor device can be brought into contact with the semiconductor device and arranged on the mounting board.

Furthermore, on the back surface of the semiconductor device, a protrusion made of insulating resin has a curved surface, and this back surface has a very small coefficient of friction. In addition, the semiconductor device itself is thin and lightweight, so that the semiconductor device is naturally self-aligned during soldering.

If a metal substrate is adopted as the mounting substrate, the heat of the semiconductor device can be released through the metal substrate, and the temperature rise of the module as a whole mounting substrate can be suppressed.

FIG. 3 is a diagram illustrating an XY film used in the semiconductor device of the present invention. FIG. 2 is a diagram illustrating characteristics of the XY film in FIG. 1. FIG. 3 is a diagram illustrating an XY film used in the semiconductor device of the present invention. FIG. 3 is a diagram illustrating a surface structure of an XY film. FIG. 3 illustrates a semiconductor device of the present invention. FIG. 3 illustrates a semiconductor device of the present invention. FIG. 3 illustrates a semiconductor device of the present invention. FIG. 3 illustrates a semiconductor device of the present invention. FIG. 3 illustrates a semiconductor device of the present invention. FIG. 3 illustrates a semiconductor device of the present invention. FIG. 3 is a diagram illustrating a conductive pattern used in the semiconductor device of the present invention. FIG. 3 illustrates a semiconductor device of the present invention. FIG. 3 is a diagram illustrating a mounting board on which the semiconductor device of the present invention is mounted. FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention. FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention. FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention. FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention. FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention. FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention. FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention. FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention. FIG. 3 is a diagram illustrating the size of the semiconductor device of the present invention. FIG. 3 is a diagram illustrating a hybrid integrated circuit board on which the semiconductor device of the present invention is mounted. FIG. 3 is a diagram illustrating an example of a circuit employed in the semiconductor device of the present invention. FIG. 25 is a diagram illustrating a conventional hybrid integrated circuit substrate using the circuit of FIG. 24. FIG. 9 illustrates a conventional semiconductor device.

Explanation of reference numerals

40, 46 Conductive path 41, 47 Crystal grain boundary 42 Fine metal wire 43 Semiconductor chip 44 Insulating resin 45, 48 Crystal grain 50 Wiring 51 Die pad or bonding pad 52 Curved structure 53 Eaves

Claims (14)

A plurality of conductive patterns,
A conductive coating formed on the upper surface of the conductive pattern,
A semiconductor element electrically connected via at least one of the conductive patterns and the conductive film;
Comprising a sealing resin for sealing the semiconductor element and the conductive pattern,
The semiconductor device according to claim 1, wherein the conductive film exposes a periphery of the conductive pattern provided in a lower layer. 2. The semiconductor device according to claim 1, wherein an upper surface of the conductive pattern and a side surface of the conductive pattern excluding a region where the conductive film is formed contact the sealing resin. The semiconductor element is placed face-up on the conductive pattern,
2. The semiconductor device according to claim 1, wherein an upper surface of the conductive pattern in a region where the semiconductor element is mounted is covered with the conductive film. The semiconductor element is electrically connected to the conductive pattern via a thin metal wire,
2. The semiconductor device according to claim 1, wherein an upper surface of the conductive pattern in a region to which the thin metal wire connects is covered with the conductive film. The semiconductor device according to claim 1, wherein the conductive film is a plating film. 2. The semiconductor device according to claim 1, wherein a side surface of the conductive pattern forms a curved surface depressed inward. 4. The semiconductor device according to claim 1, wherein the conductive pattern is embedded in the sealing resin with a back surface exposed. A conductive pattern forming a bonding pad and a die pad;
A conductive coating formed on the upper surface of the conductive pattern,
A semiconductor element electrically connected to the conductive pattern;
Comprising a sealing resin that covers the conductive pattern and the semiconductor element,
The bonding pads, the die pads, or the bonding pad and the die pad are connected via a wiring portion extending with a narrow width from the conductive pattern,
A semiconductor device, wherein an upper surface and a side surface of the wiring portion are in contact with the sealing resin. 9. The semiconductor device according to claim 8, wherein an upper surface of the conductive pattern excluding a region where the conductive film is formed and a side surface of the conductive pattern are in contact with the sealing resin. The semiconductor element is placed face-up on the conductive pattern,
9. The semiconductor device according to claim 8, wherein an upper surface of the conductive pattern in a region where the semiconductor element is mounted is covered with the conductive film. The semiconductor element is electrically connected to the conductive pattern via a thin metal wire,
9. The semiconductor device according to claim 8, wherein an upper surface of the conductive pattern in a region where the thin metal wire connects is covered with the conductive film. 9. The semiconductor device according to claim 8, wherein the conductive film is a plating film. 9. The semiconductor device according to claim 8, wherein a side surface of the conductive pattern forms a curved surface depressed inward. 9. The semiconductor device according to claim 8, wherein the conductive pattern is embedded in the sealing resin with a back surface exposed.

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