JP2004006898A - Method and apparatus for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent fluctuation of threshold voltage and deterioration of current driving capability by preventing out-diffusion during heat treatment. <P>SOLUTION: A MOS transistor having an LDD structure is manufactured by forming well regions 102, 103 in superficial regions of a P-type silicon substrate 101. A gate oxide film 105 and an N<SP>+</SP>-type polycrystalline silicon film 106, 107, are sequentially formed on the substrate 101. The polycrystalline silicon film 106, 107 is doped with phosphorus atoms at a concentration of about 3x10<SP>20</SP>/cm<SP>3</SP>. The silicon-substrate 101 surfaces of the LDD regions 110 are formed by the phosphorus implantation, later become source/drain regions, and are exposed to the atmosphere. A sidewall is formed on the gate. To strengthen adhesion of the sidewall and to activate the implanted phosphorus ions 109, annealing and oxide-film formation are conducted. In an initial stage of the heat treatment, the treatment is carried out with nitrogen gas containing 1-5 vol.% oxygen. <P>COPYRIGHT: (C)2004,JPO

Description

【００６６】
表１は図１２（ａ）のインジェクタ１７６方向を用いて目標比抵抗を１８Ω／□、２７Ω／□、７００Ω／□としたときの均一性を測定した結果である。本実施例の不純物拡散装置を用いて、シリコン基板１７０面内と、シリコン基板１７０間の均一性について測定した。シリコン基板処理枚数は基板ボート１７１に充填したシリコン基板１７０の枚数を示す。この結果、従来の構造の拡散炉ではガスの流れを一定にするため、装置の処理可能枚数以下の枚数を処理する場合、目的とするシリコン基板１７０以外にダミーのシリコン基板を基板ボート１７１に積載し、比抵抗を均一にしていたが、本実施例のごとくインジェクタ１７６を用いれば、ダミーのシリコン基板を用いる必要がなく、基板ボート１７１に充填するシリコン基板１７０の枚数が２５枚〜１００枚のいずれであっても十分な均一性を得ることができる。
【００６７】
本発明のごとき互いに９０度異なった方向にガス噴出口をもつ２重同軸型のインジェクタを気相での不純物拡散に用いることにより、同時に大量の半導体シリコン基板に対し、シリコン基板面内およびシリコン基板間の均一性よく不純物拡散を行なうことができる。
【００６８】
上記実施例では縦型拡散炉を用いて酸化・アニールする場合のプロセスシーケンスやその構造について述べた。次に、横型拡散炉を用いてパイロジェニック酸化によって酸化膜を形成する際の実施例についてのべる。横型拡散炉による、酸素リッチな雰囲気でのパイロジェニック酸化は、インジェクタ先端部において正常な燃焼状態にはならない。過剰酸素により燃焼は爆発的なものとなり水酸素炎の温度は非常に高温になる。通常インジェクタ先端部の口径は絞ってあるためインジェクタ先端部から噴出する水素および酸素の混合ガスの噴出速度は非常に高速になる。通常インジェクタは溶融石英で構成されているので、爆発的燃焼による流速の速い高温燃焼ガスによってインジェクタ先端部の石英が溶融する。溶融した石英は高速の燃焼ガスとともに放出され、微粉末となって燃焼ガスとともに、プロセスチューブ内に導入される。このようにして形成された微粉末がデバイスを形成する際にシリコン基板に付着すると、この石英粉末を核として多結晶シリコン膜が異常成長したり、エッチング時の均一性を低下させる。また、フォトリソグラフィーによるパターン形成時においても表面の反射率が変化し、正常なパターン形成が阻害される。
【００６９】
以下に本発明の横型拡散炉の実施例について図面を用いて説明する。図１３は本発明の横型拡散炉の構成図である。実施例ではシリコン基板上に膜厚２０ｎｍのシリコン酸化膜を、水素ガス流量：酸素ガス流量＝５：１５（リットル／毎分）で、成長温度９００℃のパイロジェニック酸化する場合について述べる。
【００７０】
図において、プロセスチューブ２０１には、ボート２０２に設置されたシリコン基板２０３が導入されている。ボート２０２はカンチレバー２０４上に配置されている。プロセスチューブ２０１へ導入されるガス導入口２０５とボート２０２との間にガスバッフル２０６が設置されている。ガス導入口２０５には外部燃焼チャンバ２０７が取り付けられている。外部燃焼チャンバ２０７には外部燃焼用ヒーター２０８と、インジェクタ２０９が取り付けられている。インジェクタ２０９には酸素ガスを供給する酸素ポート２１０と、水素ガスと窒素ガスを供給する水素・窒素ポート２１１を備えている。プロセスチューブ２０１には外部燃焼チャンバー２０７からつながるガス導入口２０５と、酸素ガスを供給するもう１本のガス導入口２１２とを備えている。ガス導入口２１２には酸素ポート２１３につながっている。水素・窒素ポート２１１、酸素ポート２１０と酸素ポート２１３の各々に、それぞれ水素マスフローコントローラ２１４、酸素マスフローコントローラ２１５と酸素マスフローコントローラ２１６が接続されている。酸素マスフローコントローラ２１６は水素／酸素混合比演算部２１７によって制御されている。また酸素マスフローコントローラ２１５と水素マスフローコントローラ２１４は酸素減量演算部２１８によって制御されている。
【００７１】
ここで水素ガスおよび酸素ガスの流量をそれぞれ毎分５リットルおよび毎分１５リットルを入力部に入力すると、水素ガスと酸素ガスとによる爆発を防止するための流量比の確認が行われる。本実施例の場合、水素ガス：酸素ガス流量比は３：１である。両者のガスによって爆発する上限の水素ガス：酸素ガスの流量比＝１．８：１以下であり、実施例の場合問題はない。ここで水素ガスの流量は毎分５リットルがそのまま採用され、一方酸素ガスの流量は外部燃焼を行う際に水素ガス流量：酸素ガス流量比＝１．８：１を実現するために、水素ガス流量の０．５６倍、すなわち毎分２．７８リットルの計算が酸素流量演算部２１８で行われる。
【００７２】
一方、これらの燃焼により生じた水蒸気に混合される酸素ガス量は水素／酸素混合比演算部２１７で計算される。本実施例の場合、目標の酸素ガス流量は毎分１５リットルであるので水蒸気に混合させる酸素ガス量は毎分１２．２２リットルとなる。おのおのこれらの水素ガス流量と酸素ガス流量に従ってマスフローコントローラ２１４，２１５，２１６が制御される。水素マスフローコントローラ２１４と酸素マスフローコントローラ２１５，２１６によりその流量が決定された水素および酸素はそれぞれ、水素・窒素ポート２１１および酸素ポート２１０から外部燃焼装置に導入される。この混合ガスは外部燃焼用ヒーター２０８によりインジェクタ２０９内で８００℃に加熱され、インジェクタ２０９先端で燃焼する。本実施例において使用したインジェクタ２０９を図１４に示す。
【００７３】
インジェクタ２０９はインジェクタ先端部２２０、酸素ガス放出端２２１、酸素ポート２２２、水素ポート２２３、オーリングシール２２５と燃焼チャンバ２２６とで構成されている。インジェクタ先端部２２０には水酸素炎２２７が動作時に生成される。インジェクタ２０９は同軸構造を持っており、酸素ガスは酸素ポート２２２から導入され同軸管の外管から外部燃焼チャンバ２２１内に放出される。一方、水素ガスは水素ポート２２３から同軸管の内管を通りインジェクタ先端部２２０へ導入される。水素ガスと酸素ガスはともにインジェクタ２０９内部を通過中に外部燃焼ヒーターにより十分加熱される。本実施例ではインジェクタ先端部２２０の噴き出し口は１個口とし、開口部の内径は３ｍｍとしている。水素ガス流量が毎分５リットル時、燃焼ガスの噴出速度は毎分１１．８ｍとなる。さらにインジェクタ先端部２２０の肉厚を３ｍｍと十分厚くすることによりインジェクタ先端部２２０の熱容量を大きくしている。これによって、著しくインジェクタ先端部２２０の温度が上昇しないように設計されている。もちろん噴出速度を退化させるにはさらに噴き出し口の内径を大きくし、熱容量をさらに大きくするためにインジェクタ先端部２２０の肉厚を厚くすればよい。本実施例ではインジェクタ材料として純度の高い、高純度溶融石英を用いたが、水酸基（ＯＨ）含有量および不純物含有量の低い合成石英を用いてもよい。また、いずれにせよインジェクタ先端部２２０で燃焼が生ずるため長期にわたって使用した場合には、インジェクタ２０９は徐々に磨耗する。そのため、インジェクタ材料として高温耐性および不純物含有量の少なく、表面にＣＶＤによって堆積した炭化珪素被膜を膜厚１００μｍで形成しておけば、半永久的に使用できるインジェクタ２０９が得られる。なお、噴出口の内径および肉厚は単純に大きくすればよいというものではなく、水酸素炎２２７の長さなどを考慮しなければならない。水酸素炎の長さはインジェクタ先端部２２０からその前方にある物体までの距離で決まり、通常１５〜２０ｃｍ程度である。
【００７４】
このようにしてインジェクタ先端部２２０で水素毎分５リットルと酸素毎分２．７８リットルとで燃焼させると水蒸気が発生する。この水蒸気は外部燃焼チャンバ２２６を通りプロセスチューブ２０１に導入される。なお、本実施例の方法によればインジェクタ先端部２２０の溶融は発生しないため、従来のように溶融した石英粉末がプロセスチューブ内に導入されることはない。
【００７５】
さて、一方、目標の水素ガスと酸素ガスとの混合比を実現するためにマスフローコントローラ２１６により供給される酸素ガスを毎分１２．２２リットルがプロセスチューブ２０１に設置された酸素ポート２１３から導入さる。このようにして、プロセスチューブ２０１内で水蒸気とこの酸素ガスとが混合され目標の水素ガスと酸素ガスとの混合比率が達成される。これらの混合ガスはガスバッフル２０６により乱流になった後シリコン基板２０３へと搬送される。
【００７６】
以上のプロセスにより、シリコン基板上に非常に清浄なゲート酸化膜であるシリコン酸化膜が形成される。このゲート酸化膜上には従来方法で示すような溶融石英の粉末は存在しない。したがって、後の工程で多結晶シリコン膜にオキシ塩化リンにより燐原子をドーピングする際の燐拡散を熱拡散で行った場合でも、多結晶シリコン膜が異常成長することがない。また、本実施例では続いて公知のフォトリソグラフィー技術においても表面ラフネスによるハレーションの問題や、ドライエッチングにおけるエッチング残りの問題などは発生しない。
【００７７】
本実施例ではゲート酸化、多結晶シリコン堆積についての実施例を述べているが、ＣＶＤによる膜の堆積前の堆積膜の密着性強化のための酸化膜形成などにおいても同様の効果が期待できることはいうまでもない。またシリコン基板の酸化ではなく下地がシリコン基板上のシリコン酸化膜であっても、シリコン窒化膜であっても、さらにパターンがあっても本発明の効果に差はない。ただし、溶融石英粉末自体の付着はパターン依存性や下地材料依存性があり、そのときの粒径についても依存性がある。
【００７８】
以上のように本発明によるシリコン酸化膜の形成方法および形成装置によりシリコン酸化膜を形成もしくはパイロジェニック酸化を行った場合水素、酸素の混合比にかかわらず、石英インジェクタの先端部の溶融を著しく抑制することができ、石英インジェクタの寿命を飛躍的に延命化できるとともに、溶融したインジェクタ先端部の石英が微粉末となって、シリコンシリコン基板に付着するのを防止することができ、低パーティクルおよび酸化に続いてのＣＶＤ膜堆積時における異常成長を防止することができ、加工性の低下およびデバイス性能および信頼性を低下させる事なくプロセスを行うことができる。
【００７９】
【発明の効果】
本発明の如き、高濃度不純物層もしくは高濃度不純物を含む多結晶シリコン膜をシリコン基板の表面および裏面の一部または全部に有する半導体装置に熱処理を行なう場合の外方拡散を防止でき、ＬＤＤおよびＤＤＤ構造のＭＯＳトランジスタのしきい値電圧の変動や電流駆動能力の低下を防止することができる。
【００８０】
また、本発明の半導体製造装置では、同時に大量の半導体シリコン基板に対し、シリコン基板面内およびシリコン基板間の均一性よく不純物拡散を行なうことができる。
【００８１】
さらに、パイロジェニック酸化を行った場合に石英インジェクタの先端部の溶融を著しく抑制することができ、石英インジェクタの寿命を飛躍的に延命化できる。
【図面の簡単な説明】
【図１】本発明のＬＤＤ構造の半導体装置の製造方法の工程断面図
【図２】本発明の半導体装置の製造方法の熱処理シーケンスを示す図
【図３】本発明のＤＤＤ構造の半導体装置の製造方法の工程断面図
【図４】本発明の半導体装置の製造方法の熱処理シーケンスを示す図
【図５】本発明の容量素子である半導体装置の製造方法の工程断面図
【図６】本発明の半導体装置の製造方法の熱処理シーケンスを示す図
【図７】本発明の半導体製造装置を示す図
【図８】本発明の半導体製造装置である縦型拡散炉を示す図
【図９】本発明の半導体製造装置のインジェクタを示す図
【図１０】本発明の半導体製造装置のインジェクタの長手方向の断面図
【図１１】本発明の半導体製造装置のインジェクタの断面図
【図１２】本発明の半導体製造装置によって形成されたシリコン基板上の比抵抗分布を示す図
【図１３】本発明の半導体製造装置の構成を示す図
【図１４】本発明の半導体製造装置のインジェクタを示す図
【図１５】従来の容量素子である半導体装置の製造方法の工程断面図
【図１６】従来のＬＤＤ構造の半導体装置の製造方法の工程断面図
【図１７】従来のＤＤＤ構造の半導体装置の製造方法の工程断面図
【図１８】従来の半導体製造装置を示す図
【図１９】従来の半導体製造装置によって形成されたシリコン基板上の比抵抗分布を示す図
【図２０】従来のの半導体製造装置を示す図
【図２１】従来の半導体製造装置によって形成されたシリコン基板上の比抵抗分布を示す図
【図２２】従来の半導体製造装置によって形成されたシリコン基板上の比抵抗分布を示す図
【図２３】従来の半導体製造装置の構成を示す図
【符号の説明】
１０１　シリコン基板
１０２，１０３　ウェル領域
１０４　分離領域
１０５　ゲート酸化膜
１０６，１０７　多結晶シリコン膜
１０８　フォトレジスト
１０９　リンイオン
１１０　ＬＤＤ領域
１１３　チャネル領域
１１４，１１５　ソース／ドレイン領域
１１６　側壁
１１７　酸化膜[0001]
[Industrial applications]
The present invention relates to a semiconductor device, and more particularly to a semiconductor device manufacturing method and a semiconductor manufacturing apparatus in an oxide film forming method including a gate oxide film in a MOS device.
[0002]
[Prior art]
2. Description of the Related Art A semiconductor device, particularly a MOS device, includes many steps of forming an oxide film including formation of a gate oxide film. In recent years, with the miniaturization and high integration of elements, the number of steps of using a polycrystalline silicon film in multiple layers has increased. For example, in a 1-Mbit dynamic RAM, a cell plate constituting a cell capacity is usually formed of a polycrystalline silicon film containing conductive impurities at a high concentration. Thereafter, the gate electrodes of the select transistor and the peripheral transistor are formed of a polycrystalline silicon film containing conductive impurities at a high concentration. As described above, in recent LSI elements, a polycrystalline silicon film containing conductive impurities at a high concentration has become indispensable as a wiring material and an electrode material of a MOS transistor. That is, such a polycrystalline silicon film is formed using CVD. Therefore, the polycrystalline silicon film is formed on the front surface and the back surface of the semiconductor substrate. Since these polycrystalline silicon films contain a very high concentration of conductive impurities, in a semiconductor substrate on which this polycrystalline silicon film is formed, this polycrystalline silicon film is regarded as a diffusion source of impurities. In particular, when the surface of the semiconductor substrate is exposed near the polycrystalline silicon layer containing these conductive impurities, after forming the polycrystalline silicon film, an oxide film is formed on the surface of the semiconductor substrate, annealing or the like is performed. After the thermal process described above, impurities diffuse from the polycrystalline silicon film from the exposed surface of the semiconductor substrate into the substrate.
[0003]
FIG. 15 shows a device cross section in a step of forming a gate oxide film of a DRAM transistor. In FIG. 15, 1 is a P-type silicon substrate, 2 is an isolation region, and 3 is N ⁺ Plate made of type polycrystalline silicon, 4 is a capacitive insulating film, 5 is N ⁺ Diffusion region, 6 is a P-type diffusion region, 7 is N ⁺ Out diffusion of phosphorus from polycrystalline silicon, 8 is a gate oxide film, 9 is an N-type diffusion region, 10 is N ⁺ Type polycrystalline silicon film.
[0004]
Gate Oxide Film Forming Step In FIGS. 15B and 15C, the cell plate 3 is formed of a polycrystalline silicon film containing a high concentration of conductive impurities. After the formation of the polycrystalline silicon film, phosphorus is diffused outward from the polycrystalline silicon film at the initial stage of forming the gate oxide film 8, that is, through processes such as charging of a silicon substrate, temperature ramping, and annealing. Is introduced into the transistor region where the substrate surface is exposed and is thermally diffused. Generally, the threshold voltage of a MOS transistor changes sensitively to a change in the impurity concentration on the substrate surface immediately below the gate electrode. As a result, a large change in the threshold voltage occurs. That is, in the case of the N-channel transistor of FIG. 15, phosphorus as an N-type impurity self-diffuses from cell plate 3, and the conductivity type of the channel region of the adjacent MOS transistor becomes N-type. As a result, the threshold voltage of the MOS transistor shifts to a large negative value, and the MOS transistor always becomes conductive.
[0005]
FIG. 16 is a sectional view of a MOS transistor having an LDD structure. 16, 21 is a P-type silicon substrate, 22 is a P-type well region, 23 is an N-type well region, 24 is an isolation region, 25 is a gate oxide film, and 26 is a P-type channel gate N. ⁺ Type polycrystalline silicon film, 27 is an N channel gate N ⁺ Type polycrystalline silicon film, 28 is a photoresist, 29 is LDD phosphorus implantation, 30 is a phosphorus implantation LDD region, 31 is an N-type diffusion region by self-diffusion, 32 is outward diffusion of phosphorus from a gate electrode, 33 is a channel region , 34 is N ⁺ Reference numeral 35 denotes a P-type source / drain region.
[0006]
The gate of the transistor is usually formed of a polycrystalline silicon film 27 containing a high concentration of conductive impurities. After forming the gate electrode, low-concentration impurities are implanted into the source / drain regions by ion implantation to form LDD (FIG. 16A). Thereafter, a heat treatment for activating the ion-implanted impurities is usually performed. At this time, impurities are diffused from the gate of the polycrystalline silicon film 27 into the source / drain LDD regions (FIG. 16B). When the conductivity type forming the LDD region is the same as the conductivity type of the impurity of the polycrystalline silicon film 27, the impurity concentration of the LDD region of this transistor becomes high, and as a result, this transistor becomes a short channel. That is, in FIG. 16C, in the N-channel transistor, the N-type impurity concentration in the LDD region increases due to the phosphorus atoms self-diffused from the N-type polycrystalline silicon film 27, and the diffusion length in the lateral direction also increases. Therefore, the channel region 33 becomes narrow and becomes a short channel. On the other hand, when the conductivity type of the impurity in the gate of the polycrystalline silicon film is opposite to the conductivity type of the LDD region, the impurity in the LDD region is compensated by the impurity diffused from the polycrystalline silicon film, and the impurity concentration in the LDD region decreases. As a result, the resistance of the LDD region increases, and in an extreme case, the transistor becomes an offset channel type transistor. As a result, the drive capacity is reduced.
[0007]
In FIG. 16B, phosphorus having conductivity opposite to that of the P-type source / drain is self-diffused in the source / drain regions of the P-channel transistor, and the P-type impurity and the N-type impurity are compensated. In FIG. 16C, an N-type diffusion region 31 of a high resistance layer is formed in the source / drain region of the P-channel transistor. In this case, the transistor becomes an offset channel transistor, the threshold voltage is largely shifted in the positive direction, and the driving capability of the P-channel transistor is significantly reduced.
[0008]
FIG. 17 is a device sectional view in the case of considering a MOS transistor having a DDD (double diffusion drain) structure.
[0009]
17, reference numeral 41 denotes a P-type silicon substrate, 42 denotes a P-type well region, 43 denotes an N-type well region, 44 denotes an isolation region, 45 denotes a gate oxide film, and 46 denotes a P-channel gate N. ⁺ Type polycrystalline silicon film, 47 is an N channel gate N ⁺ Type polycrystalline silicon film, 48 is a photoresist, 49 is DDD phosphorus implantation, 50 is a phosphorus implanted DDD region, 51 is an N-type diffusion region by self-diffusion, 52 is outward diffusion of phosphorus from a gate electrode, 53 is a channel region , 54 is N ⁺ Reference numeral 55 denotes a P-type source / drain region.
[0010]
In the DDD structure, similarly to the LDD structure, low-concentration impurities in the DDD region are ion-implanted (FIG. 17A). Thereafter, at the initial stage of the heat treatment for forming the DDD region, the impurity is diffused into the DDD region by self-diffusion from the polycrystalline silicon film 47 containing the impurity which is the gate electrode at a high concentration. Therefore, when the impurity in the DDD region is of the same conductivity type as that of the polycrystalline silicon film gate, a short channel state occurs. In the opposite case, an offset channel state is caused (FIG. 17 (c)). In addition, when a polycrystalline silicon film containing a high concentration of conductive impurities is present on the back surface of the silicon substrate, the silicon substrate in which the back surface of the silicon substrate and the front surface of the silicon substrate are placed facing each other in an oxidation furnace. In some cases, impurities are diffused on the surface of the substrate, causing the above-described problem. These phenomena are simply a phenomenon in which a polycrystalline silicon film containing high-concentration conductive impurities serves as a diffusion source and diffuses into an exposed surface of a semiconductor substrate surface approaching the diffusion source. I have. The degree of the auto-doping largely depends on the temperature of the heat treatment in the heat treatment furnace, the time, the atmosphere, the pitch of the silicon substrate, the structure of the silicon substrate boat, and the structure of the gas flow electric furnace in the furnace. The auto-doping becomes more remarkable as the silicon substrate pitch is narrower and the boat has a closed structure. On the other hand, in recent years, vertical electric furnaces have attracted attention and are being introduced instead of horizontal furnaces. When a vertical furnace is used, auto-doping is more remarkably observed.
[0011]
FIG. 18 shows a conventional example of a heat treatment apparatus for performing such annealing and oxidation. Here, a vertical diffusion furnace is shown. In the figure, 60 is a process tube, 61 is an exhaust port, 62 is a silicon substrate, 63 is a boat, 64 is a heater, 65 is a cap, 66 is a seal, 67 is a pedestal, 68 is a gas inlet, and 69 is a process gas flow. is there. In the conventional example, the process gas is introduced from the upper portion of the process tube 60, flows through the process tube 60, and is then discharged from the exhaust port 61 at the lower portion of the tube. At this time, the process gas flows from the upper portion to the lower portion of the process tube 60. For this reason, a laminar flow is formed around the silicon substrate 62, so that these process gases are less likely to flow toward the center of the silicon substrate 62. At the center of the silicon substrate, the conductive impurity gas released outward from the highly doped polycrystalline silicon film formed on the front or back of the silicon substrate has no gas flow passing between the silicon substrates. It stays between silicon substrates. As a result, a portion of the silicon substrate where silicon is exposed is auto-doped. Further, in an impurity diffusion furnace in which an impurity region is formed on a silicon substrate surface with uniformity using a process gas, the process gas does not easily flow between the silicon substrates, particularly toward the center of the silicon substrate. In this case, it is considered that the supply of the process gas to the center of the silicon substrate 62 is governed by diffusion. When an impurity diffusion device having such a structure is used, the impurity concentration in the surface of the silicon substrate 62 is lower at the center of the silicon substrate 62 than at the periphery. Further, since the concentration of the process gas becomes lower toward the lower part of the process tube 60, a large difference occurs in the impurity concentration between the silicon substrate 62 above the process tube 60 and the silicon substrate 62 below the process tube 60. When diffusion is performed in an impurity diffusion furnace having a conventional structure, the impurity concentration in the central portion of the silicon substrate 62 becomes lower than a target value in the surface of the silicon substrate 62. As a result, the specific resistance increases (FIG. 19). On the other hand, between the silicon substrates 62, the impurity concentration of the silicon substrate 62 above the process tube 3 and the impurity concentration of the silicon substrate 62 at the center of the process tube 60, and the impurity concentration of the silicon substrate 62 below the process tube 60 are different. As a result, the specific resistance of the silicon substrate 62 is different. The difference in the specific resistance in the longitudinal direction of the process tube 60 changes depending on the gas flow rate and the exhaust speed. In a diffusion furnace having a conventional structure, a temperature gradient is provided in the longitudinal direction of the process tube 60 in order to compensate for such non-uniformity of the specific resistance of the silicon substrate 62 in the longitudinal direction of the process tube 60. As for the uniformity in the plane of the silicon substrate 62, a method of improving the uniformity by rotating the boat 63 on which the silicon substrate 62 is loaded can be considered. However, even if the silicon substrate 62 is rotated, the uniformity is obtained. The specific resistance at the center of the silicon substrate 62 is not improved. In order to improve this, it is conceivable to use an injector 70 as shown in FIG. 20 in the longitudinal direction of the process tube 60. In the injector 70 shown in FIG. 20, holes having a diameter of about 1 mm are provided along the longitudinal direction of the injector 70 at intervals of an integral multiple of the pitch of the silicon substrate 62. It is structured to squirt in the direction. However, in the injector 70 having this structure, the speed of the gas ejected from the hole near the gas inlet 68 and the speed of the gas ejected from the gas outlet 71 at the tip of the injector 70 are greatly different. The gas ejection speed from the hole near the gas inlet 68 of the injector 70 is higher than the tip of the injector 70. Therefore, the specific resistance at the upper part and the specific resistance at the lower part of the process tube 60 are significantly different. Also, regarding the in-plane uniformity, when the holes are provided facing the silicon substrate 62, the gas flow rate is high in the portion near the holes in the surface of the silicon substrate 62, and the temperature of the surface of the silicon substrate 62 decreases. For this reason, the specific resistance is increased, and an appropriate value can be obtained at a portion farthest from the hole. Further, the value of the specific resistance is high at the center of the silicon substrate 62. At this time, the resistivity distribution in the plane of the silicon substrate 62 is as shown in FIG. On the other hand, when this hole is directed to the tube wall of the process tube 60 in the direction opposite to the silicon substrate 62, the gas collides with the tube wall, is decelerated, and the reflected gas flow reaches the silicon substrate 62. As a result, an appropriate value is obtained for the specific resistance of the portion close to the injector 70. However, since the gas flow speed is not sufficient in a portion farther from the injector 70 than the central portion of the silicon substrate 62, the gas does not spread, and a phenomenon occurs in which the specific resistance increases. FIG. 21B shows the specific resistance distribution in the silicon substrate 60 surface at this time. When such an injector 70 is used, the silicon substrate rotating mechanism is very effective. The specific resistance becomes substantially uniform around the silicon substrate 62 by the silicon substrate rotating mechanism, but still remains high at the center of the silicon substrate 62. FIG. 22 shows a specific resistance distribution in the plane of the silicon substrate 62 when the silicon substrate rotation is adopted for the injector 70. However, as described above, when rotating the silicon substrate, it is necessary to install the rotating mechanism in a high-temperature and corrosive gas atmosphere, which makes it difficult to ensure the reliability of the rotating mechanism. Further, there is a disadvantage that the apparatus itself is complicated and expensive.
[0012]
These devices may be used for the purpose of impurity diffusion or for the purpose of annealing and oxidation. When used for oxidation, water vapor generated by burning hydrogen gas and oxygen gas at a temperature of 760 ° C. or higher is used as an oxidizing agent. Such an oxidation method is known as a pyrogenic oxidation method and is used for forming a gate oxide film and an oxide film for isolation. This method is excellent in controllability of purity and water vapor content. In the pyrogenic oxidation, generally, a mixed gas of oxygen and hydrogen is ejected from the tip of an injector into a process tube of an oxidation furnace inside the process tube, and is burned in a high-temperature furnace to generate steam. At this time, from the explosion limit of hydrogen, the oxygen flow rate is set to 180% or less in consideration of safety with respect to the hydrogen flow rate. At this time, the temperature at the tip of the injector needs to be 760 ° C. or more. At this time, the ratio of water vapor to the entire oxidizing atmosphere can be determined by adjusting the flow rate of oxygen to hydrogen. In steam oxidation, the growth rate of the oxide film is determined by the partial pressure of water vapor in the atmosphere. That is, when the film thickness is small and the film thickness is required to be controlled, such as a gate oxide film, the partial pressure of water vapor in the oxidizing atmosphere may be reduced. That is, steam is generated by burning hydrogen and oxygen in an oxygen-rich atmosphere.
[0013]
These pyrogenic oxidations have traditionally been by burning in a process tube. However, when hydrogen and oxygen are burned in the process tube, a problem arises in that the temperature in the process tube becomes non-uniform due to the ejection of high-temperature combustion gas, and the film thickness becomes non-uniform. For this reason, an external combustion system in which a combustion chamber is provided outside a process tube and is burned by a dedicated combustion heater is often used. FIG. 23 is a conceptual view of an external combustion type oxide film forming apparatus having a conventional structure. 81 is a process tube, 82 is a silicon substrate, 83 is a boat, 86 is an external combustion chamber, 87 is an external combustion heater, 88 is an injector, 89 is an oxygen port, 90 is a hydrogen port, and 91 is a water oxygen flame. Hydrogen and oxygen gas introduced from the oxygen port 89 and the hydrogen port 90 are mixed and heated in the injector 88 by the external combustion heater 87. The hydrogen and oxygen gases heated to 760 ° C. or higher ignite, are discharged from the tip of the injector 88 as a water oxygen flame 91 into the combustion chamber 86, and the generated steam is sent into the process tube 81.
[0014]
[Problems to be solved by the invention]
In the above-described conventional method of manufacturing a semiconductor device, the auto-doping involves a large change in the threshold voltage of the MOS transistor, both a short channel and an offset gate of the MOS transistor, and a reduction in the resistance of the contact diffusion region, as described above. It causes various fatal problems such as an increase in the junction depth and an increase in the junction depth. However, in recent years, semiconductor devices have become more highly integrated, and multilayer polycrystalline silicon films have been increasingly used as wiring and gate electrodes. Therefore, the problems caused by such auto doping tend to increase. In particular, in recent years, a vertical electric furnace has been tending to be introduced instead of the conventional horizontal electric furnace because of good uniformity of the oxide film thickness and easy automation. According to the investigation by the inventors, the vertical electric furnace has a structure in which the gas does not sufficiently reach between the silicon substrates, especially at the central portion, and thus is more susceptible to autodoping than the horizontal electric furnace. When polycrystalline silicon films containing conductive impurities are present on the back surface of the silicon substrate, the polycrystalline silicon film on the back surface is selectively removed to prevent auto-doping during the subsequent heat treatment, but the Auto-doping from a polycrystalline silicon film existing as a pattern still poses a problem.
[0015]
Further, in the above-described conventional heat treatment apparatus, a gas containing impurities is supplied to the surface of the silicon substrate 62 with good uniformity without using the silicon substrate rotation mechanism, and the gas is uniformly supplied in the longitudinal direction of the process tube 60. It is necessary to have a structure capable of supplying a gas containing impurities.
[0016]
In order to make the gas ejection speed from the gas ejection port 71 arranged in the longitudinal direction of the injector 70 uniform, the diameter of the gas ejection port 71 is changed from the gas introduction port 68 to the tip of the injector 70. There is a method of sequentially increasing the gas ejection speed so that the gas ejection speed from the nozzle becomes constant, and a method of reducing the interval between the gas ejection ports 71. However, in these methods, it is difficult to calculate the diameter of the gas outlet 71 that gives a constant speed, and it is difficult to process the diameter. In addition, there is a problem that the balance of each gas ejection port 71 is likely to be lost due to a temporal change of the diameter of the gas ejection port 71. In order to improve the uniformity in the surface of the silicon substrate 62, there is a method of using a plurality of injectors 70. However, two gas systems are required, and it is necessary to balance between the two injectors 70. is there. Therefore, there is a problem that a spatial margin between the process tube 60 and the silicon substrate 62 is reduced.
[0017]
Further, in the conventional pyrogenic oxidation method, in pyrogenous oxidation in an oxygen-rich atmosphere, the combustion of hydrogen and oxygen at the tip of the injector 88 is oxygen-rich, so that a normal combustion state is not achieved. In a normal combustion state, the flow ratio of oxygen to hydrogen is around 180%, and the temperature of the water oxygen flame 91 at this time is combustion at a relatively low temperature. On the other hand, in the case of oxygen rich, combustion becomes explosive due to excess oxygen, and the temperature of the water oxygen flame 91 becomes extremely high. Further, in the structure of the conventional injector 88, hydrogen and oxygen gas are mixed and ejected from the same injector 88. Since the diameter of the tip of the injector 88 is usually narrowed, the ejection speed of the mixed gas of hydrogen and oxygen ejected from the tip of the injector 88 becomes extremely high.
[0018]
[Means for Solving the Problems]
In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention forms a high-concentration impurity diffusion layer or a conductive film containing a high-concentration impurity on a semiconductor substrate, and thereafter forms the impurity diffusion layer or the conductive film. Forming an oxide film on the surface of the semiconductor substrate other than the area covered by the first step of introducing the semiconductor substrate into an oxidizing apparatus; a second step of setting the temperature to a predetermined temperature after the introduction; And a third step of annealing at a temperature of 1. The first, second, and third steps are performed in a mixed atmosphere of oxygen and nitrogen.
[0019]
Further, a high-concentration impurity diffusion layer or a conductive film containing a high-concentration impurity is formed on the semiconductor substrate, and then, an oxide film is formed on a surface of the semiconductor substrate other than a region covered with the impurity diffusion layer or the conductive film. In doing so, the method includes a first step of introducing the semiconductor substrate into an oxidizing apparatus, a second step of bringing the semiconductor substrate to a predetermined temperature after the introduction, and a third step of annealing at the predetermined temperature. Is performed in a low-temperature oxygen atmosphere, and the second and third steps are performed in a non-oxidizing atmosphere.
[0020]
Further, a cell plate is formed on a semiconductor substrate with a capacitor insulating film interposed therebetween, and the cell plate is formed of a conductive film containing a high concentration of impurities. And a third step of performing annealing at the predetermined temperature after the introduction, and a third step of performing annealing at the predetermined temperature. The first, second, and third steps are performed in a mixed atmosphere of oxygen and nitrogen. Processing to form a gate oxide film.
[0021]
A step of forming a conductive film containing impurities on the semiconductor substrate; a step of performing first ion implantation using the conductive film as a mask; and a step of introducing the semiconductor substrate into an oxidizing device after the first ion implantation. A first process, a second process of bringing the temperature to a predetermined temperature after the introduction, and a third process of annealing at the predetermined temperature. The first, second, and third processes are performed in a mixed atmosphere of oxygen and nitrogen. A step of performing oxidation in the inside, a step of forming an insulating film on the side wall of the conductive film, and a second ion implantation using the conductive film and the side wall as a mask.
[0022]
A step of forming a conductive film containing impurities on the semiconductor substrate; a step of performing first ion implantation using the conductive film as a mask; and a step of introducing the semiconductor substrate into an oxidizing device after the first ion implantation. A first process, a second process of bringing the temperature to a predetermined temperature after the introduction, and a third process of annealing at the predetermined temperature. The first, second, and third processes are performed in a mixed atmosphere of oxygen and nitrogen. A step of performing oxidation in the inside, a step of forming an insulating film on the side wall of the conductive film, and a second ion implantation using the conductive film and the side wall as a mask.
[0023]
In addition, a conductive film containing an impurity is formed over a semiconductor substrate, and a first impurity having a large diffusion coefficient is doped at a low concentration by ion implantation using the conductive film as a mask, and a second impurity having a small diffusion coefficient is doped. A first step of introducing the semiconductor substrate into an oxidation device after doping with a high concentration, a second step of bringing the semiconductor substrate to a predetermined temperature after the introduction, and a third step of annealing at the predetermined temperature. The first, second and third steps are performed in a mixed atmosphere of oxygen and nitrogen.
[0024]
In order to solve the above problems, a semiconductor manufacturing apparatus according to the present invention includes a process tube, a substrate boat in which a semiconductor substrate is set in the process tube, and an injector for introducing a process gas into the process tube. Is supplied in parallel with the semiconductor substrate plane.
[0025]
In order to solve the above problems, a semiconductor manufacturing apparatus according to the present invention includes a process tube, a boat installed in the process tube, a gas inlet for introducing a gas into the process tube, and the process tube. An exhaust port for discharging gas from the inside, and a gas introduced from the gas introduction port is introduced into the process tube through an injector, and the injector extends in a longitudinal direction of the process tube beyond a length of the boat. Have a
[0026]
In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention is directed to a method of manufacturing a semiconductor device on a polycrystalline silicon film, a silicon dioxide film, a silicon nitride film, or a composite film composed of a combination of these films. Performing a thermal oxidation in a water vapor atmosphere by burning hydrogen gas and oxygen gas, and further after the thermal oxidation, a polycrystalline silicon film is further formed on the silicon substrate or a film on the silicon substrate by a chemical vapor deposition method. Forming a silicon dioxide film, a silicon nitride film or another vapor-growth film, and burning by setting the oxygen gas flow rate to 0.56 times the hydrogen gas flow rate with respect to the hydrogen gas flow rate in the thermal oxidation; Oxygen is further mixed with water vapor generated by combustion.
[0027]
Further, in order to solve the above problems, the semiconductor manufacturing apparatus of the present invention has a combustion chamber for hydrogen and oxygen gas, a heater for external combustion, and an injector outside the process tube, and generates steam generated in the combustion chamber. Means for feeding oxygen into the process tube, introducing oxygen from another inlet provided in the process tube, and automatically determining a hydrogen gas flow rate and an oxygen gas flow rate used for the combustion; Calculating means for calculating the amount of oxygen to be mixed with the steam.
[0028]
[Action]
According to the configuration of the present invention, by performing the heat treatment in accordance with the heat treatment sequence, the oxide film grown on the surface of the semiconductor substrate by the subsequent oxidation step is not adversely affected. By growing a thin oxide film for preventing impurity diffusion on the surface of the semiconductor substrate, self-diffusion from a high-concentration impurity layer can be prevented. Further, by using a heat treatment apparatus provided with a gas injector having a structure in which a process gas flows between the semiconductor substrates in the diameter direction of the semiconductor substrate, impurities diffused outward from the high-concentration impurity layers on the front and back surfaces of the semiconductor substrate are reduced. Cannot be kept between the semiconductor substrates, and is carried together with the process gas. Therefore, self-diffusion can be prevented. Of course, these methods may be used alone or in combination, and when used in combination, a reliable effect can be expected.
[0029]
【Example】
A case where the present invention is applied to a heat treatment of a MOS transistor having an LDD structure using a vertical diffusion furnace will be described below.
[0030]
When a MOS transistor having an LDD structure is formed, the process differs between an N-channel transistor and a P-channel transistor as shown in FIG. First, a P-type well region 102 and an N-type well region 103 are formed on the surface of a P-type silicon substrate 101. An isolation region 104 is formed between the well regions 102 and 103. An N-channel transistor is formed in the P-type well region 102, and a P-channel transistor is formed in the N-type well region 103. A gate oxide film 105 is formed on a silicon substrate 101, and an N film serving as a gate electrode of a P-channel transistor is formed thereon. ⁺ Form polycrystalline silicon film 106 is formed. The other is N, which is the gate electrode of the N-channel transistor. ⁺ Form polycrystalline silicon film 107 is formed. These polycrystalline silicon films 106 and 107 contain 3 × 10 3 phosphorus atoms. ²⁰ / Cm ³ Heavily doped. Next, a gate electrode of the transistor is formed by a known photolithography technique and a dry etching technique. Thereafter, the LDD region 110 formed by phosphorus implantation to be the source / drain region 114 is in a state where the surface of the silicon substrate 101 is exposed. This is because the gate oxide film 105 has become thinner, and even if an oxide film may remain during dry etching when forming the gate electrode, the oxide film is damaged by etching. And is easily removed.
[0031]
Next, in order to form an LDD region 110 of an N-channel transistor, a region where a P-channel transistor is to be formed is masked with a photoresist 108. Thereafter, phosphorus ions 109 are implanted into the entire surface of the substrate. Thus, an LDD region 110 is formed. At this time, 2 × 10 2 ¹² / Cm ² Only ions are implanted (FIG. 1A).
[0032]
Subsequently, a side wall is formed on the gate electrode. As the sidewall material, a high-temperature oxide film (HTO) formed by CVD, a TEOS oxide film formed by CVD, or the like is used. Annealing and formation of an oxide film are performed for the purpose of strengthening the adhesion of the sidewall material and activating the phosphorus ions 109 implanted into the LDD region 110 in the previous step. This heat treatment causes phosphorus atoms to diffuse outward from the gate electrodes of the polycrystalline silicon films 106 and 107 and self-diffuse to the LDD region 110. As a result, the conductivity type of LDD region 110 becomes N-type. When the LDD region 110 becomes N-type, the amount of phosphorus ions implanted into the LDD region 110 of the N-channel transistor increases. As a result, the resistance of the LDD region 110 decreases, the phosphorus ions introduced by the outward diffusion diffuse, and the N-type region reaches below the gate electrode. When the N-type region reaches below the gate electrode, the channel of the N-channel transistor becomes a short channel.
[0033]
On the other hand, in a P-channel transistor, N-type phosphorus atoms are compensated for with P-type impurities introduced to form the source / drain regions 115 in a later step. Therefore, a PN junction is formed at a position between the high resistance layer or the source / drain region 114 and the region immediately below the side wall region. As a result, the P-type diffusion layer of the source / drain region 114 does not substantially reach below the gate electrode, and the device functions as an offset gate transistor.
[0034]
In order to prevent this, the initial step of the heat treatment shown in FIG. 1B, that is, the step of putting the silicon substrate 101 into the furnace, the step of stabilizing the temperature, and the steps of performing temperature ramping and annealing are devised. is necessary. FIG. 2 shows a heat treatment sequence in these steps.
[0035]
In FIG. 2, an initial stage of the heat treatment is performed with a nitrogen gas containing 1 to 5% by volume of oxygen. Therefore, a thin oxide film 117 is formed on the surface of the gate electrodes of the polycrystalline silicon films 106 and 107 containing high-concentration impurities as a diffusion source at an early stage of the heat treatment. The oxide film 117 serves as a barrier when the high-concentration impurity diffuses outward, and suppresses the outward diffusion of the impurity. Also, a thin oxide film is formed on the surface of one LDD region 110. Impurities in which oxide film 117 is outwardly diffused can be prevented from diffusing into LDD region 110. The initial stage of the heat treatment is performed in an atmosphere having low reactivity so as not to oxidize the silicon surface. In particular, when activating the ions introduced into the substrate by the heat treatment, oxygen present generates OSF (Oxygen Induced Stacking Fault). For this reason, it is necessary to avoid oxidizing the substrate surface more than necessary. In this embodiment, it is necessary to form a thin oxide film in order to prevent impurities from diffusing on the silicon surface. Therefore, if the heat treatment is performed at a low temperature of, for example, about 700 ° C., diffusion of impurities hardly occurs, but at the same time, an oxide film on the surface hardly grows. On the other hand, at a temperature of about 1000 ° C., diffusion of impurities easily occurs, but an oxide film also easily grows at the same time. As described above, the diffusion amount of the impurity and the thickness of the oxide film have a trade-off relationship. The thickness of the oxide film must be at least 5 nm. Therefore, when growing at a temperature of 900 ° C. as in this embodiment, the oxygen partial pressure is set to about 1 to 5% by volume. If the oxygen partial pressure is 1% by volume or less, the oxidizing power is weak, so that sufficient diffusion of impurities cannot be prevented. Occurs. Here, when the growth temperature is set to about 800 ° C., the oxygen partial pressure can be used at 1% by volume to 10% by volume for the same reason.
[0036]
The annealing and oxidation conditions are as follows. First, the silicon substrate 101 is put into a furnace at a temperature of 900 ° C. The charging time is about 30 minutes. At this time, the flow rate of nitrogen gas was 14.55 liters per minute and the flow rate of oxygen was 0.45 liters in the furnace. After the silicon substrate 101 has been put into the furnace, the silicon substrate 101 is left for 20 minutes for temperature stabilization with the position of the silicon substrate 101 fixed in order to stabilize the temperature in the furnace. By this temperature stabilization, the inside of the furnace is uniformly maintained at 900 ° C. Next, while maintaining the flow rate of nitrogen (14.55 liters per minute), oxygen is introduced into the furnace at a flow rate of 15 liters per minute and hydrogen at a flow rate of 7.5 liters per minute to perform oxidation. The oxidation time is 16 minutes. After that, the supply of oxygen and hydrogen is cut off, and only the nitrogen is flown at the same flow rate while the silicon substrate 101 is taken out of the furnace. The removal time of the silicon substrate 101 is 30 minutes. However, in the step of flowing oxygen and hydrogen, nitrogen is also flowing at the same time. However, the flow of nitrogen may be stopped and only oxygen and hydrogen may flow. Here, the temperature is set to 900 ° C. because the thickness of the oxide film for protecting the silicon substrate surface after activation after ion implantation is about 30 nm, so that the redistribution and oxidation of the impurities are performed. It is used at 900 ° C. from the viewpoint of film thickness controllability. The input time is set to about 30 minutes so that stress due to thermal change of the silicon substrate is not applied as much as possible and crystal defects are not generated. The nitrogen gas flow rate is set to 14.55 liters per minute so that the inside of the process tube can be purged in a short time.
[0037]
At this time, the grown oxide film has a thickness of about 3 to 5 nm in the LDD region 110, and becomes 2 to 3 times the oxide film thickness in the LDD region 110 depending on the impurity concentration on the surfaces of the polycrystalline silicon films 106 and 107. . When the concentration of the impurity contained in the polycrystalline silicon film is used at the above value, an oxide film 117 having a thickness of 8 to 15 nm grows on the polycrystalline silicon film. Since the growth of the oxide film 117 occurs simultaneously with the outward diffusion of the phosphorus atoms contained in the gate electrode, the diffusion of phosphorus into the LDD region 110 due to auto doping can be prevented. Therefore, there is no adverse effect on the thickness and quality of the oxide film formed in the subsequent oxidation step. In this embodiment, the introduction was performed in a nitrogen atmosphere containing 3% by volume of oxygen.
[0038]
Further, even when a polycrystalline silicon film containing a high concentration of impurities is formed on the back surface of the P-type silicon substrate 101 or the back surface of the silicon substrate 101 is exposed, the silicon substrate adjacent to the silicon The present embodiment can also be used when the impurity 101 adheres and diffuses to the polycrystalline silicon film and the back surface.
[0039]
Subsequent to these heat treatments, an oxide film for forming the side wall 116 of the LDD region 110 is deposited using CVD. Thereafter, an LDD side wall 116 is formed through a photolithography and etching process. Thereafter, arsenic is used for the N-channel transistors and BF is used for the P-channel transistors using the LDD side walls 116 and the gate electrodes as a mask and the source / drain regions 114 as the masks. ₂ Is implanted to complete a MOS transistor having an LDD structure (FIG. 1C).
[0040]
That is, using the LDD side wall 116 and the gate electrode as a mask, the source / drain region 114 of the N-channel transistor is formed of arsenic, ₂ Is used. At this time, when arsenic is implanted into the N-channel transistor, the P-channel transistor is masked with a resist, and conversely, the N-channel transistor is masked with a resist.
[0041]
At this time, the LDD regions 110 of the N-channel and P-channel transistors have no diffusion region of phosphorus atoms due to auto-doping. Therefore, a short-channel effect does not occur in the N-channel transistor. In a P-channel transistor, phosphorus atoms are BF ₂ Therefore, no offset channel transistor is formed because no compensation is caused.
[0042]
FIG. 3 shows an embodiment for a MOS transistor having a DDD structure.
[0043]
In FIG. 3, a P-type well region 122 and an N-type well region 123 are formed on a P-type silicon substrate 121. An isolation region 124 is formed in a boundary region between the P-type well region 122 and the N-type well region 123 to electrically separate them from each other. A gate electrode is formed on the silicon substrate 121 in each of the well regions 122 and 123 via a gate oxide film 125. The gate electrode is a P-channel transistor gate N in the N-type well region 123. ⁺ Type polycrystalline silicon film 126 and the other is an N-channel transistor gate N ⁺ It is formed of a type polycrystalline silicon film 127.
[0044]
Next, the N-type well region 123 is masked using a photoresist 128. After that, phosphorus ions 129 are implanted. The DDD region 130 is formed by this phosphorus implantation. Next, predetermined annealing and oxidation are performed on the silicon substrate 121 to form an oxide film 131. At this time, immediately below the gate electrode sandwiched between the DDD regions 130 becomes the channel region 133. Further, N ions are implanted into the P well region 122 by ion implantation using a photoresist as a mask. ⁺ Type source / drain region 134 and P-type ⁺ Form source / drain regions 135 are formed.
[0045]
Here, as in the case of the LDD structure, during the initial stage of annealing and oxidation, which is a step after the implantation of low-concentration phosphorus ions 129 into the DDD region 130, high-concentration impurities contained in the gate electrode are diffused outward. Then, it is diffused to the DDD region 130. In order to prevent this, at the initial stage of these heat treatments, treatment is performed according to the heat treatment sequence shown in FIG. First, while maintaining the temperature at 800 ° C., oxygen gas is flowed at 15 liter / min. The silicon substrate 121 is put in this oxygen atmosphere over 30 minutes. When the loading of the silicon substrate 121 is completed, it is left in that state for 20 minutes to stabilize the temperature in the furnace. Next, after the temperature is stabilized, the flow of the oxygen gas is stopped, and the nitrogen gas is caused to flow into the furnace at 15 liters per minute. At the same time, the temperature is raised at a rate of 4 ° C. per minute, and the temperature is raised to 900 ° C. after 25 minutes. Thereafter, annealing is performed for 30 minutes in a nitrogen atmosphere. As described above, the thin oxide film 128 is formed on the surfaces of the polycrystalline silicon films 126 and 127 containing high-concentration impurities and the surface of the DDD region at the initial stage of the heat treatment, thereby suppressing the outward diffusion of impurities and preventing the impurities diffused outward. Diffusion to the DDD region 130 can be suppressed (FIG. 3B).
[0046]
Thereafter, the nitrogen gas is shut off, and 15 liters of oxygen gas and 15 liters of hydrogen gas per minute are caused to flow into the furnace. In this state, the silicon substrate 121 is oxidized by standing for 16 minutes. What is important here is to form a thin oxide film 128 on the surfaces of the polycrystalline silicon films 126 and 127 and the surface of the DDD region 130 which are diffusion sources at the earliest stage of the heat treatment. In the embodiment shown here, the silicon substrate is charged at a low temperature of 800 ° C., so that the silicon substrate is less likely to be diffused outward. After the oxidation, the flow of the oxygen gas and the hydrogen gas is shut off, and the nitrogen gas is caused to flow at a rate of 15 liters per minute. In this nitrogen atmosphere, the temperature is lowered at a rate of 4 ° C./min, and is raised to 800 ° C. after 25 minutes. Further, in this state, the silicon substrate 121 is taken out for 30 minutes.
[0047]
The temperature at the time of doping is set to 800 ° C. in order to reduce the diffusion of impurities of phosphorus at the time of doping and to reduce the amount of impurities diffused outward from the high concentration impurity diffusion layer. In this case, the oxygen atmosphere is set at a temperature of 800 ° C., so that even if the oxygen partial pressure is 100% by volume, the thickness of the oxide film grown in 20 minutes is 4.5 nm. This prevents diffusion of impurities. After that, the nitrogen gas is supplied at the time of raising the temperature because an oxide film serving as a barrier for impurity diffusion has already been formed in the previous step, so that it is not necessary to flow the oxygen gas here.
[0048]
FIG. 5 shows an embodiment in a step of forming a gate oxide film of a DRAM having a two-layer polycrystalline silicon structure. First, a field oxide film serving as an isolation region 142 is formed in a predetermined region of a P-type silicon substrate 141. Next, a P-type diffusion region 146 is formed in the silicon substrate 141. Further, N serving as the source and drain of the MOS transistor ⁺ A mold diffusion region 145 is formed. Next, a capacitor insulating film 144 and an N-type ⁺ A type polycrystalline silicon film cell plate 143 is formed (FIG. 5A). Thereafter, a gate insulating film 148 is formed on the silicon substrate 141 on which the MOS transistor is to be formed. Further, a thin oxide film 151 is formed on the surface of the cell plate 143. Here, the cell plate 143 is formed of a polycrystalline silicon film containing a high concentration of impurities. Therefore, during the formation of the gate oxide film 148 of the MOS transistor as the selection transistor, the impurities diffused outward from the cell plate 143 self-diffuse into the silicon substrate 142 immediately below the gate insulating film in the initial stage of the formation process of the gate oxide film 148. I do. In order to prevent this, processing is performed by a heat treatment sequence shown in FIG. First, while maintaining the temperature at 900 ° C., the oxygen gas is flowed at 0.45 liter / min so that the oxygen gas becomes 14.55 liter / min and the oxygen concentration becomes 3% by volume. The silicon substrate 141 is put into this atmosphere over 30 minutes. When the loading of the silicon substrate 141 is completed, the silicon substrate 141 is left in that state for 20 minutes to stabilize the temperature in the furnace. Next, after the temperature is stabilized, annealing is continuously performed for 30 minutes. Next, the flow of the nitrogen gas is stopped, the flow rate of the oxygen gas is set to 15 liters / minute, and the flow rate of the hydrogen gas is 7.5 liters / minute to oxidize for 9 minutes. Thereafter, the oxygen gas and the hydrogen gas are shut off, and instead, nitrogen gas is flowed at 14.55 liter / min. At the same time, the temperature of the furnace is raised at a rate of 4 ° C. per minute for 25 minutes to change from 900 ° C. to 1000 ° C. In this state, annealing after oxidation is performed for 20 minutes. Thereafter, the temperature is lowered at a rate of 4 ° C. per minute in a nitrogen atmosphere, and the temperature is lowered to 900 ° C. after 25 minutes. In this state, the silicon substrate 141 is taken out for 30 minutes. In this manner, as shown in FIG. 5B, in the initial stage of the heat treatment, a thin oxide film 151 is formed on the cell plate 143 and the gate region of the select transistor, and the outward diffusion of impurities from the cell plate 143 and The diffusion of the outwardly diffused impurities into the gate region is suppressed. Also in this case, the thickness of the oxide film 151 grown before the formation of the predetermined gate oxide film 148 by the heat treatment of this embodiment is about 5 nm. The thickness and quality of the gate oxide film 148 after the gate oxidation (FIG. 5C) are not affected. Of course, the same effect can be obtained when the treatment in oxygen at a low temperature is performed as shown in the embodiment of the DDD structure.
[0049]
Thereafter, the gate electrode N ⁺ Form polycrystalline silicon film 150 is formed on gate insulating film 148 (FIG. 5D).
[0050]
The above is an embodiment by improving the manufacturing method. Hereinafter, an embodiment using a manufacturing apparatus having a mechanism for solving these problems will be described. In this embodiment, a case in which a vertical electric furnace in which auto doping easily occurs is generally used will be described. FIG. 7A shows an embodiment of the vertical electric furnace of the present invention.
[0051]
In FIG. 7, a silicon substrate 160 is set on a substrate boat 165. The substrate boat 165 is installed in the vertical direction of the process tube 162 (the vertical direction on the paper). The silicon substrates 160 are installed vertically to the substrate boat 165, that is, in the vertical direction of the substrate boat 165 at substantially equal intervals one by one in the horizontal direction of the paper. A heater 163 is provided outside the process tube 162. Further, an injector 161 for supplying a process gas 164 is mounted inside the process tube 162. In order to efficiently carry out the impurities diffused outward between the silicon substrates 160 from between the silicon substrates 160, a gas flow horizontally flowing between the silicon substrates 160 is necessary. In order to realize the gas flow in the horizontal direction, a gas introduction pipe of the injector 161 having a discharge port in the horizontal direction that is an integral multiple of the silicon substrate pitch is provided.
[0052]
FIGS. 7B, 7C, and 7D show detailed drawings of the gas injector 161 used in this embodiment. As the injector 161, a quartz tube having one closed side is used, and gas ejection ports 166 are linearly arranged in the longitudinal direction of the injector 161 at equal intervals. This interval is set to be twice as long as the interval at which the silicon substrates 160 are installed on the substrate boat 165. FIG. 7C is a cross-sectional view along a longitudinal direction of a portion of a circular region A in FIG. 7B, and FIG. 7D is a cross-sectional view taken along line BB ′ in FIG. 7B. It is.
[0053]
The injector 161 has a double pipe structure in which an outer pipe having an outer diameter of 10 mm and an inner diameter of 8 mm is provided with an inner pipe having an outer diameter of 6 mm and an inner diameter of 4 mm. The process gas 164 introduced from one end of the injector 161 is once introduced into the inner pipe. The gas is discharged from the gas ejection port 167 into the gap between the inner pipe and the outer pipe while the gas advances toward the tip of the injector 161 through the inner pipe. At this time, the flow rate of the gas ejected from the gas ejection port 167 is different between the tip portion and the root portion of the injector 161. That is, the flow velocity at the tip becomes slower than the flow velocity at the root. However, once the process gas 164 is released into the gap between the inner tube and the outer tube, it serves as a buffer, and the flow velocity distribution in the longitudinal direction of the injector 161 can be suppressed. The buffer prevents the flow velocity at the distal end from being lower than the flow velocity at the root, and makes the flow velocity from the root at the distal end the same. That is, once the gas discharged from the inner tube of the concentric tube is temporarily stored in the buffer, the flow speed at the tip portion and the root portion at the time of exiting from the outer tube become substantially equal.
[0054]
The gas outlets 166 provided in the outer tube are formed such that the respective gas outlets 166 have an angle of 90 degrees with each other in the annular cross section shown in FIG. 7D. In this embodiment, since the silicon substrates 160 are installed on the substrate boat 165 at an interval of 4.76 mm, the pitch of the gas ejection ports 166 is 9.76 mm. Here, the total number of gas ejection ports 166 is 160. Further, as shown in FIG. 7D, the gas outlet 167 having a diameter of 2 mm provided in the inner tube is provided at a position having an inner angle of 135 degrees with respect to the gas outlet 166 provided in the outer tube. However, the gas outlets 167 do not need to be installed at finer intervals than the gas outlets 166, and in this embodiment, they are installed every five pitches. The gas outlet 166 allows gas to flow in the space between the silicon substrate 160 and the next substrate. For this purpose, it is preferable to provide the same number of gas injection ports as the distance between the substrates. However, since the gas ejected from the gas ejection port 166 spreads at the same time as the ejection, it is arranged at twice the distance between the substrates in this embodiment. On the other hand, since the gas outlet 167 of the inner tube may be jetted to the buffer, it is irrelevant to the distance between the substrates. However, if the interval between the substrates is too small, the flow rate of the gas ejected to the buffer at the tip portion and the root portion of the injector is different. Therefore, in this embodiment, the interval between the substrates is set to about 5 to 10 times, and A certain flow velocity is ensured.
[0055]
With the above configuration, the process gas 164 once released into the gap between the inner tube and the outer tube is discharged into the process tube 162 from the gas ejection port 167 installed in the outer tube. At this time, the flow velocity of the process gas 164 discharged from the gas ejection port 167 becomes substantially equal both at the tip of the injector 161 and at the root. The process gas 164 released from the gas ejection port 166 flows between the silicon substrates 160 in parallel to the front and back surfaces of the silicon substrate 160, reaches the other tube wall of the process tube 162, and is exhausted through the exhaust port. At this time, the process gas 164 flowing in parallel with the surface of the silicon substrate 160 diffuses outward from the back surface or the surface of the silicon substrate 160, and carries a gas containing impurities discharged outside from the space between the silicon substrates 160 at a flow rate. The process gas diffused outward from the silicon substrate 160 itself can be prevented from being re-diffused into the silicon exposed region on the surface of the silicon substrate 160 again. Here, the gas flow rate in the longitudinal direction of a 150 mm diameter process tube without such an injector is 0.7 cm / sec when oxygen or nitrogen flows at 15 liter / min. When an injector is used, the speed is increased to 53 cm / sec, approximately 76 times. Thus, the outwardly diffused impurities are exhausted without reaching the substrate. That is, when an injector is used, the flow velocity at the center of the silicon substrate is about 0.3 cm / sec. Therefore, if a silicon substrate having a diameter of 6 inches is used, it takes about 50 seconds until the gas passes. At this time, the process gas 164 needs to flow uniformly between the silicon substrates 160. For this reason, the gas outlets 166 provided in the outer tube are installed at an angle of 135 degrees with each other. Further, by rotating the silicon substrate 160, a more uniform gas flow can be secured.
[0056]
In this embodiment, the injector 161 has a straight pipe structure. However, in practice, the injector 161 may have a folded structure for the purpose of preheating the process gas 164 or the like. The same effect can be obtained regardless of the direction in which the injector 161 is inserted from above or below the process tube 162.
[0057]
When heat treatment is performed on a semiconductor device having a high-concentration impurity layer or a polycrystalline silicon film containing a high-concentration impurity on part or all of the front and back surfaces of a silicon substrate as in the present invention, outward diffusion from these impurity layers is performed. It is possible to prevent impurities from being inadvertently diffused into the exposed portion of the silicon substrate surface. As a result, in the MOS transistor having the LDD and DDD structures, the fluctuation of the threshold voltage due to the short channel or the offset channel and the fluctuation of the current driving force can be prevented. Further, in a semiconductor device having multi-layered polycrystalline silicon, auto-doping in the step of forming a gate oxide film can be prevented, and fluctuation in threshold voltage can be prevented.
[0058]
FIG. 8 shows a sectional structure of an impurity diffusion apparatus which is a second vertical diffusion furnace having the structure shown in the present invention. The silicon substrate 170 is installed on a substrate boat 171. The substrate boat 171 is installed in the vertical direction of the process tube 173 (the vertical direction on the paper). The silicon substrates 170 are installed vertically to the substrate boat 171, that is, in the vertical direction of the substrate boat 171 at substantially equal intervals one by one in the horizontal direction of the paper. The substrate boat 171 is attached to a pedestal 179 formed on a cap 177. The substrate boat 171 loaded with the silicon substrate 170 is inserted and removed from below the process tube 173 by an automatic machine. A heater 174 is provided outside the process tube 173. Further, an injector 176 for supplying a process gas 175 is mounted inside the process tube 173. The process gas 175 introduced from the gas inlet 180 passes through the inside of the injector 176 and is introduced into the process tube 173. The introduced process gas 175 is exhausted through a gas exhaust port 181 through a predetermined process. In addition, the injector 176 has a folded structure in which the injector 176 is introduced from a lower position outside the process tube 173, is guided to the upper portion of the process tube 173, and is folded back at the upper portion of the process tube 173 to be introduced into the process tube 173. I have. The process tube 173 is sealed by a cap 177 via a seal 178. Thus, the inside of the process tube 173 is operated in a reduced pressure state.
[0059]
A gas ejection port 182 is provided at the folded portion. By forming the injector 176 in a folded structure, the process gas can be preheated in the process tube 173 and then introduced into the process tube 173. By this injector 176, the process gas 175 spreads over the entire length of the substrate boat 171 on which the silicon substrate 170 is loaded.
[0060]
FIG. 9 shows the structure of an injector used in this impurity diffusion device. FIG. 10 is a longitudinal sectional view of the injector in the circular region A in FIG. FIG. 11 is an annular sectional view taken along line DD ′ in FIG. FIGS. 9, 10 and 11 are configuration diagrams of the injector 176 shown in the present invention. It has the same structure as the injector of the first vertical diffusion furnace. That is, high-purity quartz was used as a constituent material of the injector 176. The injector 176 is a double pipe having a folded structure, and the process gas 175 introduced from the gas inlet 180 is preheated to the turning point, and from the turning point, passes through the inner pipe of the double pipe, and to the inner pipe. The gas is discharged into the gap between the inner tube and the outer tube from the gas outlet 182 arranged. At this time, the velocity of the gas ejected from the gas ejection port 182 of the inner pipe differs between the tip end portion of the injector 176 and the folded portion. However, once the gas is released into the gap between the inner tube and the outer tube, the velocity difference of the gas is greatly reduced. Therefore, when gas is ejected from the gas ejection port 182 provided in the outer tube, the difference between the gas ejection speed at the tip portion of the injector 176 and the gas ejection speed at the turn-back portion is very small, and the gas ejection is uniform over the entire longitudinal direction of the injector 176. Speed can be realized. This can prevent not only the outward diffusion of the device realized by the first vertical diffusion furnace, but also the uniformity of the flow of the process gas 175 flowing between the silicon substrates 170. On the other hand, in the outer tube, two types of gas ejection ports 182 are arranged at an angle of 90 degrees to each other. The gas ejection ports 182 are linearly arranged in the longitudinal direction of the injector 176 at intervals of an integral multiple of the interval between the silicon substrates 170 arranged on the substrate boat 171. In this embodiment, the interval between the silicon substrates 170 is 5.84 mm, and therefore, the interval between the gas outlets 182 of the outer tube is set at every two pitches, that is, 11.68 mm. The diameter of the gas ejection port 182 was 1 mm. On the other hand, for the inner pipe, the interval between the gas ejection ports 182 was set to 5 pitches, that is, every 29.20 mm, and the diameter of the gas ejection ports 182 was set to 2 mm. Here, the diameter of the gas ejection port is determined by the gas ejection speed.
[0061]
The injector 176 is arranged at a distance of about 5 mm from the wall surface of the process tube 173. Two gas outlets 182 having an angle of 90 degrees with each other are arranged at angles of 45 ± 15 degrees and 135 ± 15 degrees with respect to the diameter direction of the process tube 173, respectively. That is, the bisector of the 90-degree angle formed by the two gas ejection ports 182 is 90 degrees with respect to the diameter direction of the process tube 173 and parallel to the tangent to the wall surface of the process tube 173.
[0062]
FIG. 12 shows the distribution of the specific resistance of the polycrystalline silicon film depending on the arrangement of the gas ejection ports 182. Here, an embodiment in which diffusion is performed using a process gas obtained by bubbling phosphorus oxychloride with nitrogen gas as a diffusion source will be described. In this method, impurities are diffused from a process gas into an oxide polycrystalline silicon film formed on a silicon substrate. Phosphorus oxychloride (purity 99.999999%) is maintained at 20 ° C. as a diffusion source, and nitrogen gas is flowed at 600 cc / min as a carrier gas. Thus, a process gas containing 120 mg / min of phosphorus oxychloride in nitrogen gas is generated. A mixed gas of nitrogen gas and oxygen gas is further introduced into the process tube at a flow rate of 20 liter / min and 160 cc / min, respectively. The temperature used for diffusion was 950 ° C., and the diffusion time was 20 minutes.
[0063]
The circle in FIG. 12 is a view of the process tube 173 as viewed from above. The outer circle is the outer periphery of the process tube 173, and the silicon substrate 170 is installed at the center of the process tube 173. The hatched portion of the silicon substrate 170 indicates a region having a high specific resistance, and the other regions are regions having a uniform specific resistance. The points at which the uniformity was measured were grid-like points that were 10 mm left, right, up and down from the center of the obtained silicon substrate 170, and there were 121 or more points in the silicon substrate 170. The uniformity was calculated by calculating the standard deviation from these measured values. Uniformity indicates the degree of variation in specific resistance centered on the target sheet resistance of 27Ω / □. The direction of the gas ejection port 182 of the injector 176 is shown on the right side in the drawing. The angle of the gas outlet 182 is a clockwise value from a horizontal line passing through the center of the gas outlet 182. The gas ejection direction is indicated by an arrow in the gas ejection port 182.
[0064]
FIG. 12A shows the specific resistance when the gas outlets 182 of the injector 176 are at 45 degrees and the other gas outlet 182 is at 135 degrees with respect to the diameter direction of the process tube 173. Is shown. Although the region with high specific resistance is biased around the silicon substrate, the uniformity has a relatively good value. FIG. 12 (b) shows the case of 45 degrees and 315 degrees, respectively (the bisector is parallel to the diameter direction of the tube and faces the tube wall). The region with high specific resistance occupies the left half of the silicon substrate, and has the poorest uniformity. FIG. 12C shows the case where the angle is 135 degrees and 225 degrees (the bisector is parallel to the diameter direction of the tube and faces the center of the tube). In this case, the region having a high specific resistance is distributed on the right side of the silicon substrate. The uniformity at this time is also poor. FIG. 12D shows the distribution of the specific resistance in the plane of the silicon substrate in the case where it is oriented at 0 degree and 90 degrees (the bisector is 45 degrees with respect to the diameter direction of the tube). In this case, the distribution is similar to that in the case of FIG. 12A, but the uniformity is slightly worse than that of FIG. 12A. From the above, FIG. 12A is the best. It is preferable that the angle at which the gas ejection port should be installed is within ± 15 degrees from a predetermined angle. Exceeding this range will result in poor uniformity.
[0065]
[Table 1]

[0066]
Table 1 shows the results of measuring the uniformity when the target specific resistance was set to 18 Ω / □, 27 Ω / □, and 700 Ω / □ using the direction of the injector 176 in FIG. Using the impurity diffusion apparatus of this embodiment, the uniformity within the surface of the silicon substrate 170 and the uniformity between the silicon substrates 170 were measured. The number of processed silicon substrates indicates the number of silicon substrates 170 filled in the substrate boat 171. As a result, in order to keep the gas flow constant in the diffusion furnace having the conventional structure, when processing a number of wafers equal to or less than the number that can be processed by the apparatus, a dummy silicon substrate other than the target silicon substrate 170 is loaded on the substrate boat 171. However, when the injector 176 is used as in the present embodiment, it is not necessary to use a dummy silicon substrate, and the number of silicon substrates 170 to be filled in the substrate boat 171 is 25 to 100. In any case, sufficient uniformity can be obtained.
[0067]
By using a double-coaxial injector having gas outlets in directions different from each other by 90 degrees as in the present invention for impurity diffusion in the gas phase, a large amount of semiconductor silicon substrates can be simultaneously in-plane and silicon substrates. Impurity diffusion can be carried out with good uniformity between them.
[0068]
In the above embodiment, the process sequence and the structure in the case of performing oxidation and annealing using a vertical diffusion furnace have been described. Next, an example in which an oxide film is formed by pyrogenic oxidation using a horizontal diffusion furnace will be described. Pyrogenic oxidation in an oxygen-rich atmosphere by a horizontal diffusion furnace does not result in a normal combustion state at the injector tip. Excessive oxygen causes combustion to explode and the temperature of the water oxygen flame becomes very high. Normally, the diameter of the injector tip is narrowed, so that the ejection speed of the mixed gas of hydrogen and oxygen ejected from the injector tip becomes extremely high. Normally, since the injector is made of fused quartz, quartz at the tip of the injector is melted by high-temperature combustion gas having a high flow rate due to explosive combustion. The fused quartz is released together with the high-speed combustion gas, becomes fine powder, and is introduced into the process tube together with the combustion gas. If the fine powder thus formed adheres to the silicon substrate when forming a device, the polycrystalline silicon film grows abnormally with the quartz powder as a nucleus, and the uniformity during etching is reduced. In addition, even when a pattern is formed by photolithography, the reflectance of the surface changes, and normal pattern formation is hindered.
[0069]
Hereinafter, embodiments of the horizontal diffusion furnace of the present invention will be described with reference to the drawings. FIG. 13 is a configuration diagram of the horizontal diffusion furnace of the present invention. In this embodiment, a case is described in which a silicon oxide film having a thickness of 20 nm is subjected to pyrogenic oxidation at a growth temperature of 900 ° C. on a silicon substrate at a hydrogen gas flow rate: oxygen gas flow rate = 5: 15 (liter / minute).
[0070]
In the figure, a silicon substrate 203 installed on a boat 202 is introduced into a process tube 201. The boat 202 is arranged on a cantilever 204. A gas baffle 206 is provided between a gas inlet 205 introduced into the process tube 201 and the boat 202. An external combustion chamber 207 is attached to the gas inlet 205. The external combustion chamber 207 is provided with an external combustion heater 208 and an injector 209. The injector 209 has an oxygen port 210 for supplying oxygen gas and a hydrogen / nitrogen port 211 for supplying hydrogen gas and nitrogen gas. The process tube 201 has a gas inlet 205 connected to the external combustion chamber 207 and another gas inlet 212 for supplying oxygen gas. The gas inlet 212 is connected to the oxygen port 213. A hydrogen mass flow controller 214, an oxygen mass flow controller 215, and an oxygen mass flow controller 216 are connected to the hydrogen / nitrogen port 211, the oxygen port 210, and the oxygen port 213, respectively. The oxygen mass flow controller 216 is controlled by a hydrogen / oxygen mixture ratio calculation unit 217. The oxygen mass flow controller 215 and the hydrogen mass flow controller 214 are controlled by an oxygen reduction calculator 218.
[0071]
Here, when the flow rates of the hydrogen gas and the oxygen gas are input to the input unit at 5 liters per minute and 15 liters per minute, the flow rate ratio for preventing the explosion due to the hydrogen gas and the oxygen gas is confirmed. In the case of this embodiment, the hydrogen gas: oxygen gas flow ratio is 3: 1. The upper limit of the flow ratio of hydrogen gas: oxygen gas that explodes due to both gases is 1.8: 1 or less, and there is no problem in the case of the embodiment. Here, the flow rate of hydrogen gas is 5 liters per minute as it is, while the flow rate of oxygen gas is hydrogen gas flow rate in order to realize a hydrogen gas flow rate: oxygen gas flow rate ratio of 1.8: 1 when performing external combustion. The calculation of 0.56 times the flow rate, that is, 2.78 liters per minute, is performed by the oxygen flow rate calculation unit 218.
[0072]
On the other hand, the amount of oxygen gas mixed with the steam generated by these combustions is calculated by the hydrogen / oxygen mixture ratio calculation unit 217. In the case of this embodiment, the target oxygen gas flow rate is 15 liters per minute, so the amount of oxygen gas mixed with water vapor is 12.22 liters per minute. The mass flow controllers 214, 215, and 216 are controlled according to the hydrogen gas flow rate and the oxygen gas flow rate, respectively. The hydrogen and oxygen whose flow rates have been determined by the hydrogen mass flow controller 214 and the oxygen mass flow controllers 215 and 216 are introduced into the external combustion device from the hydrogen / nitrogen port 211 and the oxygen port 210, respectively. This mixed gas is heated to 800 ° C. in the injector 209 by the external combustion heater 208 and burns at the tip of the injector 209. FIG. 14 shows the injector 209 used in this embodiment.
[0073]
The injector 209 includes an injector tip 220, an oxygen gas discharge end 221, an oxygen port 222, a hydrogen port 223, an O-ring seal 225, and a combustion chamber 226. A hydraulic oxygen flame 227 is generated at the injector tip 220 during operation. The injector 209 has a coaxial structure, and oxygen gas is introduced from the oxygen port 222 and discharged from the outer tube of the coaxial tube into the outer combustion chamber 221. On the other hand, hydrogen gas is introduced from the hydrogen port 223 to the injector tip 220 through the inner tube of the coaxial tube. Both the hydrogen gas and the oxygen gas are sufficiently heated by the external combustion heater while passing through the inside of the injector 209. In this embodiment, the number of the ejection ports of the injector tip 220 is one, and the inner diameter of the opening is 3 mm. When the flow rate of the hydrogen gas is 5 liters per minute, the ejection speed of the combustion gas is 11.8 m per minute. Further, the heat capacity of the injector tip 220 is increased by making the thickness of the injector tip 220 sufficiently thick, 3 mm. This is designed so that the temperature of the injector tip 220 does not significantly increase. Of course, to reduce the ejection speed, the inner diameter of the ejection port may be further increased, and the thickness of the injector tip 220 may be increased to further increase the heat capacity. In this embodiment, high-purity fused silica having high purity is used as the injector material, but synthetic quartz having low hydroxyl (OH) content and low impurity content may be used. In any case, since combustion occurs at the injector tip 220, the injector 209 gradually wears when used for a long period of time. Therefore, if a silicon carbide film deposited by CVD on the surface with a film thickness of 100 μm and having a high temperature resistance and a low impurity content as an injector material is used, an injector 209 that can be used semipermanently is obtained. It should be noted that the inner diameter and the wall thickness of the jet port need not be simply increased, but the length of the hydro-oxygen flame 227 must be considered. The length of the oxygen flame is determined by the distance from the injector tip 220 to the object in front of it, and is usually about 15 to 20 cm.
[0074]
In this manner, when the injector 220 is burned at 5 liters of hydrogen per minute and 2.78 liters of oxygen per minute, water vapor is generated. This water vapor is introduced into the process tube 201 through the external combustion chamber 226. In addition, according to the method of the present embodiment, since the melting of the injector tip 220 does not occur, the fused quartz powder is not introduced into the process tube unlike the related art.
[0075]
On the other hand, in order to achieve a target mixture ratio of hydrogen gas and oxygen gas, 12.22 liters of oxygen gas per minute supplied from the mass flow controller 216 is introduced from the oxygen port 213 provided in the process tube 201. . Thus, the water vapor and the oxygen gas are mixed in the process tube 201, and the target mixing ratio of the hydrogen gas and the oxygen gas is achieved. These mixed gases are transported to the silicon substrate 203 after being turbulent by the gas baffle 206.
[0076]
Through the above process, a silicon oxide film which is a very clean gate oxide film is formed on the silicon substrate. There is no fused quartz powder as shown in the conventional method on this gate oxide film. Therefore, even if phosphorus diffusion is performed by thermal diffusion when doping phosphorus atoms with phosphorus oxychloride in the polycrystalline silicon film in a later step, the polycrystalline silicon film does not grow abnormally. Further, in the present embodiment, the problem of halation due to surface roughness and the problem of residual etching in dry etching do not occur even in the known photolithography technology.
[0077]
Although the present embodiment describes an embodiment relating to gate oxidation and polycrystalline silicon deposition, the same effect can be expected in forming an oxide film for enhancing adhesion of a deposited film before deposition of the film by CVD. Needless to say. In addition, there is no difference in the effect of the present invention whether the underlying layer is a silicon oxide film on the silicon substrate, a silicon nitride film, or a pattern, instead of the oxidation of the silicon substrate. However, the adhesion of the fused quartz powder itself depends on the pattern and the underlying material, and also on the particle size at that time.
[0078]
As described above, when a silicon oxide film is formed or pyrogenic oxidation is performed by the method and apparatus for forming a silicon oxide film according to the present invention, melting of the tip of the quartz injector is significantly suppressed regardless of the mixing ratio of hydrogen and oxygen. The life of the quartz injector can be extended dramatically, and the fused quartz at the tip of the injector can be prevented from becoming fine powder and adhering to the silicon-silicon substrate. Then, abnormal growth at the time of depositing a CVD film can be prevented, and the process can be performed without lowering workability and lowering device performance and reliability.
[0079]
【The invention's effect】
As in the present invention, it is possible to prevent out-diffusion when a heat treatment is performed on a semiconductor device having a high-concentration impurity layer or a polycrystalline silicon film containing a high-concentration impurity on a part or all of the front and back surfaces of a silicon substrate. Variations in the threshold voltage of the MOS transistor having the DDD structure and a decrease in current driving capability can be prevented.
[0080]
Further, in the semiconductor manufacturing apparatus of the present invention, it is possible to simultaneously diffuse impurities into a large amount of semiconductor silicon substrates with good uniformity within the silicon substrate surface and between the silicon substrates.
[0081]
Furthermore, when the pyrogenic oxidation is performed, the melting of the tip of the quartz injector can be significantly suppressed, and the life of the quartz injector can be significantly extended.
[Brief description of the drawings]
FIG. 1 is a process sectional view of a method of manufacturing a semiconductor device having an LDD structure according to the present invention.
FIG. 2 is a view showing a heat treatment sequence of the semiconductor device manufacturing method of the present invention.
FIG. 3 is a process sectional view of a method for manufacturing a semiconductor device having a DDD structure according to the present invention;
FIG. 4 is a view showing a heat treatment sequence of the semiconductor device manufacturing method of the present invention.
FIG. 5 is a process sectional view of a method for manufacturing a semiconductor device which is a capacitive element according to the present invention.
FIG. 6 is a view showing a heat treatment sequence of the method for manufacturing a semiconductor device according to the present invention.
FIG. 7 is a diagram showing a semiconductor manufacturing apparatus of the present invention.
FIG. 8 is a view showing a vertical diffusion furnace which is a semiconductor manufacturing apparatus of the present invention.
FIG. 9 is a view showing an injector of the semiconductor manufacturing apparatus of the present invention.
FIG. 10 is a longitudinal sectional view of an injector of the semiconductor manufacturing apparatus of the present invention.
FIG. 11 is a sectional view of an injector of the semiconductor manufacturing apparatus of the present invention.
FIG. 12 is a diagram showing a resistivity distribution on a silicon substrate formed by the semiconductor manufacturing apparatus of the present invention.
FIG. 13 is a diagram showing a configuration of a semiconductor manufacturing apparatus of the present invention.
FIG. 14 is a view showing an injector of the semiconductor manufacturing apparatus of the present invention.
FIG. 15 is a process sectional view of a conventional method for manufacturing a semiconductor device which is a capacitive element.
FIG. 16 is a process sectional view of a conventional method for manufacturing a semiconductor device having an LDD structure.
FIG. 17 is a process sectional view of a conventional method for manufacturing a semiconductor device having a DDD structure.
FIG. 18 is a diagram showing a conventional semiconductor manufacturing apparatus.
FIG. 19 is a diagram showing a specific resistance distribution on a silicon substrate formed by a conventional semiconductor manufacturing apparatus.
FIG. 20 shows a conventional semiconductor manufacturing apparatus.
FIG. 21 is a diagram showing a specific resistance distribution on a silicon substrate formed by a conventional semiconductor manufacturing apparatus.
FIG. 22 is a diagram showing a resistivity distribution on a silicon substrate formed by a conventional semiconductor manufacturing apparatus.
FIG. 23 is a diagram showing a configuration of a conventional semiconductor manufacturing apparatus.
[Explanation of symbols]
101 silicon substrate
102,103 well area
104 Separation area
105 Gate oxide film
106,107 Polycrystalline silicon film
108 Photoresist
109 phosphorus ion
110 LDD area
113 channel area
114, 115 source / drain regions
116 Side wall
117 Oxide film

Claims (9)

A process tube, a substrate boat in which a semiconductor substrate is set in the process tube, and an injector for introducing a process gas into the process tube, wherein the process gas introduced from the injector is supplied in parallel with the semiconductor substrate plane. A semiconductor manufacturing apparatus characterized by the above-mentioned. A process tube, a boat installed in the process tube, a gas inlet for introducing gas into the process tube, an exhaust outlet for discharging gas from inside the process tube, and a gas introduced from the gas inlet. Gas is introduced into the process tube through an injector, and the injector has a length exceeding a length of the boat in a longitudinal direction of the process tube. 3. The semiconductor manufacturing apparatus according to claim 2, wherein said injector comprises a coaxial double tube. At least two first gas outlets having an angle of 90 degrees with respect to the center of the cross section of the outer tube of the double tube of the injector, and the first gas outlet of the inner tube of the double tube. 4. The semiconductor manufacturing apparatus according to claim 3, comprising a second ejection port having at least an angle of 135 degrees with respect to each of the two. 4. The gas introduced into the injector is discharged from the inner tube between the inner tube and the outer tube, and then discharged from the outer tube into the process tube. 13. The semiconductor manufacturing apparatus according to claim 1. A step of performing thermal oxidation in a steam atmosphere by burning hydrogen gas and oxygen gas on a polycrystalline silicon film or a silicon dioxide film or a silicon nitride film on a silicon substrate, or a composite film composed of a combination of these films; Forming a polycrystalline silicon film, a silicon dioxide film, a silicon nitride film or another vapor grown film on the silicon substrate or a film on the silicon substrate by a chemical vapor deposition method continuously after the thermal oxidation; Burning the oxygen gas flow rate with respect to the hydrogen gas flow rate by 0.56 times the hydrogen gas flow rate in the thermal oxidation, and further oxidizing the water vapor generated by the combustion by further mixing oxygen. Manufacturing method of a semiconductor device. Having a combustion chamber for hydrogen and oxygen gas, a heater for external combustion, and an injector outside the process tube, sending steam generated in the combustion chamber into the process tube, and further installed in the process tube, another Oxygen is introduced from the inlet, means for automatically determining the hydrogen gas flow rate and oxygen gas flow rate used for the combustion, and calculating means for calculating the amount of oxygen to be mixed with water vapor generated by the combustion are provided. Characteristic semiconductor manufacturing equipment. 8. The semiconductor manufacturing apparatus according to claim 7, wherein said injector has a coaxial structure, wherein hydrogen gas is emitted from an inner tube and oxygen gas is emitted from an outer tube. 8. The semiconductor manufacturing apparatus according to claim 7, wherein said injector is made of sintered silicon carbide of silicon carbide and silicon, and silicon carbide is coated therearound.

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