JP2004005993A - Digital signal recorder, recording method and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide digital signal recording method and device capable of corresponding to different transmission rates or formats of a recorded signal. <P>SOLUTION: A group of m packets of a digital signal in a packet format are arranged in n blocks. When the number of packets is m' (m' <m), the m packets are arranged in m' × n/m blocks to be recorded. Since packet arrangement is completed in the unit of n blocks, the digital signal recording method and device can easily correspond to different transmission rates or the formats of the recorded signal. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a digital video signal recording and reproducing apparatus for recording and reproducing digital video signals, and more particularly to a recording method and apparatus for recording and reproducing digital compressed video signals.
[0002]
[Prior art]
A digital signal recording apparatus for recording a digital compressed video signal on a magnetic tape using a rotating head is described in Japanese Patent Application Laid-Open No. 5-174496.
[0003]
[Problems to be solved by the invention]
However, no consideration is given to handling different types of recording signals.
[0004]
An object of the present invention is to provide a digital signal recording method and apparatus capable of coping with a case where a transmission rate or a format of a recording signal is different.
[0005]
[Means for Solving the Problems]
The object is to add a synchronization signal, a control signal, and an error detection and correction code to a b-byte of a-byte packet format digital signal to form a block format, and form a digital signal recording area by a predetermined number of blocks for magnetic recording. In a digital signal recording method for recording on a medium, the ratio of a and b is set to n: m, the ratio of integers n and m satisfying n <a and m <b, and m packets are divided into n blocks. If the number of packets is m '(m'<m), then this can be achieved by arranging and recording m '× n / m blocks.
[0006]
By controlling the amount of data to be recorded on one track in packet units of a predetermined number of bytes, and arranging and recording m packets in n blocks, the packet arrangement is completed in n block units. It is possible to easily cope with the case where the rate or the format of the recording signal is different.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0008]
FIG. 1 shows the configuration of a recording / reproducing apparatus using the digital signal recording method of the present invention. FIG. 1 shows a device that is used for both recording and reproduction. Of course, the same applies to the case where recording and reproduction are independent. Reference numeral 100 denotes a rotating head, 101 denotes a capstan, 102 denotes a recording / reproducing signal processing circuit for generating a recording signal at the time of recording and demodulating a reproducing signal at the time of reproduction, and 104 controls a recording / reproducing mode, for example, a microprocessor. , A timing generation circuit 105 for generating a timing signal serving as a reference for the rotation of the rotary head 100, a servo circuit 106 for controlling the rotation speed of the rotary head and the tape, and a recording signal input or reproduction 107. An input / output circuit for outputting a signal, a timing control circuit 109 for controlling timing at the time of recording, an oscillation circuit 110 for generating a reference clock, a tape 111, and a recording / reproducing circuit 112 for an analog video signal.
[0009]
During recording, recording data in packet format is input from the input / output terminal 108 at arbitrary time intervals. Part of the packet data input from the input / output terminal 108 is input to the control circuit 104 via the input / output circuit 107. The control circuit 104 detects the type of the packet data, the maximum transmission rate, and the like based on the information added to the packet data or the information transmitted separately from the packet data, and determines the recording mode based on the detection result. The operation mode of the processing circuit 102 and the servo circuit 106 is set. The input / output circuit 107 detects packet data to be recorded and outputs the packet data to the recording / reproducing signal processing circuit 102. The recording / reproducing signal processing circuit 102 determines the number of packets to be recorded on one track according to the recording mode determined by the control circuit 104, generates an error correction code, ID information, a subcode, etc. It is generated and recorded on the tape 111 by the rotating head 100.
[0010]
At the time of reproduction, first, a reproduction operation is performed in an arbitrary reproduction mode, and the recording / reproduction signal processing circuit 102 detects ID information. Then, the control circuit 104 determines which mode has been recorded, and the operation mode of the recording / reproduction signal processing circuit 104 and the servo circuit 106 is reset to perform reproduction. The recording / reproducing signal processing circuit 104 performs detection of a synchronizing signal, error detection and correction, and the like from the reproduced signal reproduced from the rotary head 100, reproduces data, subcode, and the like, and outputs the reproduced data to the input / output circuit 107. The input / output circuit 107 outputs reproduced data from the input / output terminal 108 based on the timing generated by the timing generation circuit 105.
[0011]
At the time of recording, the operation timing of the recording / reproducing apparatus is controlled by the timing control circuit 109 based on the rate of the recording data input from the input / output terminal 108, and at the time of reproduction, the operation is performed based on the clock oscillated by the oscillation circuit 110. .
[0012]
When recording and reproducing an analog video signal, the analog video signal input from the input terminal 113 is subjected to predetermined processing by an analog recording / reproducing circuit 112 at the time of recording, and is recorded on a tape 111 by the rotary head 100 and reproduced. Sometimes, a video signal reproduced by the rotary head 111 is output from an output terminal 114 after a predetermined process is performed by an analog recording / reproducing circuit 112. In this case, although not shown, the servo circuit 106 is controlled based on the frame period of the analog video signal. The analog recording head may be used as a digital recording head, or may be provided independently.
[0013]
FIG. 2 shows a recording pattern of one track. Reference numeral 3 denotes an additional information recording area for recording an audio signal, 7 denotes a data recording area for recording a digital compressed video signal, 12 denotes a subcode recording area for recording subcodes such as time information and program information, and 2, 6 and 11 denote respective areas. , 4, 8 and 13 are postambles of the respective recording areas, 5 and 9 are gaps between the respective recording areas, and 1 and 14 are margins at the track ends. By providing the postamble, preamble, and gap in each recording area in this way, it is possible to perform dubbing on each area independently. Of course, digital signals other than digital compressed video signals and audio signals may be recorded in the recording areas 3 and 7. Further, a digital compressed audio signal may be recorded together with the digital compressed video signal in the area 7.
[0014]
FIG. 3 shows a block configuration of each area. FIG. 2A shows a block configuration of the additional information recording area 3 and the data recording area 7. Reference numeral 20 denotes a synchronization signal, 21 denotes ID information, 22 denotes data, and 23 denotes a parity (C1 parity) for first error detection and correction. For example, the synchronization signal 20 is composed of 2 bytes, the ID information 21 is composed of 3 bytes, the data 22 is composed of 99 bytes, the parity 23 is composed of 8 bytes, and one block is composed of 112 bytes. FIG. 2B shows a block configuration of the subcode recording area 12. In the block of the subcode recording area, the synchronization signal 20 and the ID information 21 are the same as in FIG. 2A, the data 22 is composed of 19 bytes, and the parity 23 is composed of 4 bytes. One block is shown in FIG. The block is composed of 28 bytes, which is 1/4 of the block. In this way, the number of bytes in one block is also made to be an integer ratio, and the configuration of the synchronization signal 11 and the ID information 12 is the same in all areas, so that the generation of the block at the time of recording and the synchronization signal at the time of recording are performed. , ID information detection and the like can be processed by the same circuit.
[0015]
FIG. 4 shows the configuration of the ID information 21. 31 is a sequence number, 32 is a track address, 33 is a block address in one track, and 35 is a parity for detecting an error in the sequence number 31, track address 32 and block address 33. The block address 33 is an address for identifying a block in each recording area. For example, 0 to 335 in the data recording area 7, 0 to 13 in the additional information recording area 3, and 0 to 15 in the subcode recording area 12. The track address 32 is an address for identifying a track. For example, by changing the address in units of one track or two tracks and setting it to 0-5 or 0-2, six tracks can be identified. . The sequence number 31 is changed, for example, in units of six tracks identified by the track address 32 and is set to 0 to 11, whereby 72 tracks can be identified. If the track address is synchronized with the cycle of a second error correction code described later, and the sequence number is synchronized with the recording cycle of variable-speed playback data described later, processing during recording and identification during playback can be facilitated. Can be.
[0016]
FIG. 5 shows the data structure of one track in the data recording area 7. Note that the synchronization signal 20 and the ID information 21 are omitted. The data recording area 7 is composed of, for example, 336 blocks, and records the data 41 in the first 306 blocks and the second error correction code (C2 parity) 43 in the next 30 blocks.
[0017]
For example, the C2 parity 43 divides data of 306 blocks × 6 tracks into 18 in units of 6 tracks, and adds 10 blocks of C2 parity to each 102 blocks. For example, a Reed-Solomon code may be used as the error correction code.
[0018]
Each block of 99-byte data is composed of a 3-byte header 44 and 96-byte data 41. FIG. 6 shows the configuration of the header 44 of the data recording area 7. The header 44 includes the format information 31, the additional information 32, and the block information 33.
[0019]
FIG. 7 shows the structure of the format information 31. The format information 31 is information relating to the recording format, and for example, one information is composed of 6 bytes of 12 blocks. By multiplex-recording this information a plurality of times, the detection capability at the time of reproduction is improved. The data of the six blocks includes, for example, the size of one block, the presence or absence of the additional information recording area 3, the number of programs to be recorded, the number of rotations of the rotary head, the method of error correction code, the recording mode, the format of the data to be recorded, and the like. ing.
[0020]
The recording mode defines, for example, the maximum recording capacity. In this embodiment, when two-channel recording is performed at a rotation speed of 1800 rpm using a four-head rotating head, data of about 25 Mbps can be recorded. Here, if recording is performed once every two times, the recording capacity becomes about 12.5 Mbps. If recording is performed once every four times, the recording capacity will be approximately 6.25 Mbps. In this case, if the tape feed speed is set to 1/2 or 1/4, the track pattern on the tape becomes almost the same. Similarly, the maximum recording capacity can be reduced to 1 / n of 25 Mbps. At the time of recording, the transmission rate of the recording data is identified, and an optimal recording mode is set for recording. Then, the mode in which recording was performed is recorded in the format information 31. For example, it is "1" at 25 Mbps, "2" at 12.5 Mbps, "3" at 6.25 Mbps, and the like.
[0021]
The format of the data to be recorded defines, for example, the packet length of the packet to be recorded. By controlling the amount of data to be recorded on one track in packet units and recording the recorded number, it is possible to cope with an arbitrary transmission rate. The control may be performed for one track or for a plurality of tracks. Also, by recording the packet length, it is possible to correspond to a packet of an arbitrary length.
[0022]
At the time of reproduction, the format information 31 may be detected to identify a recording mode or the like, and the reproduction processing circuit may be set to that mode for reproduction.
[0023]
Further, the recording information of the variable speed reproduction data of the format information 31 may be recorded. As shown in FIG. 8, by recording the data 50 exclusively for variable speed reproduction at a predetermined position corresponding to the miracle of the head at the time of variable speed reproduction, a good reproduced image can be reproduced even at variable speed reproduction. it can. Therefore, whether or not this data is recorded or what kind of data is recorded is recorded, and by identifying it at the time of reproduction, it is possible to easily cope with variable speed reproduction. it can.
[0024]
FIG. 9 shows the configuration of the additional information 32. The additional information 32 includes, for example, one block of information consisting of six bytes of six blocks. The first byte is an item code indicating the type of information, and the remaining five bytes are data. Can be recorded. For example, information such as the recording time and the type of the recording signal are recorded. Here, detailed information on the variable speed reproduction data may be recorded in association with the format information 31.
[0025]
FIG. 10 shows an example of a block configuration when a digital compressed video signal transmitted in a 188-byte packet format is recorded in the data recording area 41. In this case, 4-byte time information 25 is added to make 192 bytes, and one packet is recorded in two blocks. By recording one packet of data in correspondence with two blocks, that is, one code sequence of C1, when an uncorrectable block unit occurs due to a burst error due to dropout on a tape or the like, the error is transmitted in units of transmission. Does not span more than one packet.
[0026]
FIG. 11 shows a block configuration when the length of the packet 71 is 140 bytes. At this time, two packets 71 are recorded in three blocks. When there is only one packet, one packet may be arranged in two blocks as shown in FIG. That is, one packet may be arranged in 1.5 blocks, and the remaining 0.5 blocks may be dummy data.
[0027]
FIG. 13 shows another configuration example of the packet shown in FIG. 10 or FIGS. The packet includes, for example, 3-byte time information 25 and control information 72 related to a 1-byte packet as 188-byte or 140-byte packet data 71. If the number of packet data 71 is smaller than this, for example, 130 bytes, dummy data may be added and recorded, or the area of control information may be increased.
[0028]
The time information 25 is information on the time at which the packet was transmitted. That is, the time when a packet (the head) is transmitted or the interval between packets is counted by a reference clock, the count value is recorded together with the packet data, and the interval between the packets is determined based on the information at the time of reproduction. By setting, data can be output in the same form as when transmitted.
[0029]
As described above, if the ratio of the number of bytes of one packet to the number of bytes of the recording area of one block is represented by a simple integer ratio n: m, and m packets are recorded in n blocks, Even when the packet length is different from the recording area of one block, recording can be performed efficiently. Further, when the number of packets is not in units of m, for example, when m ′ (m ′ <m), the m ′ packets are arranged in m ′ × n / m blocks and recorded. If you do, you can record efficiently
n and m are smaller values than the number of bytes of one packet and the number of bytes of the recording area of one block, respectively, and if they can be represented by integers of about 10 or less, processing can be facilitated. It should be noted that even when the length of one packet is longer than the recording area of one block (n> m), recording can be performed in the same manner. Further, if the information such as the time information is the same in the packets of different lengths, the recording / reproducing process is facilitated. Identification in the case where the packet lengths are different may be performed using the format information 31.
[0030]
FIG. 14 shows the configuration of the block information 33. The block information 33 is information for identifying data in block units. The data information 74 is information for identifying the type of data recorded in this block. For example, 0 may be set for a block where normal packet data is recorded, 1 may be set for a block where valid data is not recorded, and 2 may be set for a block where variable speed reproduction data is recorded.
[0031]
The block number 75 is information for identifying the order of blocks when packet data is recorded in units of two blocks or three blocks. For example, when recording is performed in units of two blocks, 0 to 1, and when recording is performed in units of 3 blocks, 0 to 2. Furthermore, if the end of the recording area can be identified by such information, the processing at the time of reproduction becomes easy.
[0032]
FIG. 15 is a recording example of the block information 33 when the packet is recorded in the arrangement of FIG. 11 or FIG. Reference numeral 51 denotes a block in which normal packet data is recorded, 52 denotes a block in which variable speed reproduction data is recorded, and 53 denotes an unused area. In this way, by recording the data other than the variable speed reproduction data with the MSB justified, packet data input at an arbitrary interval can be efficiently recorded. If an invalid block occurs in between, the data information 74 of the block may be set to 1. In the unused area 53, the data information 74 is set to 1 and the block number 75 is set to 3 so that the end of the data can be detected.
[0033]
At the time of reproduction, the data information 74 is identified for each block, and if it is other than 0, the block may be skipped and output. This makes it possible to maintain compatibility at the time of reproduction regardless of where variable speed reproduction data or invalid data is recorded. Even if other special data is recorded, there is no problem if different data information is assigned to the block. Further, the end of the recording area can be detected by identifying the block whose data information 74 is 1 and whose block number is 3. As a result, there is no need to access an unnecessary area, so that the load during reproduction can be reduced.
[0034]
FIG. 16 shows an example of the case where the data is not left-justified, that is, the case where the packet to be recorded is recorded corresponding to the input position. In this case, since the unused area is dispersed throughout the track, it is not necessary to particularly identify the end of the data.
[0035]
FIG. 17 illustrates a configuration of the input / output circuit 107. Reference numeral 300 denotes a packet detection circuit, 301 denotes a time information confirmation circuit, 302 denotes an output control circuit, 303 denotes a buffer, and 304 denotes a time control circuit. It is assumed that the frequency of the clock that generates the time information of the packet input / output from the input / output terminal 108A is the same as the reference clock of the recording / reproducing device transmitted from the oscillation circuit 110.
[0036]
During recording, data and a synchronous clock are input from the input / output terminals 108A and 108B at the timing shown in FIG. The input data and the synchronous clock are input to the packet detection circuit 300, and packet detection is performed by the clock output from the timing generation circuit 105 input from the input terminal 307. Then, the detected packet 71 is output from the output terminal 305A to the recording / reproducing signal processing circuit 102. The recording / reproducing signal processing circuit 102 adds the block information 33 and the like to the packet 71 input during a period corresponding to one track of recording, and records the packet. The control signal and the like transmitted in addition to the packet are output from the output terminal 306A to the control circuit 104, where the type of the packet is determined, the recording mode is determined, and the like. The time information 25 added to each packet is output to the time information confirmation circuit 301.
[0037]
The time information confirmation circuit 301 compares the time information 25 with the interval between packets counted by the clock input from the input terminal 307. If there is a difference between the two, the timing control circuit 109 controls the recording processing timing and the number of rotations of the rotary head 100 so as to correct the difference based on a control signal output from the output terminal 308.
[0038]
At the time of reproduction, the output control circuit 302 is controlled to the output mode by a control signal from the control circuit 104 input from the input terminal 306B, and the reproduced packet 71 is output in synchronization with the reference clock transmitted from the oscillation circuit 110. I do. The recording / reproducing signal processing circuit 102 identifies the reproduced block block information 33 and the like, and outputs only valid and reproduced packets without errors. The packet input from the input terminal 305B is stored in the buffer 303. The time information 25 in the packet is input to the time control circuit 304. The time control circuit 304 controls the timing of reading and outputting a packet from the buffer 303 and generates a synchronous clock based on the time information 25 and the clock input from the input terminal 307, and generates the synchronous clock as shown in FIG. Output at the same timing as when it was input. As a result, in a device for receiving and processing reproduced packets, such as a digital compressed video signal decoding device and other digital signal recording / reproducing devices, recording and reproduction are performed in the same processing as when the signal before recording is directly processed. Can be processed.
[0039]
FIG. 19 shows an example of connection between the digital signal recording / reproducing apparatus of FIG. 1 and a digital broadcast receiver. Reference numeral 200 denotes the digital signal recording device of FIG. 1, 201 denotes a digital broadcast receiver, 202 denotes an antenna, and 206 denotes a receiver. 203 is a tuner, 204 is a selection circuit, 205 is a decoding circuit, and 206 is an interface circuit. After the digital broadcast signal received by the antenna 202 is demodulated by the tuner 203, the selection circuit 204 selects a required digital compressed video signal. The selected digital compressed video signal is decoded by the decoding circuit 205 into a normal video signal and output to the receiver 206. Further, when a process such as scrambling is performed on the received signal, the decoding circuit 205 cancels it and then performs a decoding process.
[0040]
At the time of normal reception, the digital broadcast receiver 201 demodulates a digital compression signal such as a so-called MPEG signal from a received signal, and decodes the digital compression signal into a normal video signal and an audio signal by a decoder and outputs the demodulated signal to a television or the like. Output to This digital compressed signal is usually transmitted in a packet format. The packet transmission rate varies depending on the content of the broadcast. The packet transmission interval also changes according to the encoding process. The decoder reproduces the frame frequency at the time of encoding from the information included in the data in the packet format and the interval at which the packet is sent, and decodes the video signal.
[0041]
At the time of recording from the digital broadcast receiver 201, the interface circuit 206 adds time information indicating a packet transmission interval to the packetized digital compressed signal, converts the signal into the format shown in FIG. 16, and outputs it. Then, it is input from the input / output terminal 108 to the digital signal recording device 200 and recorded. If the transmission is performed without adding the time information, the recording and reproducing apparatus 108 may add the time information and record.
[0042]
The digital compressed video signal and the like reproduced by the digital signal recording / reproducing apparatus 200 are output from the input / output terminal 108 to the interface circuit 206 at the same intervals as at the time of recording using time information. The interface circuit 206 performs the same processing as that at the time of normal reception from the input signal, and outputs the signal to the receiver 206. Then, the video signal and the audio signal are decoded and output to a television or the like.
[0043]
Note that the input / output circuit of FIG. 10 can be similarly applied to input / output circuits of other devices such as the digital broadcast receiver 201.
[0044]
Further, in the embodiment, the input and the output are performed using the shared terminal, but the input and the output may be performed using the independent terminals.
[0045]
【The invention's effect】
According to the present invention, the amount of data to be recorded on one track is controlled in packet units of a predetermined number of bytes, and m packets are arranged and recorded in n blocks, so that the arrangement of packets is n blocks. Since the recording is completed in units, recording can be efficiently performed even when the transmission rate or the format of the recording signal is different.
[0046]
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a digital signal recording / reproducing apparatus.
FIG. 2 is a recording pattern diagram of one track.
FIG. 3 is a block diagram of each area.
FIG. 4 is a configuration diagram of ID information 21;
FIG. 5 is a configuration diagram of data of one track in a data recording area 7;
FIG. 6 is a configuration diagram of a header 44 of the data recording area 7;
FIG. 7 is a configuration diagram of format information 31;
FIG. 8 is a diagram showing a recording example of variable speed reproduction data.
FIG. 9 is a configuration diagram of a configuration of additional information 32;
FIG. 10 is a block diagram of a block for recording a digital compressed video signal transmitted in a packet format of 188 bytes in a data recording area 41.
FIG. 11 is a block diagram of a block when the length of a packet 71 is 140 bytes.
FIG. 12 is another configuration diagram of the block when the length of the packet 71 is 140 bytes.
FIG. 13 is another configuration diagram of the packet of FIG. 10, FIG. 11, or FIG.
14 is a configuration diagram of block information 33. FIG.
FIG. 15 is a diagram showing a recording example of block information 33.
FIG. 16 is a diagram showing another example of recording block information 33.
17 is a configuration diagram of an input / output circuit 107. FIG.
FIG. 18 is a timing chart of input / output signals.
19 is a connection diagram of the digital signal recording / reproducing apparatus of FIG. 1 and a digital broadcast receiver.
[Explanation of symbols]
7 data recording area, 20 synchronization signal, 21 ID information, 22 data, 23 C1 parity, 25 time information, 31 format information, 32 additional information, 33 block information, 41 video signal data 43, C2 parity, 44, header, 50, variable speed data, 51, normal packet data 52, block recording variable speed reproduction data, 53, unused area, 71, packet, 72, control information, 74 data information, 75 block information, 100 rotary head, 101 capstan, 102 recording / reproducing signal processing circuit, 104 control circuit, 105 timing generation circuit, 106 servo circuit, 107 input / output circuit, 109: timing control circuit, 110: oscillation circuit, 112: analog signal recording / reproduction circuit, 300: packet detection circuit, 30 ... time information confirmation circuit, 302 ... output control circuit, 303 ... buffer, 304 ... time control circuit.

Claims (10)

A sync signal, a control signal, and an error detection / correction code are added to b bytes of a digital signal in a packet format of a byte to form a block format, and a predetermined number of the blocks form a digital signal recording area to be recorded on a magnetic recording medium. In a digital signal recording method for recording, a ratio of a and b is set to a ratio n: m of integers n and m satisfying n <a and m <b, and m packets are divided into n blocks. A digital signal recording method comprising: arranging and, when the number of packets is m ′ (m ′ <m), arranging and recording in m ′ × n / m blocks. 2. The digital signal recording method according to claim 1, wherein the a-byte packet includes packet data and additional information related to the packet data. 3. The digital signal recording method according to claim 2, wherein the additional information is information indicating a time at which the packet data was transmitted. 2. The digital signal recording method according to claim 1, wherein when the number of bytes of the packet is smaller than a, the packet is converted into an a-byte packet format and recorded. Wherein n is 3, m is 2, and the two packets are arranged in three blocks, and when the number of packets is one, they are arranged in two blocks and recorded. 2. The digital signal recording method according to claim 1, wherein: A sync signal, a control signal, and an error detection / correction code are added to b bytes of a digital signal in a packet format of a byte to form a block format. In the digital signal recording method for recording, a ratio of a and b is set to a ratio n: m of integers n and m satisfying n <a and m <b, and m packets are divided into n blocks. A digital signal recording apparatus, comprising: recording means for arranging and, when the number of packets is m '(m' <m), arranging and recording in m'.times.n / m blocks. 7. The digital signal recording apparatus according to claim 6, wherein the a-byte packet comprises packet data and additional information related to the packet data. 8. The digital signal recording apparatus according to claim 7, wherein the additional information is information indicating a time when the packet data was transmitted. 7. The digital signal recording apparatus according to claim 6, wherein when the number of bytes of the packet is smaller than a, the packet is converted into an a-byte packet format and recorded. Wherein n is 3, m is 2, and the two packets are arranged in three blocks, and when the number of packets is one, they are arranged in two blocks and recorded. 7. The digital signal recording device according to claim 6, wherein:

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