JP2003527755A - Digital communication processor - Google Patents

Abstract

(57) Summary In general, an integrated circuit (203) is used to process a data stream and, in special cases, a packet stream. The integrated circuit comprises a number of packet processors (307, 313, 303), a table lookup engine (301), a queue management engine (305), and a buffer management engine (315). The packet processor comprises a receiving processor (421), a transmitting processor (427), a risk (RISC) core processor (401), and other programmable elements.

Description

Description: FIELD OF THE INVENTION The present invention relates generally to digital packet networks, and more particularly to switches used in such networks. BACKGROUND ART Communication in a digital stream is generally performed using packets. Such a packet is shown at 113 in FIG. DISCLOSURE OF THE INVENTION In general, an integrated circuit (203) is used to process data streams and, in special cases, packet streams. This integrated circuit comprises a number of packet processors (307, 313, 303) and a table lookup engine (301).
And a queue management engine (305) and a buffer management engine (3).
15). The packet processor comprises a receiving processor (421), a transmitting processor (427), a risk (RISC) core processor (401), and other programmable elements. DETAILED DESCRIPTION OF THE INVENTION The following description describes a digital communication system including a digital communication processor according to the present invention.
Beginning with a description of the structure and operation of the packet switch, followed by a description of the structure and operation of the digital communication processor, and will cover details of the structure and operation of the components of the digital communication processor. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a block diagram of a packet switch in a network.

[Procedure amendment] [Date of submission] February 7, 2001 (2001.2.7) [Procedure amendment 1] [Document name to be amended] Description [Item name to be amended] Full text [Amendment method] Change [Amendment] Patent application title: DIGITAL COMMUNICATION PROCESSOR 1. A plurality of data receiving and / or transmitting data streams.
Data stream input and / or output; with a plurality of data stream processors processing said data stream
Wherein each is coupled to a data stream input and / or output: a writable instruction memory containing instructions; and sequentially executing certain ones of the instructions so that the data stream input
A receiving processor for processing the data stream received from the same; and / or
Processes the data stream by sequentially executing a specific one of the instructions
A plurality of data stream processors comprising: a transmission processor for outputting the data stream to the data stream output. 2. A method for receiving and / or transmitting a plurality of data streams.
Data stream input and / or output; and a plurality of data stream processors for processing said data stream.
Each being coupled to a data stream input and / or output,
With local writable memory located in the data stream processor
A plurality of data processors, wherein the plurality of local memories are associated with the data processing system.
A global address that can be addressed by any of the processors
An integrated circuit characterized by belonging to the address space. 3. A plurality of data receiving and / or transmitting data streams.
Data stream input and / or output; said data each being coupled to a data stream input and / or output
A plurality of data stream processors for processing the stream; and receiving from a particular data stream processor for processing the data stream.
Responding to the transmitted information and relating to the context of the particular data stream.
Context for generating information and providing the context information to the processor
A processor, wherein the specific data stream processor is the content
Processing said data stream using custom information
circuit. 4. The context processor receives the information and receives the information.
Data stream processor and each of the context processors
To provide the context information via a bus having an upper limit of the waiting time.
The integrated circuit according to claim 3, wherein: 5. A data stream and a data stream containing control data.
And multiple data streams that receive and / or transmit
Power and / or output; with a plurality of data stream processors processing said data stream
Where each data stream processor has a data stream input and / or
Or the output is coupled and the received data stream is processed to
And the payload is extracted, and the transmitted data stream is processed to control data.
A plurality of data stream processors for adding data to the payload; providing an address of a buffer for storing the payload, and accompanying a buffer address.
Write the payload to the addressed buffer in response to a write operation
Buffer addressed in response to a read operation with a buffer address.
A buffer manager for reading a payload from a queue; and a queue manager for managing a queue of descriptors of the payload, the queue manager comprising:
Comprises at least one buffer address, wherein the queue manager
The descriptor provided with the queue command is sent to the queue specified in the command.
Responds to the command by putting it in a matrix and is specified in the command
Queue responding to dequeue commands by removing descriptors from the queue
A column manager; wherein the data stream processor comprises a
The payload of the stream and the address provided by the buffer manager
Performs a write operation on the buffer manager, and includes the address.
Respond to the received data stream by performing an enqueue operation on the
The result of the dequeue operation in a read operation to the buffer manager
Perform a dequeue operation using the address in the descriptor obtained as
A data stream using the payload received from the
Data stream by generating and transmitting said generated data stream.
An integrated circuit for transmitting a program. 6. A plurality of data receiving and / or transmitting data streams.
Data stream input and / or output; said data each being coupled to a data stream input and / or output
A plurality of data stream processors for processing the stream; and integrating a particular one of said data stream processors to
The integrated data stream processor is used to process data streams.
A cooperating integrated device comprising: a configurable interconnect between the integrated data stream processors; a configurable operation for coordinating the operation of the integrated data stream processors.
A coordinator; and optionally the configurable interconnect and the configurable operation coordinator.
And a setting device for integrating the data stream processor. 7. A plurality of data receiving and / or transmitting data streams.
Data stream input and / or output; with a plurality of data stream processors processing said data stream
Wherein each is coupled to a data stream input and / or output: a control data processor; for processing a data stream received from said data stream input.
A receiving processor; and / or a transmission for processing a data stream and outputting to the data stream output
A processor; and the control data processor and the receiving processor and / or the transmitting
Processor and shared by the receiving processor and / or the transmitting processor.
The receiving processor and the control processor are used by the processor and the control data processor.
And / or data by said transmitting processor and said control data processor.
A data structure containing information for coordinating the pipelining of the data stream. A plurality of data stream processors comprising: 8. A plurality of data receiving and / or transmitting data streams.
Data stream input and / or output; and a plurality of data stream processors for processing said data stream.
Wherein each is coupled to a data stream input and / or output: serializing a data stream received from said data stream input
A receiving processor for processing the data stream serially and / or serially processing the data stream to output the data stream.
A plurality of data stream processors comprising: a transmitting processor for outputting; and the receiving processor and / or the transmitting processor
A plurality of processing components, and one or more of the components
Components to bypass the processing of the data stream.
An integrated circuit characterized by being able to. 9. A plurality of systems for receiving and / or transmitting data streams.
A real data stream input and / or output; and a plurality of data stream processors for processing said data stream.
Wherein each is coupled to a data stream input and / or output: a data stream received from said serial data stream input
A receiving processor for serially processing the data stream; and / or serially processing the data stream to obtain the serial data stream.
A plurality of data stream processors comprising: a transmission processor for outputting the processed data stream to a memory;
And / or the transmitting processor processes the data stream to be processed.
The receiving processor reads from the memory the data to be processed.
Data stream can be reconfigured to read and / or
Resets the communication processor to write the processed data stream to the memory.
An integrated circuit characterized in that it can be used. 10. A method for serially receiving and / or transmitting a data stream.
A plurality of serial data stream inputs and / or outputs; at least one set of packets for receiving and / or transmitting data streams in parallel.
A plurality of serial data stream processors for processing the data stream;
Processor, each of which is a serial data stream input and / or output
Coupled to the input: a data stream received from the serial data stream input
And / or a serial receiving processor that processes the data stream and outputs the data stream to the data stream output.
A real transmit processor; and at least one coupled to the set of parallel data stream inputs
A parallel data stream processor comprising: a data stream received from the set of parallel data stream inputs;
A parallel receiving processor for processing the stream; and / or for processing the data stream, the set of parallel data streams.
An integrated circuit comprising: a plurality of serial data stream processors comprising: a parallel transmission processor for outputting to a system output; and at least one parallel data stream processor comprising: 11. A plurality of I / O pins for receiving and / or transmitting signals; a data stream processor for processing data represented by the signals; a writable setting specifier for specifying the plurality of settings; And coupled between the plurality of I / O pins and the data stream processor;
In response to the setting specifier, the I / O pin is set according to the specification of the setting specifier.
An integrated circuit, comprising: 12. The method according to claim 11, wherein the setting specifier specifies an electrical characteristic of the I / O pin.
Setting the I / O pins according to the electrical characteristics required for the setting circuit configuration
The integrated circuit according to claim 11, wherein: 13. A data stream processor, comprising: a plurality of data stream processors;
The specifier is any one of the plurality of data stream processors.
Connected to the plurality of I / O pins, thereby enabling
A stream processor is received and / or transmitted by the plurality of I / O pins
The processing of the data represented by the signal can be shared.
Item 12. The integrated circuit according to Item 11. 14. A signal at the data stream input and / or output.
A plurality of I / O pins for receiving and / or transmitting; a writable setting specifier for specifying the plurality of settings; and a plurality of I / O pins coupled between the plurality of I / O pins and the data stream processor.
Responding to the setting specifier, the I / O pin according to the specification by the setting specifier.
To allow the integrated circuit to be used with multiple transmission protocols.
6. The integrated circuit according to claim 5, further comprising: a setting circuit configuration for enabling the setting. 15. Each data stream processor may include a plurality of processing components.
Components in the processing of the data stream.
That it can be individually configured to bypass one or more components.
The integrated circuit according to claim 5, wherein: 16. The method according to claim 16, wherein the data stream processor includes a specific data stream.
Integrating the stream processor to form the integrated data stream processor;
An integrated device with which the integrated data stream processor cooperates in processing the data stream: a configurable interconnect between the integrated data stream processors; a configurable operation that coordinates operation of the integrated data stream processor.
A coordinator; and if necessary to integrate said data stream processor,
A setting device for specifying a configurable interconnect and the configurable operation coordinator
The integrated circuit according to claim 5, further comprising: an integrated device comprising: 17. The method according to claim 16, wherein said data stream input and / or output is parallel.
At least one set of parallel receivers for receiving and / or transmitting data streams.
A data stream input and / or output;
A processor configured to output and / or output the set of parallel data streams;
At least one parallel data stream processor coupled to the
And each parallel data stream processor is provided with the set of parallel data streams.
Process and / or process data received from the data stream input.
Data stream to output to the set of parallel data streams.
6. The integrated circuit according to claim 5, wherein the integrated circuit is activated. 18. The data stream processor, the queue money
Manager and all of the buffer managers share one address space
The integrated circuit according to claim 17, wherein: 19. A specific data stream for processing a data stream.
Responsive to the information received from the processor, the particular data stream
Generate information about a context, and send the context information to the processor.
Further characterized by providing a context processor
An integrated circuit according to claim 5. 20. The method according to claim 20, wherein the context processor is configured to transmit the data stream to the data stream.
A first bus structure coupling the processor to the processor; and the data stream processor to the queuing manager and the buffer.
20. The integrated circuit of claim 19, further comprising: a second bus structure coupled to the manager. The present invention relates generally to digital packet networks, and more particularly to digital packet networks.
Relates to switches used in such networks. BACKGROUND OF THE INVENTION FIG. 1 Packets and Protocols Communication between digital systems generally occurs via packets. Packet
This is illustrated at 113 in FIG. The meaning of a packet depends on the protocol.
It is just a sequence of bits to be determined. Protocol processes packets
Defines how the digital device interprets the bits in the packet.
Regardless of the protocol, many packets have a header 115, which
Shows how that particular packet is processed according to the protocol.
It is. A packet is a payload that is the actual information communicated by the packet.
117. The packet also has a trailer 119, which simply indicates the end of the packet.
To indicate that an error occurred during the transmission or processing of a packet.
And / or may contain information that can be modified. The process that defines it
Depending on the protocol, packets have a fixed or variable length. In the following description,
The contents of the header 115 and the trailer 119 are referred to as protocol data. This is
The way in which these contents are interpreted is completely determined by the protocol.
The contents of the payload 117 are called payload data. Specific protocol
Are often referred to as frames or cells. [0002] Packets are at many different levels for communication in digital systems.
Used. As a result, packets at some level in a digital system
The group payload may be a higher level packet. Figure 1
137. The IP packet 121 is a packet interpreted according to the IP protocol.
It is. The IP packet 121 includes an IP header 123 and a variable-length IP payload 12
And 5. The information in the IP header 123 includes the length of the IP payload 125
It is. When the IP packet 121 is transported in the actual network,
It is carried in the payload of stream 135 of packet 127. Each transport packet
127 has its own header 129, payload 131, trailer 133,
Having. What is called a transport packet in this specification is the link layer of the ISO 7-layer model.
Packet. Transport packets depend on the protocol used at the link layer.
And have a fixed or variable length. A device that handles a transport packet includes a header 129 and a trailer 133 in the packet.
Address the packet and verify the contents of the payload 131 as indicated by
And not. When the transport packet reaches its destination, the payload is transferred to the target system.
Part, in this case, to components that operate according to the IP protocol,
Component handles IP packet 121 as indicated in IP header 123
. Of course, if the IP payload 125 is another higher-level packet,
In some cases. For example, a packet addressed to a decryptor
, The payload of the packet may be an encrypted IP packet 121
. In such a case, the component handling the IP packet 121 decodes the payload.
Passed to the crypter, the decryptor decrypts the encrypted IP packet 121 and decrypts it
Component that has already been sent back to the component.
Take action for processing. For this process, of course, the decrypted IP packet
Includes sending to a destination, and communication with that destination involves transport packets 127.
If it is through a protocol, the component that handles IP packets
Sends the decrypted IP packet to the component that generates the packet stream
, The decrypted IP packet is carried in the payload of the transport packet 127. Packet switch Packets are used to communicate between digital systems located remotely from each other.
The packet travels over the digital network that connects the systems.
I do. At the physical level, a digital network communicates between two devices.
Transmission medium, such as broadcast radio waves, conductors or optical cables.
Used. Packets are distributed between transmission paths by a packet switch. Packet
Switch distributes the packet according to the information normally contained in the packet header.
I do. [0004] As expected, various protocols have their own distribution rules. for example
For example, the IP protocol uses logical distribution. That is, each source of IP packets or
The destination has a logical IP address, and IP packets addressed to a certain destination are
The destination logical IP address. The header does not indicate the physical location of the destination
. IP packet switches must translate IP addresses to physical addresses
The physical address sends the packet at least part of the way to the destination
put out. Also, the IP packet switch carries the IP packet as the payload 131.
Constructs a stream 135 of transport packets destined for that physical address.
There must be. Therefore, the IP node 109 (n) is connected to the Ethernet LAN 105
Ethernet node 107 (n) on (a), connected to LAN 105 (a)
IP packet switches that carry IP packets as payload
Must respond to the IP packet destined for node 107 (n). A typical packet switch is shown at 101. The packet switch 101
Connected to several physical media 106 through which the packet switch 1
01 receives and transmits data. Examples of such media include optical fiber
・ There are cables or cables made of electric conductors. Each of these media 106
, Has its own protocol for defining data sent over the medium.
For example, a protocol widely used to send data over optical cables
One of the rules is the SONET protocol. In FIG. 1, the medium 106 (a ... m) is SO
An optical cable using the NET protocol, and the medium 106 (n ... z) is an electric cable.
Bull. Packets at the intermediate media level-referred to herein as media packets-
-Has a transport packet as its payload. In the ISO 7 layer model
, The media packet is a physical layer packet. In the switch 103, an optical cable
The transport packets transmitted and received on the ATM
Transport packets built according to the TM protocol and sent and received on electrical cables
Ethernet (TM) Pro used by Local Area Network 109
It is built according to Tokor. In most cases, the transport packet is used as its payload.
In this case, the packet switch 103 converts the IP packet to an IP packet.
To the host 109. As mentioned above, to make an IP packet reach its destination
Determine which medium 106 (i) is to be used and use that medium as the payload
Packets according to the protocol required for the medium with the transport packet stream
By building the stream, the packet switch does that. Also,
These packets have IP packets as their payload. For this reason,
The packet switch 103 is switched from the WAN 111 to the IP node 109 (n).
Upon receiving the packet, the IP node 109 (n) transmits the packet on the Ethernet LAN 105 (a).
If it is an Ethernet node 107 (n), the packet switch 103
Must construct a stream of packets in the format required by medium 106 (n).
No. The media payload is destined for Ethernet node 107 (n).
Streams of Ethernet packets that are
Have as payload. [0006] Therefore, the switch 103 must be able to:-switch the incoming stream of packets having the format required by the protocol of the input medium.
Read the payload, the transport packet and the payload of the transport packet.
Connecting the transport packet received on the ATM WAN 111 to the packet switch 103;
Delivering to other destinations in one of the connected Ethernet LANs; a packet switch 1 for transport packets received on the Ethernet LAN 105;
Delivering to other destinations in one of the Ethernet LANs connected to 03; delivering packets required by the IP address along with the IP packets; having the format required by the protocol of the output medium; Other types of payload
Outgoing stream of packets with transport packets as payload containing packets
Generating a system. For such a delivery, one type of transport packet is converted to another type of transport packet.
It becomes necessary. For example, an IP packet comes from ATM WAN 111 and
Ethernet node 109 (n) in the network LAN 105 (a) as a destination.
In this case, the packet switch 103 extracts the IP packet from the payload of the ATM transport packet.
Excerpt, and route it to Ethernet node 107 (n).
Must be included in the payload of the packet. [0008] In addition, the packet switch may provide filtering, encryption / decryption or switching.
Confidentiality functions such as scrambling / descrambling (descrambling)
Often used to perform. The packet switch 103 here
At the boundary between the private network 104 and the public network 102
Is shown. In the header of each IP packet 121, the source IP address of the packet
And the destination IP address, and the security means of the private network 104
Public network 102 with private source address to private network 104
Prohibits access by IP packets of private networks and private networks with specific source addresses.
Access from the network 104 to the public network 102 by packets is also prohibited.
I will. Switch 103 bans each incoming IP packet from its source address.
Filter by comparing to a list of source addresses
If the entry is on the list, discard it. The switch 103 receives the incoming packet
Is filtered in a similar manner. For encryption / decryption,
The switch 103 sends the payload to an IP address in the private network 104
IP packet from public network 102 that is an encrypted IP packet destined for
In some cases, may receive data. In such a case, the packet switch 103
Take out the encrypted IP packet, decrypt it, and
Send to the destination within. Similarly, the packet switch 103 is connected to the public network
IP packets sent to destinations belonging to private network 104 via
Receive, encrypt the IP packet, and send it to another IP
Before sending the packet, it may be placed as a payload in another IP packet. Problems caused by the packet switch The design of the packet switch causes many problems for engineers
. As is evident from the above description, the packet switch determines the incoming packet stream.
Place the payload in the stream, generate the outgoing packet stream, and
Or at a higher level to transform the information in the packet and fill
Perform complex operations, such as tapping and performing encryption / decryption.
No. Packet switches can perform these operations quickly and with high processing power.
Must be executed. In addition, the packet switch uses an e-mail
At a reasonable time (measured in time) after being sent through a service such as TV
Packets must arrive at their destination within a certain time of each other.
Not only the time interval between packets, but also the
Packets that impose strict restrictions on the total length of travel from the source to the destination
It must be able to handle a variety of services, up to the telephone system. In modern electronic devices, high speed, high throughput and time constraints are satisfied.
This has been achieved through the use of special-purpose hardware,
The complexity has been addressed by using programmable processors. Special
Special purpose hardware devices are usually fast but expensive and inflexible.
In addition, complicated processing cannot be performed. Devices with programmable processors
Is usually inexpensive and versatile and can perform any desired processing, but
You. [0010] For this reason, high speed packet switches have been compliant with special purpose hardware.
. As expected, such a packet switch is fast and has high processing power,
Time constraints could be met, but expensive, inflexible, and filtered
Complex functions such as encryption or encryption / decryption could not be performed. Sa
In addition, various transport protocols require their own specialized hardware,
Switch to change the transport protocol used by the high-speed switch
It was necessary to change the special purpose hardware. [0011] Slower packet switches are more programmable processor compliant.
It was. Again, as expected, these switches are relatively
It is inexpensive, can perform any desired complex function, and can be
All other protocol changes need to be reprogrammed
No. However, a packet switch compliant with a programmable processor
Is found in packet switches built with special purpose hardware.
Does not have the ability to satisfy such speed, processing, or time constraints. What is needed is a flexible, inexpensive, programmable processor standard.
Has the ability to perform complex functions specific to
Packet switch that satisfies constraints and can provide high speed and high processing power
It is. Providing such a packet switch is disclosed herein.
The purpose of a digital communications processor. SUMMARY OF THE INVENTION The present invention comprises a plurality of data stream processors and a stream context.
A collection comprising a host processor, a queuing manager, and a buffer manager.
By providing an integrated circuit, packets and packets that typically process a stream of data
Overcoming the above problems of switches and devices. [0014] The data stream processor receiving the data stream includes a data stream processor.
Extract control information from the stream, send it to the context processor,
Interpret as required by the context of the data stream
Process the data stream using the results provided by the processor. Day
To send more data streams, the data stream processor
The buffer from the incoming data stream is given to the buffer
Stored in a file and queue management of the enqueue command
To the sender. The enqueue command is a tag that identifies at least the buffer
And the data stream that is transmitting the data stream.
Queue specifier for the queue read by the
And The queue manager places the descriptor in the appropriate queue (enqueue
). The transmitting data stream processor removes the descriptor from the queue (data
Cue) and use the tag to remove the payload from the buffer and
Create an output data stream using the
Add control information if necessary. Descriptors are on the data stream processor
Is completely defined by the programs that work in
The receiving data stream processor and the transmitting data stream processor
Provides a general mechanism for ordering and communicating information with Sessa
. The data stream processor includes a receiving processor, a transmitting processor,
Control data processor, local memory, receive processor, transmit processor
Between the server and buffer manager, and between local memory and buffer manager.
And a DMA engine for performing a DMA access with the controller. Data stream
Local memory belonging to each of the processors;
The local memory belonging to the matrix manager has a single global address
Device that has access to the global address space, everything in between
Is read and written by Data stream processor is the data stream
While receiving the data, the receiving processor and the control data processor work together to
Process the stream as follows: the transmit processor receives the stream,
Extract control information from the robot, pass it to the control data processor,
To the buffer manager. The transmitting processor is the next part of the stream
Control data processor while working on the minute
Process the context information about the DMA-processed part using
Sends a command to the queuing manager with the descriptor of the DMA-processed payload
You. The data structure, called the data scope, allows the control data processor
Information exchange with the receiving processor is simplified. Transmit processor and control data
The interaction with the processor is substantially the same, but the payload is reversed
Moving. The data stream processor includes a serial data stream processor.
And at least one parallel data stream processor
You. Parallel data stream processors use integrated circuits to
Used to connect to integrated circuits, buses or switching fabrics. [0017] Serial data processors are highly configurable. Settings are global
• Performed by a register in the address space. Each serial data processor
Can receive and / or transmit separate data streams, or
Is used when serial data processors process a single data stream.
Sometimes integrated to work together. Serial data processor I / O pins
Are set up and integrated to meet the electrical requirements of different physical media.
All data processors can be configured to receive the same input.
Wear. Various devices in the receive or transmit processor are available as required
A particular type of serial input stream that is received or transmitted, disabled or disabled
Can be dealt with. Also, the receiving or transmitting processor has already processed
The data stream can be recirculated. This application is a priority application based on the following US application. No. 60 / 084,706, Brown et al., "Programmable packet switch" (19
No. 60 / 105,823, Brown et al., "Digital communications processor"
(Filed October 27, 1998). DESCRIPTION OF THE PREFERRED EMBODIMENT The following detailed description is directed to a digital communication system including a digital communication processor of the present invention.
Begin with an overview of the structure and operation of the packet switch, followed by digital communications
Outlines the structure and operation of the processor, and then describes the digital communication processor
The details of the structure and operation of the components are described. Digital Packet Switch Including Digital Communication Processor: FIG. 2 FIG. 2 is a block diagram of the packet switch 201. Packet switch
201 is a digital communication processor for realizing the digital communication processor of the present invention.
It is constructed using the power integrated circuit 203. The integrated circuit 201 has the following external devices.
With an interface for: up to 16 to 2 for packets sent or received by the transport protocol
05 (0 ... 15) serial input 204 and serial output 206; 32 bit output and 32 bit input from optional digital switching device
(Interface 221)-PCI bus interface 225 with optional host processor 227
A 128-bit wide interface 228 with the SDRAM buffer memory 229; a 64-bit wide interface with the SRAM conversion table memory 207; and a 32-bit wide interface with the queue memory 213; More specifically regarding these interfaces, the digital communication process
The processor 203 connects the serial inputs and outputs in a single DCP 203 to many different media.
Programmed to be used for body and transport protocols
You. When the network in which the DCP 203 is used is changed, the DCP 203
Reprogrammed to handle the different network configurations. Fast protocol is
, Connect some serial input or output to transmission medium for high speed protocol
It is dealt with by. In the preferred embodiment, media and transport protocols
Includes: 10 Mb Ethernet; 100 Mb Ethernet; 1 Gb Ethernet; T1 / E1 interface; T3 / E3 interface; OC-3c interface; and OC-12c interface. DCP 203 receives a media packet at input 204 and receives a media packet from output 206.
Output body packet. Media packets are received on input 204 and transmitted on output 206
What happens in the interim is how the DCP is programmed
Is determined by The methods by which the DCP 203 can be programmed include:
There are: each input has a receiving processor, and each output has a transmitting processor. these
The processor has different types of media packets, transport packets and transport packets.
Independently programmed to address the packet that is the payload; the input and output are integrated; the state behavior associated with the stream of packets can be programmed
Examples include address translation and error correction code processing; the ability to program the source and destination relationships of packets in the DCP
The information transmitted from the packet source to the packet destination is interpreted by the destination;
Can be programmed as For a typical packet switching application, DCP 203 operates as follows.
Be programmed. As each media packet is received at input 204,
DCP 203 stores data from the payload of the media packet in buffer memory 229.
Is stored in the buffer 231 in the file. This stored data is used here for protocol data
Data unit or PDU (protocol data unit). PDUs are often
, A transport packet that is part of the payload of the media packet. The media packet is
When output, the DCP 203 retrieves the PDU from the buffer 231 and makes the necessary changes.
(For example, changing the delivery information in the transport packet or changing the type of transport packet)
), Add protocol data for media packets. The DCP 203 uses the conversion table 209 in the conversion table memory 207 to
Deliver transport packets and higher level packets. Packets delivered
The DCP 203, the descriptor for the buffer 231 containing the PDU for the packet
217 is a queue in the queue memory 213 for the output 206 from which the packet is output.
Put at the end of 215. In general, each queue 215 is associated with one output 206
May put the packet received at input 204 at the end of any queue 215
Therefore, packets received at an input 204 are transmitted through a plurality of outputs 206.
Can be output. Packets may be multicast. Sand
That is, it is put in two or more queues 215. DCP 203 relates to output 206
Takes the descriptor 217 from the front of the queue and places it in the buffer identified by the descriptor.
231 is output to the queue output 206. The DCP 203 receives packets from any digital switching organization, as shown at 221.
It can also receive packet data and provide it with packet data. Switching group
The fabric may be another packet switch, such as packet switch 201,
Or any other device capable of delivering a stream of digital data.
It can be a device. For example, the packet switch 201 is connected to the crossbar switch.
It can also be connected to switches or other packet switches for the bus. I
Received from the interface 221 or output to the interface 221.
The delivery of the packet data is basically received at the serial input 204.
This is as described above with respect to the packet to be transmitted. Finally, DCP203 is PCI bus 2
25, receive data from the optional host 227 and send a packet
・ Send data. The external control interface includes a GPIO interface 223 and a PCI bus interface.
And a face 225. The GPIO interface 223 includes an LED and a nonvolatile memory.
External systems such as memory, physical layer serial transmit and receive components and power supplies.
Utility interface for monitoring and controlling system elements. PCI bus
The interface 225 controls the DCP 203 and the switching system 201, and
Advanced level such as access check of packet contents received by
Communication with a host processor that also performs the operations of the Detailed Example of Operation Using the example of the description of the related art, the components of the packet switch 201
Describes in more detail how it is programmed to deliver packets.
I will tell. As an example, the serial input 204 (i) of the serial pair 205 (i) is
A stream of SONET packets with a stream of ATM transport packets as the payload of the
Ream is being received. An ATM transport packet has an IP node as its payload.
109 (n), which is directed to the Ethernet LAN 105 (
On device 107 (n) attached to a). Ethernet LAN 105 (a)
, Serial pair 205 (j). packet
-Since the switch 201 is used to distribute IP packets, the DCP 203
For the payload, including the header of the P packet, on the serial input 204 (i)
It is programmed to scan incoming transport packets. IP packet header
If found, the DCP 203 buffers the payload from the ATM transport packet into a buffer
To the buffer 231 in the buffer memory 229 specified by the tag 233.
Start to work. If the IP packet is longer than the buffer, an additional buffer is adopted.
You. While the IP packet is being transferred to the buffer memory 229, the DCP 203
Process the information in the header of the packet to determine how to deliver the IP packet,
After that, the IP packet is delivered. Processing of the header information is performed in the conversion table memory 2
07 is performed using the conversion table. In this case, two conversions are performed. You
That is, the IP destination address in the header of the IP packet is changed to the IP having the destination address.
Must convert to the Ethernet address of device 107 (n) where the node is located
And the Ethernet address of the device 107 (n) is stored in the queue memory 213.
Must be converted to a queue identifier within. From there, the serial output 206
(J) outputs an Ethernet packet. One of these, the IP destination address
(IPA: IP destination address) to Ethernet address (ENA: Ethern
et address) into the conversion table
209 (a). The DCP 203 stores information from the header of the IP packet and the conversion table 209 (a).
Is used to create the descriptor 207 of the IP packet. This descriptor includes Ethernet
Address and the buffer tag 233 of the buffer 231 containing the packet
included. DCP 203 then outputs descriptor 207 from serial output 206 (j).
It is placed at the end 221 of the queue 215 (j) for packets to be output. descriptor
When 207 reaches the forefront of queue 215 (j), DCP 203 returns a buffer containing IPA.
The contents of the file 231 are extracted, and the contents are output with respect to the serial output 206 (j).
Stream the packets with the appropriate media protocol. These media packages
The packet has an Ethernet transport packet as its payload. Information description
Using the device 207, the DCP 203 converts the device 107 (
n) Ethernet address. Next, pay for the Ethernet transport packet.
The load is stored in the buffer specified by the buffer tag. The DCP 203 can, of course, perform the above operation or a variant thereof for up to 16 incoming calls.
Packet serial stream and 16 outgoing transport packet streams.
And at the same time, in some cases,
Data stream to and / or from a digital switch
Data stream between itself and external host 227 via interface 227
Note that it may be performed at the same time as the system is transferred. In addition,
In many cases, packet switching operations are subject to strict timing constraints, as described in
Is governed by As described in more detail below, the design of DCP 203
An important factor in the DCP 203 is that it is necessary for the types of operations described above.
By providing data paths and memory structures with high speed and latency characteristics
is there. DCP 203 Structure: FIGS. 3 and 5 FIG. 3 is a high-level block diagram of the internal structure of DCP 203. Shown in FIG.
2 are labeled with the reference numbers shown in FIG. Transport packet
Starting with the serial input and output 205 sent and received, each serial pair 205
, Connected to its own programmable channel processor 307. This professional
The processor 307 processes serial input from the pair and serial output to the pair. So
Therefore, in the preferred embodiment, there are 16 channel processors 307
I do. For very fast transport protocols, up to four channel channels
Coupling processor 307 into the channel processor cluster shown at 309
be able to. The organization processor 303 is similar to the channel processor, except that
Process parallel data received from source 221 and sent to interface 221
Is different. The table lookup engine 301 uses a conversion table
Address conversion is performed using a table in the memory 207. Queue management engine 3
05 manages a queue 215 of descriptors. In some embodiments, the queue is DCP IC
Queue memory 213 may be stored in a separate external memory
In some cases. The buffer management engine 315 has a buffer memory 229.
Manages the buffer 231 in the inside. The execution processor 313 includes other components.
Initialize and maintain the data in the PCI bus with the optional external host 227.
Interface and GPIO interface, and higher if necessary.
Perform level processing. The program and data of the execution processor 313 are stored in SDRA
It is stored in M229. Execution processor 313, channel processor 309 and
And organization processor 303, all of TLE 301, QME 305 and BME 314
To process packets and / or frames, and
Are collectively referred to as packet processors. But here, the packet
The processor processes not only packets but also any other stream of data.
General purpose bits / n bytes / byte / or (of tissue processor)
(If) can be considered a 32-bit word stream processor.
It should be noted that. All processing components of DCP 203 are programmable. H
The channel processor 307 has different types of media packets, transport packets and
Can be individually programmed to handle transport packet payloads
, Tissue processor 303 to process data employed by different switching devices
Can be programmed. Do not write the table in the table storage unit 207.
And the table lookup engine 301
It is programmed to perform different types of lookups. Queuing pipe
The engine 305 sets up a different number of queues and stores different sizes of queues in the queues.
The buffer management engine 315 can be programmed to use a predicate.
Buffers pools of different sizes to different buffer sizes in the pool
Is programmed as Finally, XP313 is a general purpose processor,
Can be programmed to perform the functions of Component Pro
Grams are loaded when DCP 203 is initialized. The program code is
Loaded into SDRAM 229 by external host 227 or stored in BME 315
It is stored in an external PROM that is part of the address space managed by the user. Any place
Again, XP 313 loads the code into the component's memory. Due to the bus and memory structure of the digital communication processor 203, the DCP 203
Are the table lookup engine 301, the queue management engine 305, and
Packet switching speed while employing the buffer management engine 315 as a shared resource.
Degree and time constraints can be satisfied. Table lookup
All components of the digital communication processor 203 except the engine 301
Shares one global address space 321. Each packet process
Has its own local memory in the global address space 321;
Other packets whose local memory belongs to the global address space 321
The local memory of the processor and the memory belonging to the BME 315 and QME 305
Mori can also be accessed. Each packet processor has its own local
Access directly to the local memory of other components.
Are accessible via a 32-bit global bus 319. Ma
In addition, the organization processor 303 has a unique route 3 for the queue management engine 305.
04. FIG. 5 shows an outline of the global address space 321. First, the channel
Global memory consisting of the local memory 501 of the processor 307 (0 ... 15)
There is a portion 504 of the address space. Portion 504 includes each channel processor channel.
It is further subdivided into a cluster memory 503 for the raster 309. Specific cha
The channel processor 307 (i) accesses its local memory 501 (i)
The fastest access can be performed, and the
Next fastest access to local memory of other channel processors in the cluster.
Access to the rest of the global address space 321
Even do slow access. The local memory is in the global address space 32
Other components that are part of one have their local memory shown at 505.
Organization processor 303 and QME 30 whose local memory is shown at 507
5, the BME 315 whose local memory is shown at 513, and its local memory.
The memory is the QME 305 shown at 517. Share global address space
Processors generally use global addresses for communication between the processors.
Space can be used. For example, processors coordinate their operations.
To set up signals (semaphores) in the global address space to
Can be. In order to create and use such signals, the preferred embodiment
Some processors have a bit-test-and-set-bit instruction. The
Other information available in the global address space includes the QME local memory 5
07, the queue status information 505, the buffer management engine local memory 51
3 and the system setting in the XP local memory 517.
There is a constant register 519 and system interface setting information 521. last
In addition, the QME 305 has a queue state for the queue read by the packet processor.
Write the status information to the local memory of the packet processor. With further reference to FIG. 3, each of the component's local memories contains
A bus 317 is coupled to the buffer management engine 315. This is 4
Operates in a cycle burst and stores up to 64 bytes of data to SDRAM 229 and other
Is a 128-bit wide bus for transferring data to and from a component. Payload bar
The data transferred via the data processor 317 includes:-programs and data used by the execution processor 313;-data used by the execution processor 313 to set the DCP 203;-SDRAM 229 and the packet processor. Protocol data transferred during
A unit; a buffer tag 233; and a descriptor queued by the packet processor and retrieved therefrom.
. The transfer between the SDRAM 229 and the local memory is performed by direct memory access (DMA
: Direct memory access) mechanism. Component that performs the transfer
Gives a DMA instruction for transfer to the DMA mechanism, and the DMA mechanism
Perform the transfer without further intervention from the component. With this structure, professional
Parallel transfer of protocol data units and other processing by components
The operation speed and the processing capacity of the DCP 203 can be greatly improved. The lookup engine 301 and the packet processor are all ring processors.
It is connected via a bus 311. Ring bus 311 is 64 bits wide,
Are time-multiplexed between connected nodes. At any one moment, these components
Each of the components is assigned one to five bus slots. Each
Lots can carry 64-bit messages. The bus is between its nodes
Since each node has a predetermined maximum number of slots, the message
Is reliably transferred from one node on the ring bus 311 to another node within a certain period of time.
You can move. In the preferred embodiment, execution processor 313
The table in the table storage unit 207 is set and
The packet processor uses ring bus messages to modify
Information to the table lookup engine 301 for
Lookup engine 301 uses the ring bus message to convert and
Send the result to the packet processor. All devices coupled to the ring bus 311
The ring bus 311 to any other device coupled to the ring bus 311.
In another embodiment, the ring bus
The message is passed, for example, to channel processor 3 comprising cluster 309
07 can be used to adjust the operation. Example of Cooperation of Components of DCP 203 Continuing with the example of FIGS. 1 and 2 at the level of detail indicated by FIG.
In response, a stream of ATM packets is received on input line 204 (i). input
Line 204 (i) belongs to channel processor 307 (i). ATM packets
Arrives, the channel processor 307 (i) starts a series of DMA transfers,
First, send the packet to the local memory of the channel processor 307 (i),
Next, in the buffer tag 233 owned by the channel processor 307 (i),
Therefore, the data is transferred to the designated buffer 231. While this is in progress, the channel
The processor 307 (i) scans the payload of the ATM packet for an IP packet
I do. Upon finding the beginning of an IP packet, the channel processor 307 (i)
Extract destination address of IP packet from IP packet header and look up table
Create a message containing the destination address for the up engine 301. This
, The destination address is the device 10 connected to the Ethernet LAN 105 (a).
7 (n) is designated as the IP node 109 (n). Ethernet LAN 105 (a)
Receives the packet output from serial output 206 (j). Channel processor
The server 307 (i) then sends a message to one of the slots in the ring bus 311.
Insert Channel processor 307 (i) communicates with Ethernet of device 107 (n).
Address and the number m of the queue to which the serial output 206 (j) corresponds.
Upon receiving a reply to the message, at least the Ethernet address and
Create a descriptor 217 (k) containing the buffer tag 233 of the buffer. next
, Channel processor 307 (i)
The queue command is transferred to the mailbox belonging to the channel processor 307 (i).
Write to The enqueue command includes at least a descriptor 217 (k) and a wait
Matrix number m. The queue management engine 305 stores the descriptor 217 (k)
Respond to the command by placing it at the end 221 of the queue 215 (m). The serial output 206 (j) belongs to the channel processor 306 (j) and waits
Queue management engine 305 determines whether queue 215 (m) is at the forefront 219
Gives the descriptor. The processor communicates with the queue 21 via the payload bus 317.
Writing a dequeue command specifying 5 (m) to that mailbox
Do this more. The queue management engine 305 is located at the front of the queue 215 (m).
The descriptor 217 in the section 219 is transferred to the channel processor via the payload bus 317.
Responds to a dequeue command by giving it to the processor 307 (j). After all, the descriptor 217 at the forefront 219 of the queue 215 (m) is the descriptor 217
(K). Channel processor 307 (j) has descriptor 217 (k)
Then, using the buffer tag 233 in the descriptor 217 (k), the IP packet is
From the containing buffer to the local memory of channel processor 307 (j).
Starts DMA transfer of IP packets. When an IP packet arrives, the channel
The processor 307 (j) has an address addressed to the Ethernet device 107 (n).
Creates a stream of Ethernet transport packets and associates the IP packet with its payload.
And a stream of Ethernet packets on serial output 206 (j).
Output. The Ethernet address in the packet is, of course, the descriptor 217 (k
). Advantages of DCP 203 Bus and Memory Architecture As will be apparent from the above description, DCP 203 bus and memory architecture
Depending on the architecture, the packet processor can handle packet headers,
-Data unit transfer and enqueue and dequeue operations can be performed in parallel.
Can be. In addition, different buses not only have different paths,
Satisfies the latency requirements of the operations performed. For this reason, the most time-sensitive
Operation is the conversion of information in the packet header. This is the result of the conversion is obtained
Distribution cannot be performed until the Each of the packet processors
Each slot processor has a slot in the ring bus 311 so that
Accessing the table lookup engine 301 within a proven time
As a result, the time constraint of the conversion is satisfied. On the other hand, protocol data between the packet processor and the SDRAM 229
Unit transfers include high-bandwidth bursts, or more precisely, local memory
Provided by DMA transfer to and from SDRAM 229 via payload bus 317
A burst is required. Buffer management engine 315 and channel processor
Transfer of the buffer tag from the server 307 (i);
Transfer of descriptors to / from the channel processor 307 (i) is also strict in time
Therefore, these operations are also performed on the payload bus 317. Operations with less time constraints such as reading and writing are performed in the global address space 321.
Can be done with The time required for such reading and writing depends on the global address.
It is determined by whether or not it is in the space. The global address of a particular processor itself
Identify that reading and writing to the part of the source space takes the shortest time and the second
Read / write to processors belonging to the cluster 309 of
Read and write to processors that do not belong to the fixed processor cluster 309 are the most
take time. All of the processors of the DCP 203 except the TLE 301 have a global address space.
Sharing the H.321 facilitates communication between the processors. For example,
Row processor 313 stores data in that portion of global address space 321.
Initialize and / or reconfigure other components by writing
The packet processor 307 is managed by the queue management engine 305.
Queue 215 and the buffer 2 managed by the buffer management engine 315
31 or status of other packet processors in cluster 309
Status information from the part of the global address space belonging to these devices.
The processor group has a global address space
Signals within can regulate that behavior. Receive packet
The processor may also take advantage of the global address space in some applications.
And the protocol data output by the protocol data unit it receives
Can be written directly to the local memory of the sending packet processor.
Wear. The execution processor 313 eventually uses the global address space
In this case, the execution processor 313 controls each processor sharing the global address space.
The situation of Sessa can be judged. When operations in the global address space are performed very frequently, a dedicated hardware
Hardware support is provided. For example, the organization processor 303 may
Dedicated access to the global address space of the engine 305.
To obtain queuing status information without burdening global bus 319
Can be. Similarly, each packet processor has a global address space
In the part there are status bits for the mailbox of the QME 305 and these bits
Since the packet is routed directly to the queue management engine 305, each packet processor
The security officer checks the status of the mailbox without burdening the global bus 319.
Can be turned off. Packet Processor Details The next section describes the channel processors 307 (0 ... n) in detail.
Next, the organization processor 303 and finally the execution processor 313 will be described. Overview of Channel Processor 307 (i): FIGS. 4 and 6 FIG. 4 is a block diagram of components of the channel processor 307 (i).
is there. As shown in FIG. 3, the channel processor 307 (i)
A serial packet input is received via input 204 (i) and serial output 20 is received.
6 (i) and sends the serial packet output to the ring bus 311.
And has a slot therein, and the payload bus 317 and the global bus 31
9 is connected. Integration routes 433 and 435 and cluster routes 437 and 439
Thus, the channel processor 307 (i) can use other channels in the cluster 309
Integrated with the processor 307 to handle very fast transmission media.
it can. At a high level, the channel processor 307 (i) has three components
Have a global address that controls the operation of other components.
Channel processor, which is a general-purpose processor capable of accessing the
A channel processor risc core (CPRC) 401 and a serial processor
The packet is received from the serial input 204 (i) and is sent to the serial output 206 (i).
Serial data processor (SDP: serial
data processor) 420, channel processor 307 (i) and BME 315
D which handles data transfer to / from the QME 305 via the global bus 317.
The MA engine 411. Both SDP 420 and CP RISC core 401
It is connected to the ring bus 311 via the bus interface 415. S
DP 420 has two sub-components:
An RxSDP 421 for processing and a TxSDP 427 for processing outgoing packets. Next, the details of the CPRC 401 will be described. The CPRC 401 is a well-known MIPS1 instruction set.
A general-purpose microprocessor that employs a subset. CPRC 401 is a ring
Messages can be sent and received on the SDP 420, the SDP 420 and two registers
・ Share files. Using the extract space 417, the incoming packet is
The protocol data extracted from the protocol is stored and used by the CPRC 401.
On the other hand, the protocol sent to the SDP 420 by the CPRC 401 using the merged space 419
The col data is stored and used for creating an outgoing packet. The CPRC has four contexts, an independent set of register files.
is there. The CPRC 401 responds to a break (BREAK) command in the program,
Alternatively, it can switch between contexts in response to a hardware interrupt.
The context is prioritized by the highest priority number from 0 to 3
The ranking is given. Each context has a context entry register and a context.
And a text return register. When the context changes, the current
The address of the next instruction executed in the context is the context of the current context
-Context entry of new context stored in return register
Execution proceeds according to the instruction at the address stored in the re-register. There are five system events that cause a context switch: • Master reset • Masking disabled interrupt • Debug interrupt • User interrupt 1 • User interrupt 2 Context related to master reset event and debug interrupt event・
The entry register settings are system defined. For other events,
It can be programmed. The instruction memory 403 includes a code executed by the CPRC 401. This code
The CPRC 401 and the CPRCs of the other CPs 307 in the cluster 309 to which the CP 307 (i) belongs.
Read and write only by In the preferred embodiment, the code is IM
Loaded in EM403. First, the execution processor 313 sets the global bus 3
19, the code is loaded into DMEM 407, and then CPRC 401
The data is transferred from the EM 407 to the IMEM 403. The DMEM 405 stores the local data memo of the channel processor 307 (i).
Ri. This is due to local storage by CPRC 401 and payload bus 413
Used for both DMA processing of data through DMEM405, excerpt space 417
And the merged space 419 are all part of the global address space 321;
Other channel processors in cluster 309 of channel processor 307 (i)
307 and other processors in the DCP 203 via the global bus 317.
Can be accessed. DMEM implementing this structure in preferred embodiment
The memory components added to 405 include a request FIFO 407, a MUX 407, and a global
Global bus interface 413 and payload bus interface
411. The MUX 407 is composed of RxSDP421, TxSDP427, payload bus
Access to DMEM 405 between interface 411 and request FIFO 406
Are multiplexed. Request FIFO 406 is CCP2 coupled to global bus 319.
03 accesses the DMEM 405, the CPRC 401
Access to DM 405 and global address space 321;
The other CPRC 401 of the channel processor 307 in the cluster 309 of FIG.
Enables access to DMEM 405. MUX 407, DMEM 405 and
The erase bus interface 411 together constitute the DMA engine 441,
This is the payload bus 317 between the SRAM 229 and the CPRC 405 and the SDP 420.
Execute DMA operation via. As shown in the above structure, RxDSP 421, TxSDP 427 and payload bus
The interface 411 has the first priority of access to the DMEM 411
, Global bus interface 413, CPRC 401 and other CPRC 401
Must compete for the remaining access rights. For this reason, this structure
On the one hand, between the SDP 420 and the DMEM 405, and, on the other hand, the DMEM 405 and the SDRAM 22.
The first priority is given to the DMA transfer of the protocol data unit between 9 and 9. The details of the components of the serial data processor 420 are further described
Then, the RxSDP 421 specializes in processing the stream of the incoming packet. RxSDP42
1 extracts the field containing the protocol data from the incoming stream,
The contents of the field are transferred to the ring bus 31 via the ring bus interface 413.
1 or via the excerpt space 417 to the CPRC 401. Also via DMA transfer
To provide the protocol data unit from the packet stream to DMEM 405
I can. RxDSP 421 has three subcomponents. That is, the transmission medium
A pin logic 443 for receiving a physical signal representing a packet stream within the body;
Framing to place media packets and transport packets in the packet stream
An assist processor 407 and protocol information from the transport packet and its payload.
Information, and transmit a transfer packet to the DMEM 405 via the path 425.
453 processor. The byte processor 453 has the extract space 417
The extracted protocol information can be placed in the
Placing ring bus messages via bus interface 415
Can be. TxSDP 427 is a protocol that TxSDP 427 obtains from DMEM 405 via DMA.
Specializing in the generation of streams of outgoing transport packets carrying digital data units
. For this purpose, the TxSDP 427 uses the protocol that the CPRC 401 puts into the merged space 419.
Merge col data into protocol data units. TxSDP427
The components are functionally equivalent to the components of the RxSDP 421. others
For this reason, the byte processor 453 checks the transport packet and the protocol in its payload.
Manipulates data and framing support processor 449 needs media packets
And the pin logic 445 outputs the data and the data is output.
In the format required by the physical medium being used. Another interesting feature of SDP 420 is that recirculation path 441 and integration path 433,
435. The recirculation path 441 transmits the packet stored in the DMEM 405 to RxSDP
Returning to step 421, further processing is performed and output to the DMEM 405 is enabled. Sum
The path 433 is a state where all the RxDSPs 421 in the cluster 309 share the same input data.
In order to enable reception, the integrated path 435 belongs to TxSDP 427 to which CP 307 (i) belongs.
You can receive data about the output from TxSDP in other CPs 307 of the cluster.
To do. Operation example of channel processor 307: FIG. 25 FIG. 25 shows how the receiving-side channel processor 307 (i)
In cooperation with the channel processor 307 (j).
media path containing a sequence of transport packets at input 204 (i) belonging to i).
Receive a stream of packets and its payload is
Sender channel processor 307 which is the transport packet received in i)
A medium comprising a sequence of transport packets at output 206 (j) belonging to (j)
Indicates whether a sequence of packets can be output. Medium to be received and transmitted
The body packet and the transport packet belong to different protocols, of course. The received medium packet is sent to the RxSDP 421 of the channel processor 307 (i).
Received. RxSDP 421 uses the transport packet and its payload to
The col data is extracted to the extraction space 417, and the DMEM 405 and the payload bus are extracted.
The protocol data unit consisting of the transport packet via 317 is transmitted to the BME 31
5 is DMA-processed. The BME 315 transfers this protocol data unit to SDRAM2
29 buffer 231. Protocol data unit is shown in 2503
Is done. On the other hand, the CPRC 401 in the channel processor 307 (i)
The descriptor 217 is created using the col data. Next, CPRC 401 pays this
Transfer to QME 305 via load bus 317 and queue. (Prototype
A part of the col data is transmitted to the TLE 301 via the ring bus 311 for transmission.
Note that the appearance is not shown in this figure. ) CPRC 401 put in queue
When the CPRC 401 sends the power descriptor 217, the CPRC 401 sends the
Put it at the end of the queue 215 read by Sessa 307 (j)
Specify that The QME 305 stores the descriptor 21 at the end of the designated queue 215.
Insert 7. The channel processor 307 (j) starts the descriptor 207 from the front of the queue 215.
, The QME 305 passes it over the payload bus 317 to the channel
It is sent to the processor 307 (j). Channel processor 307 (j)
Using the predicate 217, a protocol relating to a stream of output packets
Data is created, and the protocol data is entered into the merge space 419. Next,
The buffer 23 in the SDRAM 229 via the erase bus 317 and the DMEM 405
1 to Protocol Data Unit to Serial Data Processor 420
Start the DMA operation to transfer. Here, TxSDP 427 is a protocol data unit.
Output 20 conveying unit 2503 from the packet received at 204 (i)
Necessary to create a stream of media packets 2505 for 6 (j).
Add protocol data. Details of Local Memory 501: FIG. 6 FIG. 6 shows the local memory 501 for the channel processor 307 (i).
(I) is shown. As described above, all of the local memory 501 (i)
Of the digital communication processor 203 sharing the global address space 321
Can be read and written by all components. Data Scope 625 (0) and 625 (1) As described above, the RxSDP 421 transmits the incoming packet stream to the SDRAM 229 by DM.
A process and perform protocol data from incoming packet streams
And sends it to the CPRC 401 for processing. On the other hand, TxSDP427 is SDRAM
The outgoing protocol data unit is received from the H.229 and the CPRC 401
Receive the protocol data and send it to the appropriate
Put in place. For one transport packet, the process involves two stages. Incoming call
In the case of a packet, it is the following stages: Extract protocol data and transfer protocol data unit to SDRAM 229
And the protocol data is processed by the CPRC 401. In channel processor 307, these two stages are pipelined.
You. For an incoming packet stream, CPRC 401 contains the previous protocol data
Processes the protocol data extracted from the unit, but the RxSDP421
Extracting protocol data from the packet stream
DMA the current protocol data unit from the system. Send in the same way
Processed, TxSDP 427 DMAs the current protocol data unit,
RC 401 converts the protocol data contained in the next protocol data unit
To process. The pipeline processing can be performed by the data scopes 625 (0) and 625 (1).
It will work. These are data structures that are visible and accessible from CPRC 401
, SDP 420 and the interaction between CPRC 401 and SDP 420. Ah
The data scope 625 (i) has a collection of data scope registers 624.
And a set of flags 632 (i) of the data scope event register 632.
Is included. The data scope register 624 further stores the Tx data
Loop 641 and an Rx data scope 643. Rx data scope 643
Is extracted by the RxSDP 421 from the incoming packet stream during the first stage
CPRC 401 receives the protocol data in the second stage.
Process on the floor. Similarly, the Tx data scope 643 indicates that the CPRC 401 is
Receives the processed protocol data for the outgoing packet stream at Tx
SDP 427 sends protocol data from Tx data scope 643 during the second phase
Is output. In addition to enabling packet processing to be pipelined, data scope 6
25 is currently received by Rx 421 of SDP on CPRC 401, or
The running program for the stream of packets being sent by xSDP 427
Provides a uniform interface for RAM. Stream needs further processing
In some applications, the number of data scopes can be increased. For example, wear
Processing of communication stream, storing of PDUs derived from it in DMEM 405, recirculation path
Reprocessing of the PDU stored in the DMEM 405 using the 441 and the final PDU
RxSDP processing including DMA processing to RAM 229 includes four data scopes.
Can be The program to be executed on the CPRC 401 currently determines which data
Determine if a co-op is being used. The SPD 420 has the data scope 625 (
Extract protocol data from 9) and merge protocol data with it
Meanwhile, the CPRC 401 processes the protocol data with the data scope 621 (1).
You. When the SDP 420 terminates the data scope 625 (0), the data scope is sent to the CPRC 401.
The CPRC 401 informs the SDP 420 that the data scope 625 (1)
Prepare the data scope 625 (1) so that you can start
The operation in the loop 621 (0) is started. The contents of the data scope 625 (i) will be described in more detail.
The data scope 643 is an abstract including the protocol information extracted by the RxSDP 601.
The packet received by the RxSDP 421 is transferred to the smart register 601 and the SDRAM 229 by the DMA.
The RxCB 633 containing the information necessary for processing and the RxSDP 421
Rx status including status information about RxSDP421, including whether DMA
Status 635. Tx data scope 641 is similar for packet transmission
Register. The merge register 603 stores the protocol to be merged with the outgoing packet.
TxCB633 is the packet transmitted from the SDRAM 229 by TxSDP.
Tx status contains information necessary for DMA processing of the packet, and the Tx SDP 427
It includes status information on TxSDP 427, including whether or not processing has been completed. Control block register 611 The control block register 611 controls the DMA transfer between the CPRC 401 and the SDRAM 229.
Is a set of four registers that control. WrCB610 is from CPRC401 to SDRAM2
RdCB controls the DMA transfer to the CPRC 401. Ring bus control registers 617 These registers are part of the ring bus interface 415. This
With these registers, RxSDP421 and CPRC401 send messages on the ring bus.
The CPRC 401 sends a message on this ring bus.
Can be received. 4 registers for sending messages and CP307 (
8 registers for receiving replies to the message sent by i)
And one queue of registers for receiving spontaneous messages. SONET overhead bit 612 This register contains the SON for the SONET packet output by CP 307 (i).
Includes ET overhead bit. RxSDP control 613 and TxSDP control 615 These registers control the operation of RxSDP 421 and TxSDP 427, respectively.
Including parameters. CP Mode Register 625 This register contains parameters that control the operation of CP 307 (i). SDP Mode Register 627 This register contains parameters that control the operation of SDP 420. Queue status 621 The queue status 621 indicates the status of the channel processor 307 (i) in the QME 305.
Read by the channel processor 307 (i)
Contains information about queue status. Channel processor 307 (i)
The hardware for the registers that indicate the status of the
Directly controlled. Therefore, the global bus 31 is read and written by the register.
No traffic will occur on 9. QME305 is a channel processor
The status of the queue read by the server 307 (i) is transmitted via the payload bus 317.
Then, DMA processing is performed on the DMEM 405. Event Timer 620 This register is set and started by software running in CPRC 401.
Includes event timer that is activated. When the timer expires, the RC 401
An event occurs to which the vent mechanism responds. Cycle Counter Register 619 The cycle counter register 619 stores a counter value, a clock division value,
Includes CC enable bit. The CPRC 401 has a counter value, a clock division value,
And the CC enable bit can be set. The clock division value is CPRC40
Specifies the rate at which the counter value increases relative to one clock. CPRC 401 is CC
Setting the enable bit starts the counter. CPRC401 is CC rice
Clearing the table bit stops the counter from running. The current counter value is
Unaffected by setting or clearing the CC enable bit. Event Register 631 This register is used to generate asynchronous events to which the CPRC 401 must respond.
Contains a flag indicating whether the There are two types of events:
The general event whose lag is in register 630 and its flag
Event related to data scope 625 in loop event register 632
It is an event. CPRC 401, along with all the registers described, has its local data
The data in the memory 405 can be accessed, and the SDRAM 229 and the local memory
Local memory between data memory 405 and SDP and SDRAM 229
Via 405, a DMA transfer can be set as described above. Details of an example of cooperation between the CPRC 401, the RxSDP 421, and the TxSDP 427: FIGS. 7 to 97 Stored in the memory interface between the RISC core and the SDP FIG.
How they can be programmed to interact when
Show. The flowchart 701 not only shows the operations performed, but also the RxSDP 421, CPRC
It indicates which of 401 and QME 305 performs the operation. Start at 703
The incoming packet is read by the RxSDP 421 (705). RxSDP421
What to do with what you read depends on the position of the material in the packet. Rx
There are three types of information that the SDP 421 must process. That is, the protocol
Data units and protocols that must be converted by TLE301
Information and protocol information that must be converted by the CPRC 401. Bob
As shown in the box 707, the RxSDP 421 uses the DMA to transmit protocol data.
When a unit is read, it is transferred to the SDRAM 229 via the DMEM 405. 7
09, the RxSDP 421 utilizes the ring bus 311 to
1 sends a message to TLE 301 with the protocol information
Attached. Finally, as shown in 711, the RxSDP 421 uses the excerpt space 601
Then, the information that the CPRC 401 needs to process the protocol information is transferred to the CPRC 401.
Send. In block 713, the CPRC 401 determines whether the information received from the RxSDP 421
Using the response received from the TLE 301 in response to the message of xSDP421,
Decide what to do with the transport packet. If the content has been destroyed,
Or the payload comes from a source that was dropped by the packet switch
Or the transport packet is invalid for any reason, the CPRC 401
Marks the packet and discards it. Mark (tray added during DMA
In response, the DMA engine stops transmitting and the BME 315
The buffer 231 receiving the packet is released. If the transport packet is valid, the CPRC 401 checks the information received from the TLE 301
Utilizing the information in the extraction space 601, the protocol / data
Determine the queue 215 for inserting the knit and create the descriptor 217 for the queue
I do. Next, at 751, the descriptor and the protocol data unit are
An enqueue command including the number of queues to be put on the bus 317
. The QME 305 places the descriptor 217 in the appropriate queue 215 to
Respond to queue commands. As shown in boxes 717, 719, 721
There are three broad ranges of queues depending on the components of the DCP 203 that read the queues.
There is a matrix. That is, the queue read by the XP processor 313 and the channel
A queue read by the processor 307 and a queue read by the organization processor 303
Column. For queues read by XP processor 313, corresponds to descriptor
The protocol data unit to go to host 227. Tissue processor 3
03, the protocol data corresponding to the descriptor
The unit proceeds to the switching organization. Here, RxSDP 421, CPRC 401 and QME 305 all operate independently.
Processor, the processing shown in the flowchart 701 can be performed in parallel.
Note that The pipeline between RxSDP421 and CPRC401 has already been
Explained. In addition, the CPME 401 determines that the QME 305
No need to wait for a response to a command. Role of Data Scope 625 in Interaction of CPRC 401 and RxSDP 421
FIG. 9 shows details of the reception data scope 643 in order to explain
You. Rx status register 6 indicating the status of the interaction between RxSDP 421 and CPRC 401
Start with 35. The register has four target fields. OWN field 9
35 is set by hardware. Bit is RxSDP421 or CPRC40
Either one uses the data scope 625 to which the Rx status 635 currently belongs
To indicate that L5: L0 937 is used to control RxSDP421 and CPRC40 under program control.
Six handshake bits set and reset by one.
Busy 941 is set by RxSDP 941, and RxSDP 421 is currently busy (used
Medium). The Tx status 639 has the same functions and contents as the Rx status 635.
You. The RxCB 633 and the RxSDP 421 and the DMA engine 441 during the DMA processing of the incoming packet
Governs the interaction between CPRC401 is the data score to which RxCB633 belongs.
RxCB 633 is set when owning group 625 (i), and RxSDP 421 sets RxCB6
33, the RxSDP 421 and the CPRC 401 are connected to the data scope 625 (i).
Continue DMA processing of incoming packets while changing ownership. Fee in RxCB633
Most of the fields contain various addressing information needed to perform DMA.
Information is included. Buffer pool number 909, BTAG 933 and offset 93
1 both write the packet that the DMA engine 441 is currently receiving by the RxSDP 421.
The position in the DRAM 229 to which data is written is specified. As described in more detail below, DRAM 229 is divided into buffer pools.
It is. BTAG 933 is a buffer tag 233 for buffers in the pool.
Offset 931 is the offset in the buffer where the data is currently written.
It is. When the DMA engine 441 writes data, the offset 931 is updated.
You. The DMEM DMA address 907 indicates that the DMA engine 411 is currently performing DMA processing on the DRAM 229.
This is the address of the 16-byte line of the data in the DMEM 405. Txrcy address
Address 903 and the Rxrcy address 903, the RxSDP 421 recirculates data from the DMEM 405.
This is a special address used for looping. Txrcy address 905 is TxSDP427
DMEM 405 line to which data is currently written by the DMA engine 441
Rxrcy address 903 indicates that RxSDP 421 is currently writing data.
Specify DMEM405 line. Therefore, the RxSDP421 uses these addresses to perform SDR
Before writing to AM 229 or after writing to SDRAM 229,
Can be circulated. RxSDP421 is the DMEM byte address 901
This is a line in the DMEM 405 where data is written. The RxDBCTL 913 is provided between the CPRC 401, the RxSDP 421, and the DMA engine 441.
Includes control and status fields governing the interaction: Avail 929 indicates whether RxCB 633 is available; NR 927 indicates data to DRAM 229 before
Indicates the number of requests to transfer the data; Error 925 indicates an error during the transfer currently represented by RxCB 933
Indicates whether or not an ODD has occurred; Own (ownership) 921 is written by RxSDP 421 and read by DMA engine 411
If the line in M405 is currently being written by RxSDP 421 or DMA
EOP917 indicates that the RxSDP 421 is a packet in the data written to the line in the DMEM 405.
Set by RxSDP 421 when the end point of the set indicator is encountered; ST 915 is the current status of SDP 420; BCTL status 919 is the current status of payload bus 317; and length 911. Is set by the RxSDP 421. This is written by RxSDP421
This is the data length of the line in the DMEM 405 that is running. The TxCB 637 is substantially similar to the RxCB 633, except that the DMA transfer
Proceeds in the opposite direction, and the fields have a meaning corresponding to that direction. Rx SDP 421 sets OWN bit 935, L2 Done 937 or L1 done 939 to Rx status
Setting the Avail bit 929 in the register 636 or the RxCB 633 results in
As a result, an interrupt to the CPRC 401 occurs. Which action caused the interrupt depends on Rx
Data scope entry for the scope that exists when SDP sets the bit.
Indicated by a bit in vent register 632. The same structure is used for Tx data
It is also used for the corresponding bits in the scope 641. First, the CPRC 401 sets the data scope 625 and gives the RxSDP 421 the ownership
give. CPRC 401 now owns data scope 625 (1). Pa
When a packet comes, RxSDP421 extracts the protocol data and extracts it
Write to register 601 (0). RxSDP421 is a protocol that requires conversion.
Sends a message including data to TLE301 in Txmsg 645 (0)
You. The collation result appears in the RxResp register 747 (0, i). While this is going on
, RxSDP421 is the protocol to the line in DMEM405 designated to RxCB633 (0).
Start writing the data unit. When the entire line is received, RxSDP4
21 sets the owner bit 935 to the Rx status 635 and the CPRC 401
Data scope 625 and the owner bit 9 in RxCB 633 (0).
Set 21 to indicate that the DMA engine 411 is reading the line that was written
To automatically switch RxSDP421 to data scope 910 (1)
To achieve. The RxSDP 421 then uses the data scope 625 (1) owner bit
Verify 935 to see if CPRC 401 still has that control
You. If the CPRC 401 has control, the RxSDP 421 transmits the next packet to the CPRC 401.
Wait until control of data scope 625 (1) is relinquished before starting processing
I do. Processing is performed by the RxSDP 421 instead of the data scope 625 (0).
Same as above except that the resources of scope 625 (1) are used. While the RxSDP 421 continues to work with the received data scope 625 (1), the CPRC
401 processes the received data scope 625 (0). CPRC401 is RxSDP
421 verifies and verifies the protocol data entered in the excerpt space register 601 (9).
And / or remove, verify RxCB633 and error in DMA processing on SDRAM 229
It is determined whether or not the processing has been completed without causing the RxSDP 421 to be used by the RxSDP 421 for the next use.
33 (0) is set. Next, the program that RxSDP421 put into the extract register 601
Protocol data and a variable received from the TLE 301 in the RxRsp structure 647 (0, i).
Create descriptors for data written to SDRAM 229 by using
The descriptor is stored in the mailbox of the channel processor 307 in the QME 305.
Put in. When all this is done, the CPRC 401 sets the owner bit 935 (0
), The receive data scope 625 (0) becomes available to the RxSDP 421 again
Set as follows. Owner bit 935 (1) is set and RxSDP421
When the work with the received data scope 625 (1) is indicated to be completed, the CPRC
401 is the same method as described for the received data scope 625 (0)
Then, work related to the reception data scope 625 (1) is performed. 803 Start 805 The data that the RISC core sends from the queue management engine via the local
FIG. 8 shows the CPRC 401 and TxSDP 427 when transmitting a stream of transport packets.
Is an overview showing how and interact. Outgoing packets are combined
Sending is much easier than receiving because you only need to send it and do not need to convert it.
You. Most of the work related to transmission is performed by the CPRC 401. Start with 803
The CPRC 401 first executes a loop 805. That is, receiving from QME 305
The channel processor 307 (i) checks the received queue status information and reads it.
It is checked whether or not there is a descriptor in the queue 217 that has been inserted. Shown at 807
CPRC 401, if there is a descriptor,
Queue command, which is also transmitted to the QME 305 via the payload bus 317.
Receive the descriptor. Next, the CPRC 401 is transmitted using the information in the descriptor.
The merge register 603 is set according to the need of the packet (811), and the
Set register in Tx control block register 637 using buffer tag
Then, the contents of the buffer are transferred from the SDRAM 229 to the TxSDP 427 (813), and the transfer is performed.
Start (815). If status 915 or EOP 917 indicates the end of the transfer, the CPRC
401 releases the TxSDP 427 and other resources used for transfer (817). TxSDP4
27 and CPRC 401 in the same manner as RxSDP 421 and CPRC 401
Corps 625 (0) and (1) are used alternately. The shift between data scopes
Because it is under the control of the program being executed by CPRC 401, the program
Allocates the resource represented by the data scope between TxSDP 427 and RxSDP 421.
You can do whatever you need to do so. Details of RxSDP 421: FIGS. 10 and 11 RxSDP 421 and TxSDP 427 are serial input 204 (i) and serial
Output 206 (i) and other components of channel processor 307 (i).
And a programmable interface to the channel processor 307 (
i). Thus, a particular input 204 (i) belongs to a particular protocol.
Media and transport packets as needed to adequately address
Specific output 204 (j) belongs to a specific protocol
It can be programmed to output media and transport packets. Each SD
P421 or 427 is a registry independent of its own microprogram storage.
Data set. FIG. 10 is a block diagram of the RxSDP 421. Component is a serial input
To parallel, first at the media packet level, then at the transport packet level.
A sequence of a processor and a FIFO that processes the input above the bell. Process
Some of the services are dedicated to address a particular protocol. The bypass path is
To allow data to bypass any processor and / or FIFO
Can be programmed. Overall, the components are:
Configurable physical logic 443 receives serial input from the physical layer and resolves it.
To generate a stream of 10-bit codes. A pin interface 204 (i) for receiving a 10-bit code from the physical layer
. Generate byte from 10 bit code received from pin logic 443 8b /
10b / decryption 1001.・ Small size FIFO that is asynchronous with different programmable read / write clocks
FIFO 1003. The write clock is at the frequency required for the input data stream
The movement and the read clock move at the speed of the CPRC 401. In the preferred embodiment, the FIFO
1003 has eight 9-bit word depths. An excerpt file coming from the small FIFO 1003 via path 1005 to the excerpt space 417
Pattern matching and fielding on a stream of bytes received with
Receive bit processor 1005 which performs a field extract. A received SONET framer 1007 that processes SONET frames. Of the data in the frame
Unscramble, remove protocol data from frame, and remove parity
Check and write protocol data to extract space 417 via path 1008
Put in. A synchronization processor 1009 for processing ATM cells. Discover cell boundaries and protocols
・ Return data, start TLE operation with protocol data, and
The rumble is released, and the protocol data is transferred via the path 1019 to the extraction space 417.
Write to. A large receiving asynchronous FIFO 1011 which is an asynchronous FIFO. In a preferred embodiment, the FI
FO 1011 is 64 bits word deep. FIFO 1011 is mainly used for VPI / VCI
Is used to execute ATM cells while TLE 301 is verifying,
Used to give the ket elasticity. • Operates under microcode control and patterns for 9-bit word data
A receive byte processor 1013 that performs matching and field extraction. The bypass path 1015 is connected to the MUXs 1002, 1006, 1014, and 1010.
Is constructed. The MUX 1010 also establishes a recirculation path 441. Bypass path
And the recirculation path is set by setting a bit in SDP mode 627.
, Can be set dynamically. Data is CPRC401 and bit processor
1005, between synchronous processor 1009 or byte processor 1013
, RxSDP control 613 directly. As described above, the channel processor 307 is integrated to provide very high speed data.
-Streams can be processed. When integrated, an integrated channel
The processor operates as one pipeline and each of the integrated channel processors
Sequentially process portions of the data stream. Coordination between integrated RxSDP421
Are implemented by token buses 1027, 1017, 1028. for example
For example, upon integration, the enabled Rx bit processor 1005
Incoming data stream only if it has a token provided by bus 1004
Does not perform system processing. RxSDP421 used to process the incoming stream
Some of the components vary depending on the type of input stream, so some talk
Bus is required. Details of Configurable Pin Logic 443: FIGS. 46 and 47 Configurable Pin Logic 443 can be configured in two ways: one, two, three or four of the SDPs 420 in the cluster Input stream to
And receive an output stream therefrom; and the medium through which either the input stream or the output stream is transmitted.
Works with the different physical interfaces required by the body. The first type of setting involves the integration of the channel processors 307 in the cluster 309
One of the elements that enables and processes high-speed input or output streams. No.
The two types of settings allow different transmission of the DCP 203 without adding a device outside the DCP 203.
The signal received from the medium can be used with a DCP2
Adapted for use with 03. Either type of setting is dependent on the channel processor.
Controlled by registers in local memory. The registers are
Set by the processor itself or by the XP 313. FIG. 46 shows that the cluster 309 in the DCP 203 has RMII, OC-3, DS1, DS3, GMII, and TBI.
And generate and generate serial data streams that comply with OC-12 standards.
4601 is a table 4601 showing how the settings are made. Column 4603 is
, List the I / O pins of each channel processor in the cluster; column 4605
Indicates the general purpose of the pin; therefore, I / O at each channel processor
Pins 0 and 1 are for clock signals, the remaining pins are for data
. The remaining columns show how the pins are used for each medium. Row 4607
Indicates pin usage in RAMII; 4609 indicates pin usage in OC-3
4611 indicates usage in DS3; 4615 indicates a channel in a cluster.
Receive data using two of the two
4617 illustrates the use of the GMII when the processor is used for transmission;
4619 shows the use in the TBI when the processor is used similarly;
Which channel processor changes between the transmitter and receiver
To be used. Various media require different types of drivers and receivers for I / O pins.
You. Therefore, each I / O pin in the settable pin logic 443 is a three-state driver, TTL
It has a driver and a PECL driver. For media such as OC-3 using PECL logic,
The pairs of I / O pins are set as different pairs as shown in column 4609. FIG. 47 shows the pin mode register 4701 and the SDP mode register 4713
And Each channel processor 307 has one of these registers.
I do. Register 4701 configures how channel processor I / O pins are configured
Decide what to do. Data Cnfg bit 4703 indicates that the I / O pin is a 3-state driver
, TTL driver or PECL driver
Is a bit. RxClk Mux 4705 and TxClk Mux 4707 receive and
And / or specify which pins are used to carry the transmit clock signal.
You. Rx Data Enable 4709 determines which pin is used to receive data.
Is specified. Finally, Tx Data Enable 4711 sends data
Specify which pins will be used to The SDP mode register 4713 can be any of the components of the RxSDP 421
Which recirculation circuit configuration is enabled and to which the channel processor 309 belongs
That control what kind of integration is currently employed within the cluster
including. A similar register exists for the channel processor TxSDP427.
I do. RxEn bit 4715 enables RxSDP 421 of the channel processor.
Indicates whether or not it has been Bit 4717 indicates that byte processor 1013 has
Indicates whether it has been enabled. Bit 4719 is bit processor 1
005 indicates whether or not it is enabled. Bit 4721 is the Rx Sonet framer
Indicates whether 1007 is enabled. Bit 4723 is the Rx synchronization processor
Indicates whether or not the service 1009 is enabled. The next two bits are for recirculation control.
Bit 4725 indicates recirculation to byte processor 1013
However, bit 4729 is recycled from extract space 417 to bit processor 1005.
Shows a ring. Integration mode field 4731 indicates that no integration is performed in the cluster
Or whether bi-directional integration occurs (ie, two channel processors
And two channel processors transmit) or four-way integration
Is specified (all four channel processors receive or transmit)
This is a 2-bit field. Building the Processor in the SDP: FIG. 11 FIG. 11 shows how the processor in the SDP is built. Details here
Is an Rx byte processor 1013, but the Rx bit
The same applies to the processor in the processor 1005 and the processor in the reception synchronization processor 1009.
You. Sonnet framer 1007 is constructed using a processor as shown in FIG.
Is a configurable state device. As shown in MUX 1107, the Rx byte processor 1013 has a large FIFO
An external input is received from 1011. The Rx byte processor 1013
23, a ring bus interface 415, an excerpt space 417 or a buffer
Provides an external output to the file 1025, which converts the protocol data unit to DMEM
405. Components built into Rx byte processor 1013
Include: • Contains microcode that processor 1013 processes,
By providing control signals (dashed arrows) that control other components
A control store 1101 responsive to the currently addressed microinstruction. Control storage
The unit 1101 is loaded by the XP 313. -Next address logic 1105. Control signal from control storage unit 1105 and condition code
MUX1121 and content addressable memory (CAM: content-addressable me)
mory 1117) is input to the next microcontroller executed from the control storage unit 1101.
Responds by selecting an instruction. A counter 109 and a general register 1115; The counter indicates that processing is currently taking place.
Track the bit position in the packet. 8-bit counter 1109 (0 ...
3), which are set as two 16-bit counters, and
As indicated by the input to the next address logic 1105 from the counter.
Specify the drive whose code depends on the counter value. General register 1115 is being processed
6 8-bit registers for storing data used for CAM (content addressing memory) 1117: CAM is used for pattern matching
Memory. Each cell in the CAM contains a pattern and is stored in the CAM cell.
CAM is presented with data that matches the pattern to be
Is output. Microcode specifies actions that depend on values output by CAM
I do. The CAM 1117 is loaded by the CPRC 401 or the XP 313. In CAM
Has 64 9-bit words and the CAM is programmed into up to 16 logical CAMs.
Can be divided into groups. The CRC 1111 is dedicated hardware for performing a cyclic redundancy check. Other specialty
Hardware is included for descrambling the packet. ALU 1119 is an 8-bit ALU with a built-in barrel rotator. As can be seen from the above, the XP 313 stores the CTL storage unit 1101 and the CAM 1117
Set Rx byte processor 1013 for operation by loading
. The CPRC 401 stops and activates the byte processor 1013 by a reset signal.
Start up. When the byte processor 1013 is set to start, each received byte
To the CAM 1117. If a match is found indicating the beginning of the transport packet, control
The process 1105 starts executing microcode to process the transport packet.
. The counter is set and the byte processor 1013 detects the CAM 117
Process the packet as indicated by the further match and the counter value. Match is
, Microcode, (pattern, mask, length) or (offset, pattern)
, Mask, length). However, the offset is
Offset within packet, mask specifies "don't care" bit
And length specifies the number of bits in the match. Protocol data from transport packets
Data is extracted and the extracted space 417 or the ring bus interface 415 is
Sent via path 1019 and the protocol data unit is transmitted via path 425
And sent to the 16-byte buffer 1025. From here, the protocol
Data units are DMAed to lines in DMEM 405. The excerpt is (offset
, Length, register address) in the microcode. Office
Again indicates the offset within the packet, and the length is the field to be extracted.
The register address is the length of the stored field.
This is the address of the register in the general register 1115 located in the register. Details of Rx Bit Processor 1005 Continuing with a detailed description of the functions performed by the components of RxSDP 421
, Rx bit processor 1005 is similar to Rx byte processor 1013.
However, the difference is that a linear feedback shift register is provided instead of the CRC 1111.
The linear feedback shift register can be set up to 32 bits long,
It has positions for polynomials and data streams. The linear feedback register is
Used to generate hash values or other checksums. Rx
The bit processor 1105 controls the buffer received by the RxSDP 421 at the lowest level.
Process a stream of sites. Because of this, HDLC frames and invalid sequences
STS frames in OC-3 data stream, detecting and eliminating padded zeros
To detect and delete the preamble of incoming Ethernet frames.
Be programmed. Details of Received SONET Framer 1007 The received SONET framer 1007 handles SONET frames. Framer 1007 is
Rx bit processor 1005 or directly via bypass 1015
Frame from the interface 204 (i). SONET Framer 10
07 is the physical layer interface connected to the pin interface 204 (i).
The received clock / frame synchronization signal recovered by the face chip and the frame
8 bit data included in the system. SONET frames are transport overhead.
And a synchronous payload envelope (SPE: synch
ronous payload envelope). Synchronous payroll for transport overhead
Contains the STS pointer pointing to the de-envelope. Synchronous payload envelope
The rope contains path overhead bytes. [0083] Received SONET framer 1007 descrambles the bytes in the SONET frame.
, Check parity, and extract transport overhead via path 1008
Write in space. The receiving SONET framer 1007 further interprets the STS pointer,
Discover SPE. When it finds it, Framer 1007 checks the parity
Then, write the path overhead of the SPE into the extract space. Payload in SPE
It is sent to another component of RxSDP421 as needed depending on the type of load.
You. For example, if the payload is an ATM cell, the reception synchronization processor 1009
Sent. In the preferred embodiment, the receiving SONET framer 1007
Do not demultiplex the code. Details of Reception Synchronization Processor 1009 The reception synchronization processor 1009 specializes in ATM cells. 53 cells for ATM cells
Is included. 5 bytes are virtual path indicator, virtual channel indicator
Data, payload type indicator, cell loss priority indicator, comprehensive flow control information
This is the header that contains the report and header error check bytes. 48 remaining
Is the payload. The reception synchronization processor 1009 performs header error checking.
Check applied sequentially to the 5-byte sequence, and the fifth byte in the sequence is
The header error check byte of the preceding 4 bytes in the sequence
That the byte stream is a stream of ATM cells
Is determined. If the header error check fails, the reception synchronization processor 1
009 continues the trial. If the header error check is successful,
Processor 1009 finds the ATM cell. Programmable number in one line
When a cell is found, it is synchronized with the ATM cell stream. Processor 1009
Causes a programmable number of consecutive header error checks to fail.
Indicates that the synchronization processor 1009 is not synchronized with the stream of ATM cells.
Until they are synchronized. When the reception synchronization processor 1009 is in synchronization with the ATM stream, the ATM
The header of the cell is dispersed, and the contents of the header are output to the extraction space. Receive synchronization process
The processor 1009 further descrambles the payload and attaches a status byte.
In addition, if the header check for a cell is bad, it can be discarded.
To further process the payload. Generally speaking, receive sync pro
The payload output from the processor 1009 proceeds to the large FIFO 1011. This FIFO
Performs TLE matching on VPI-VCI before further processing of the payload is required.
It has enough depth to allow it. Details of Receive Byte Processor 1013 Receive Byte Processor 1013 is programmed to perform several functions.
Can handle: • Handle HDLC escape sequences for PPP for SONET; • Includes frame check sequences for Ethernet and AAL5 3
Perform 2-bit CRC check; Channel processor 307 (i) is integrated with other processors to 1000BASE
-When processing XGigabit Ethernet, the receive byte processor 1013
Recognize Ethernet segmentation; receive byte processor using recirculation path
1013 integrates with other processors to handle T1 and T3 data rates
Can be. The recirculation path also handles multi-channel HDLC and encryption / decryption
To be able to The receive byte processor 1013, upon detecting the end of the frame,
Write in the excerpt space. The receive byte processor 1013 extracts VPI / VCI from the header of the ATM cell,
Retrieve messages containing virtual path indicators and virtual channel indicators
To the TLE 301 via the switching bus 311. TLE 301 is a channel processor
307 (i) for ATM streams with VPI-VCI combinations.
Respond to the message by returning a message stating the output queue. [0085] Receive byte processor 1013 processes 9-bit words. Its behavior
Has already been described in detail. Example of Component Cooperation In the following example, the pin interface 204 (i) of the RxSDP 421 is an optical cable.
It is assumed that it is connected to a cable. Payload data on this optical cable
Sent using SONET protocol. The payload data in the SONET frame is
A payload in an ATM cell whose ATM cell has a specific VPI / VCI pair.
Is an IP packet. The RxSDP 421 extracts ATM cells from the SONET frame, and
Programmed to process the ATM cells of The bytes from the SONET frame go first to the Rx bit processor 1005.
This processor sends the bytes to SONET framer 1007. Rx bit processor
The sensor 1005 also detects the start point of the frame, and receives a signal notifying the arrival of the frame.
Send to NET framer 1007. The receiving SONET framer 1007 descrambles
And performs parity check, and places the payload data in the SONET frame.
Place. The ATM cell payload goes to the receive synchronization processor 1009, which
Sessa detects the ATM cell, reads its header, and extracts the information in it.
Send to 17. Next, the ATM cell payload advances to the Rx byte processor 1013.
The processor 1013 sends the VPI / VCI pair of the ATM cell to the TLE 301 for conversion, and
Extract information from the header of the packet included in the payload of the packet into the excerpt space 417
Read. Details of TxSDP 427: FIG. 12 The TxSDP 427 performs the reverse operation of the RxSDP 421. That is, from the SDRAM 229
Receiving the protocol data unit, its destination and pin interface 2
06 (i) to the format required by the physical interface to which it is connected.
Add the protocol data needed to output the protocol data unit
. Again, the operation is hierarchical and the protocol data for the transport packet is
Is added before the protocol data for the media packet. FIG.
The details of TxSDP 427 are shown. The protocol data unit starts from DMEM405
A 16-byte buffer 1229 is reached via path 431. Buffer 122
From 9, the data unit is read by the Tx byte processor 1213
. The protocol data arrives from the merged space 419 via the path 429 and the Tx SONET
Framer 1207 and Tx bit processor 1205 and Tx byte processor
Proceed to 1213. The recirculation path to RxSDP 421 is at 441. MUX1206
1204 and 1202 construct a bypass path 1215. According to the integration path 1223
Specific TxSDP 427 integrates media protocol data with specific TxSDP 427
Added to the stream of transport packets generated by other TxSDPs 427
Can be. If a particular TxSDP 427 is part of the integration, the Tx byte processor
The output of the source 1213 is controlled by a token on the Tx byte token bus 1225.
Is controlled. The components of TxSDP 427 are similarly named for RxSDP 421
Similar to a component, but its function is to extract protocol data
Without adding protocol data to the protocol data unit stream
The difference is that As a result of the difference in functions,
There is no equipment to send the bus message. Tx status 639 and TxCB
637 is similar to the corresponding component of the Rx data scope 643,
In this case as well, there is a difference in the direction. By TxSDP ctl 615, CPRC4
01 can communicate with TxSDP 427, and the register for SDP mode 627 is bypassed.
Service path can be set. The components are as follows in the order in which the outputs are processed: Tx byte processor 1213 sends protocol data unit from DMEM 405
Program to read, insert, delete and swap fields
Is possible. Also, the Tx byte processor 1213 converts the ATM header into a protocol.
Adds a 48-byte chunk before the data unit and arbitrarily changes the cell contents.
Programmable to generate ATM cells by rumble.
Tx byte processor if there is no protocol data unit to send
Reference numeral 1213 generates an idle ATM cell. Large asynchronous FIFO 1211 has a depth of 64 words and a width of 9 bits,
It provides the resiliency needed for field insertion and deletion performed by the server 1213.
The FIFO 1211 is written at the core clock speed and is either core clock or serial clock.
Read at any of the al clock speeds. -The output of the Tx byte processor 1213 is the payload of the SONET framer 1207.
Generates a SONET frame that is a code. Tx bit processor 1205 is an intelligent parallel-serial
Processor. Under program control, this processor
Perform field insertion, deletion and replacement for Input data is 18
Output data, one bit at a time, depending on the physical interface.
It becomes 2 bits or 4 bits. Processor 1205 includes a general-purpose linear feedback shift
It has a register. • Small FIFO 1203: Data is written to this FIFO at core clock speed and
Read from here at real clock speed. FIFO is 8 words deep and 9 bits wide
It is. The 8b / 10b encoder 1201 performs 8b / 10b encoding of data. The processors 1213, 1207, 1205 are programmable and
It has the same general internal structure as the Rx byte processor 1013 described above. The cooperation of the components is illustrated with an example. This example uses the RxSDP421
The opposite is true. The input is a protocol data unit, which is an IP packet. Out
The force is a SONET frame with ATM cells as its payload, and the ATM cells
It has an IP packet as its payload. The IP packet is finally transferred to the SRAM 22
9 and DMA-processed to the DMEM 405 from there. ATM cells and SONET frames
The protocol data needed to form the is in the merged space 419. IP packet
Is read from DMEM 405 in 48 byte chunks. Tx byte
The processor 1213 creates an ATM header for each 48-byte chunk,
The originating ATM cell proceeds to the large FIFO 1211. From here, the cell is SONET Framer 1.
Read by 207. The SONET framer 1207 converts ATM cells into ATM frame packets.
Batch and add necessary SONET protocol data. SONET frame
The frame is then output to the Tx bit processor 1205, which
This is serialized and output to the small FIFO 1203. From here, the frame is Enko
The process proceeds to the mode 1201 and further to the pin interface 206 (i). Utilization of Channel Processor 307 in PDH Telephony Long-distance telephone service providers have been using digital processors to carry long-distance calls for many years.
I have used the digital trunk line. In such systems, calls connected by calls
The speech signal generated by the talk is digitized into one byte samples, and from many calls
Digitized samples are multiplexed on the main line with distribution information about the samples
Be transformed into Although the sample and its distribution information look like a very simple packet, this system
There is no hierarchy of packets in the system, and the relationship between the receiving port and the transmitting port is one.
It is fixed. As a result, a table lookup for the packet in SDRAM 229 is performed.
No loops, descriptor queues or buffers are required. Instead, the receiving channel
The processor 307 (i) communicates with the transmitting channel processor 308 (j) globally.
Taking advantage of the fact that they share the global address space, each sample is
It simply writes to the queue in the DMEM 405 of the processor 307 (j). Submit
The CPRC 401 of the side channel processor 307 (j) manages this queue. Integration of channel processor 307: FIGS. 13, 14 and 26-27 As described above, channel processor 307 has four channel processors 30.
7 clusters 309. Place channel processors in the cluster
This allows for faster speeds than would be possible with a single channel processor 307
These can be integrated so that they can be received or transmitted. Good
In a preferred embodiment, OC-12c and Gigabit Ethernet
-Send and receive protocols. The OC-12c protocol uses four channels in a cluster.
Two processors are used to receive data and the other two are
Can be used to send. Or use two clusters
, One for data reception and the other for data transmission. Gigabit
The Ethernet protocol uses two clusters, and the protocol
Therefore, four channel processors in one cluster are used for reception, and
According to the protocol, four channel processors in the other cluster are available for transmission.
Used. Integrating a group of channel processors to receive the protocol
Here, it is called reception integration. In response to this, a group of channels is used to transmit the protocol.
Integrating the channel processors is called transmission integration. In the reception integration,
Each of the channel processors receives all of the input from the protocol, but
Process only part. In transmit integration, each of the channel processors is
Part of the output of the
Output to the sending channel processor. Channel processor in cluster
Serial I / O pins are shared by all channel processors in the cluster.
Wired to receive input. Also, all channel processors
Setting the integrated channel processor to be controlled by the same timer
Is also possible. Finally, a token constructed as a signal in shared memory
To coordinate the operation of the channel processors in the cluster. Integration is a
By setting a configuration register in the channel processor belonging to the
Be executed. FIG. 13 shows details of an arrangement in which the integration can be performed in the preferred embodiment.
Cluster 309 (j) of four channel processors 307 (j, 0 ... 3)
Is illustrated. The inputs to the cluster are integrated as follows. Each channel
The processor 307 (j, k) has seven I / O pins CPP (0 ... 6) and has 28
A star I / O pin 1301 is provided. Cluster I / O pin 1301 (0) is the channel
The processor I / O pin 1303 (0,0) is the CLP 1301 (2).
(0, 1), and the CLP 1301 (27) follows the CPP 1303 (3, 6) in this order.
). The pins are CLP1301 (0), CLP1301 (7), CLP1301 (1
4), the input in one of the CLPs 1302 (21) is
, 0), 1303 (1,0), 1303 (2,0), 1303 (3,0)
Interconnected to be received by The output is the cell / frame shown in FIG.
Integration is performed via the integration path 1223. As shown, each TxSDP 427 (j
, I) is connected to the MUX 1208 of each of the other TxSDPs 427 in the cluster.
Therefore, one TxSDP 427 (j, i) is one of the other TxSDPs 427 in the cluster.
The output can be received from one of the large FIFOs 2122 and
The output can be processed in subsequent equipment. Specific RxSDP421 or TxSDP42
How S7 participates in the cluster is indicated by a bit in SDP mode 627.
Determined by setting. Each channel processor 307 selects one of the eleven clock inputs
It also has a clock MUX 1307 that allows Of the clock inputs
The external global clock inputs 1309 (0.7) are digital clocks.
This is for a clock external to the channel processor IC 203, and
Two of the powers, CPPGC 1311, are recovered by one channel processor
Is the global clock input provided to other channel processors.
One of the local clocks 1313 is a digital channel processor.
The clock is specific to the IC 203. Coordination of processing by the cluster of channel processors is performed by three sets of token links.
In other words, the TxSDP token ring 1225
The output from the Tx byte processor 1213 of xSDP 427 is adjusted. The token
Only the associated TxSDP 427 outputs to the large FIFO 1211. As shown in FIG.
, The device in the RxSDP 421 provides three token rings, namely
Ring 1027 for Rx bit processor 1005, Rx synchronous processor 1
Ring 1017 for R.017 and resource for Rx byte processor 1013
1028. RxSDP 42 with token ring enabled
Devices in 1 provide output only when they have a token. Which Token Lin
Is used depends on which devices in RxSDP 421 are enabled
. The tokens in the ring for TxSDP 427 and RxSDP 421 are TxSDP and RxSDP
Transmitted and tested by microcode executed by the DP. Channel push
The Processor Token Ring 1315 is provided by the channel processor in the integration.
Controls write access to global bus 319. Ring 1315
Only the channel processor that currently has a
Can be accessed for writing. Channel processor token
Ring 1315 is a cluster memo shared by the channel processors of the cluster.
It is constructed by the signal in 503. The integration is based on the arrangement of local and shared memories in the cluster shown in FIG.
More support. As a result of this arrangement, a cluster memory 503 is obtained. K
The raster memory 503 stores the channel processor (0. 0) in the cluster 309 (j).
.. 3) with a channel processor local memory 503 for each
. Each channel processor memory 503 (j, i) stores a serial data program.
A channel processor 307 (j, i) memory 1403 for the processor;
EM 405, bus control memory 1405, memory 1407 for CPRC 401,
, And a part of the instruction memory 403. Each channel processor 3 in the cluster
07 is connected to other channel processors in the cluster via the cluster path 439.
Access to each DMEM 405 can be performed. Other channel pros
There is a one-cycle wait time for Sessa's access to DMEM 405. Instruction memory
When the communication processor 203 is initialized, the instruction memory is shared IMEM 140
9 to be shared among all four channel processors
Can be. Or splitting between all four channel processors
Yes (IMEM403). When the instruction memory is set as shared IMEM 1409,
Each of the four channel processors in the raster has one cycle in a fixed
The access right to the shared IMEM 1409 is given once per file. Shared memory IM
The EM 403 allows the channel processor programmer or cluster thereof to
Separate channel processor at the expense of larger processor
To increase the flexibility of the device. Example of operation of integrated channel processor: FIGS. 26 and 27 When integrated channel processor handles Gigabit Ethernet, receiver
Is a cluster 309 (i) of four channel processors and the transmitter has four
Another cluster of channel processors 309 (j). FIG. 26 shows RxSDP4
21 (i, 0... 3) are set, and FIG. 27 shows TxSDP 427 (j
, 0 ... 3) are set. Both clusters 309 (i), 3
09 (j) indicates that one reception clock of the channel processor in the transmitter is
It is set to be the master reception clock for the master. Check the transmitter cluster
All of the channel processors have a Gigabit Ethernet clock.
Select the signal in the external global clock 1309. Within CP 307 of the cluster
Between the CPRCs 401 is performed by a signal in the cluster memory 503.
. RxSDP Integration: FIG. 26 As shown in FIG. 26, each of the RxSDPs has a decoder 1001 and an Rx bit
Processors other than the processor 1005 and the Rx byte processor 1013 are bypassed.
Is set to The decoder 1001 outputs a 3-bit synchronization loss to the CPRC 401.
Give force 2603. Receiving input by the Rx bit processor 1005
The output from the Rx byte processor 1013 is controlled by the
Controlled by token bus 1028. For this reason, the Rx bit processor
When the processing result of the contents of the small FIFO 1003 has a token,
1011 and the Rx byte processor 1013 similarly has a token
Only when this is the case, the processing result of the contents of the large FIFO 1011 is output. In the preferred embodiment, each channel processor has a token
Receive one frame of Gigabit Ethernet data and receive the frame
Pass the token to the next channel processor in the cluster and receive
Process the next frame. As already mentioned, one of the consequences of data processing is
Descriptor for data. The channel processor uses the global bus 319
To the mailbox 511 in the queue management engine 305 via
Command, and the queue management engine 305 queues the descriptor.
Responds to commands by Finally, it is built as a signal in shared memory
The token that is received by a particular channel processor in the receiving cluster
To the global bus 319 only when
Restrict access to global buses by buses. FIG. 27 shows how the TxSDP 427 (j, 0 ... 3) in the output cluster is set.
Or As shown in the figure, only the enabled part of TxSDP (j, 0 ... 3)
Is the Tx byte processor 1213, large FIFO 1223 and integrated path 1223
is there. The rest of the processing of the output stream is performed by TxSDP (j, 0),
Here, the Tx bit processor 1205 and the encoder 1201 and the Tx bit
Processor 1213 is enabled. A certain TxSDP 427 (j, k)
If there is a token on the bus 1225, its Tx byte processor 12
13 transmits data via a large FIFO and an integrated path 1223 to the TxSDP 427 (j, 0).
). TxSDP427 (j, 0) selects appropriate input in MUX1228
The input is then processed in the enable processor following the MUX 1208. In the setting 2701, each channel processor 307 in the cluster
Outputs a frame of bit Ethernet data. As already explained,
The channel processor 307 issues a dequeue command to the QME 305
To start transmission, and the protocol data unit of the frame to be transmitted.
Get the descriptor for the event. CP token ring 1315 is in the sending cluster
To ensure that all channel processors get the descriptors in the correct order.
Used. The channel processor in the transmit cluster uses the global bus 319
And the channel processor talks into the CP token ring 1315.
Only when it has a token, the queue management engine 305 is given a dequeue command.
Can be The channel processor stores a descriptor for the output data.
Once obtained, the Tx byte processor 1213 can begin processing data.
Can be. The data is transferred to the Tx byte processor 1213 by the token ring 13.
Tx byte processor 121 only if it has a token provided by
3 can be output. The output of the Tx byte processor 1213 is
Proceed to TxSDP (j, 0) via the path 1223 and output there. Again,
This arrangement allows certain channel processors in the cluster to try to output.
Frame, while the other channels in the transmitting cluster
The processor outputs the frame. The OC-12c cluster functions substantially the same as above, but within four clusters
Two of the channel processors are configured for receive and two are configured for transmit.
Is different. Token Ring is used as described above, but OC-12c is an ATM
Token Ring 11017 receives when used to transmit cells
It differs in that it controls a receive synchronization processor 1009 in the channel processor. Details of Execution Processor (XP) 313: FIG. 15 XP 313 is a general-purpose CPU for constructing a MIPS IV instruction set. This is a digital communication
Performs the following functions in the communication processor 203: Resets and initializes the DCP 203; Loads programs to channel processor 307 and organization processor 303
A set of parameters for the code and their operation; the translation table 20 used by the table lookup engine 301
9 and the registers in the table lookup engine 301
Handling of exceptions; running the real-time operating system of DCP 203; and interfacing with host 227, if any. The interface with the host 227 is the host 22 having a variable size window.
7 in the global address space 321 and the XP 313
Processing of packets received from or transmitted to the host 227 is also included. FIG. 15 is a block diagram of the XP 313. XP313 is a channel processor
It has many of the same components as 307. Like the channel processor, this
These are the ring bus 311, the payload bus 313 and the global bus 31
9 The basic processing element is the XP RISC core processor 1501,
This is a processor similar to the CPRC 401. Interface with ring bus 311
Base, two banks of local data memory 1507, 1508, payroll
Interface with the global bus 319 and the interface with the global bus 319.
There is a face 1513. DMEM1507 and DMEM1508 are both payload
Accessible via the bus interface 1511 and actually
A separate node on the load bus 315. Only DMEM1507 is global
Accessible via the network interface 1513. Channel processor
The interface of the XP 313 which does not exist in the server is a general-purpose I / O interface 151.
7, a PROM interface 1525 and a PCI interface 1523. life
The command memory has three components. That is, loadable instruction memory
1503, instruction read-only memory 1504, and XPRC 1501
Instruction memory loader 1 including a program to be executed to load EM1503
506. For code executed by XP RISC core 1501 and code execution
The data to be used is stored in SDRAM 229, and needs for XP RISC core 1501
Accordingly, DMEM 1507, DMEM 1508, and IMEM 1 are transferred from SDRAM 229 via DMA.
Moved to 503. Like the channel processor 307, the XP 313
Global address space 321 can be accessed. XP / CP setting register
1517 is a part of the global address space 321 in the XP 313. Details of Functions Executed by Execution Processor 313 Execution processor 313 sends a reset signal to each channel processor 307.
The chip received by the digital communication processor 203
Responds to a reset signal. When doing so, XP 313 will start executing the initialization code.
Start. The initialization code is PCI interface 1523 and global bus 3
17 has already been loaded into the SDRAM 229 or via a PROM interface.
Included in an optional external PROM coupled to face 1521. Initialization code
Shared for IMEM403 and cluster for each channel processor
A program that loads IMEM1409 and is executed by RxSDP421 and TxSDP427
And the setting information is loaded into the register in the global address space 321.
I do. When the digital communication processor 203 is initialized, the XP 313
Implements real-time operating system for communication processor 203
Support network monitoring protocols and are notified by the channel processor.
Handle exceptions. The XP 313 further controls the global address space 321
Using access, channel processor, organization processor 303, queuing pipe
The management engine 305 and the buffer management engine 315 are managed. XP313,
Using the interface with the ring bus 311, the table lookup
Manage the engine 301. A certain management function stores the conversion table in the conversion table 209.
Insert and delete file entries and another function manages the table of statistics. Strange
The ability to manage the conversion table 209 and the buffer management engine 315 is based on XP31.
3 gives the power to set the relationship between input and output ports in DCP 203
. If the host 227 is present, the XP 313 notifies the host of the global
Table that provides visibility into the local address space and that TLE 301 manages for it.
Files can be read. XP 313 is further received from host 226
Or as a packet transceiver for packets destined for it
Can work. For example, host 227 may use Internet Protocol
A node that may receive or transmit Internet packets.
XP313 is essentially a packet processor and a channel processor.
Operates in the same way as the above, except that the I / O interface is a PCI bus. Organization Processor 303: FIGS. 16 to 20 As shown in FIG. 3, the organization processor (FP) 303 is a digital communication processor.
The interface between the processor 203 and the switching organization 222 is managed. Switching organization 2
22 is used to communicate between several switching devices, such as a communication processor 203.
Used. FIG. 19 shows that a plurality of DCPs 203 (1.
3 (i) shows a method of coupling to the switching tissue 222. Belongs to DCP203 (i)
The packet received at the serial input (i, j) is
Is transferred to another DCP (k) through the exchange organization 222, and is received by the FP 303 (k) there.
And output at serial output 206 (k, l). The data moves within the organization 222 as an organization frame. Organization frame accuracy
The shape depends on the switching tissue, but the tissue frame is generally the part shown in FIG.
Has: The organization header 1803 indicates that the organization 222 is responsible for distribution and flow control within the organization 222.
The frame header 1805 inputs the organization frame 1801 to the organization 222.
Information that the source device gives to the destination device that receives frame 1801 from organization 222
The payload 1807 is the payload received from the network to the source device
And output to the network by the destination device. As will be described in further detail below, the tissue processor 303 may be configured to use different types of sets.
It can be programmed to handle woven frames. Suitable environment
For example, the tissue processor 303 generates a frame having a fixed length (FL1809).
Can be programmed to process. This fixed length is 32 bytes to 1
The range is 28 bytes. From the above description, the organization processor 303 is basically the channel processor 3
It will be clear that it has the same function as 07. However, the serial port
The input is received from the switching organization 222 and the output is transmitted to the organization 222. This
Differences have important consequences. First, the switching organization 222 has a serial input and
It receives a parallel input, not an output, and provides a parallel output. Input or
The width of the output depends on the switching system. In the preferred embodiment, the tissue processor 3
03 outputs data at 8, 16, or 32 bits wide per clock cycle.
Programmed to force. Second, organization processor 303 is faster than channel processor 307.
You have to process the data in degrees. One reason for this is that the input and output are serial
This is because it is not parallel but parallel. Another reason is that the switching organization 222 is
The organization processor 303 receives data from the switching organization 222
The speed at which data can be provided to the switching system 222 is the speed and speed of all devices.
And the processing capacity. To achieve the required operating speed,
The weave processor 303 is constructed as a pair of finite state devices. Finite state machine
In a preferred embodiment, it works with a tissue frame 1801 having the following characteristics:
The frame has a predetermined length; the data is preceded by a fixed length organization header 1803; the switching organization is multicasting with the destination bit mask in the organization header.
(Delivery of packets to two or more destinations simultaneously); congestion information can be extracted from the organization header by a simple state machine; and
And the first ancestral transmitter frame 180 in the sequence of the
The relationship of 1 is deterministic. Details of Organization Processor 303: FIG. 16 FIG. 16 is a block diagram of the organization processor 303. Channel processor
The general similarity to FIG. Channel processor 3
07, the organization processor 303 includes a payload bus 317, global
Coupled to bus 319 and ring bus 311; Therefore, SDRAM229
Send and receive protocol data units to and from the global address space
321 and a message is communicated with the table lookup engine 301.
Page can be sent and received. There are three main differences: Rx organization processor 1617 and Tx organization processor 1621 are 32-bit buses
Connected to organization 222 by 1619, 1623; organization control engine 1601 is a fully programmable RISC processor
Rather, two parameterizable state machines. That is, the organization processor 3
Rx organization control engine 1604 that processes frame 1801 received in
, Tx organization control for processing frame 1801 output from organization processor 303
Engine 1602; and organization control engine 1601 is a direct connection to queue management engine 305.
Units 1625, 1627, thereby via the global bus 319
Access to the queuing management engine 305 that has fewer temporary changes than possible access.
Gain access. The operation of the organization processor 303 is different from the operation of the channel processor 307 in general.
Is similar to By the switching organization 222, the organization frame 1801 stores the Rx organization data.
Receive in 8, 16 or 32 bit chunks in processor 1617
Be trusted. The Rx organization data processor 1617 outputs the headers 1803 and 1805.
It is separated from the payload 1807. Part of the information in the header goes to extract space 1613
Then, use by the Rx organization control engine 1604 becomes possible. Rx organization data
Processor 1617 uses other information to generate a message for TLE 301
create. The protocol data units are MUX1605, DMEM1603 and
D and the buffer 231 (i) in the SDRAM 229 via the payload bus 317.
MA processed. The Rx organization control engine 1604 uses the buffer 231 (i)
Tag 233, the header information in the extraction space 1513, and the Rx organization data
TLE 30 in response to a ring bus message sent by sesa 1617
1 for the protocol data unit using the information received from
The predicate 217 is created. Individual connection 1625 to queue management engine 305
, The organization control engine 1601 performs an enqueue operation for the descriptor. The transmission processing is executed by the Tx organization control engine 1602. Tx engine 160
2 is a matrix tube for a descriptor 217 that specifies the destinations that the switching organization 222 can reach.
The descriptor is read from the queue 215 held by the processing engine 305. Tissue processor
The server 303 reads the descriptor from the forefront of the queue. For each descriptor, the organization process
The server 303 sets the merged space 1615 using the information in the descriptor. this
Is the organization frame for the data specified by the buffer tag 233 of the descriptor.
Needed to create headers 1803 and 1805 for
Done by information. The organization processor 303 also stores the buffer
233, the payload bus 317, the DMEM 1603 and the MUX 160
5 from the buffer memory 229 to the Tx tissue data processor 1621.
Start DMA. Data processor 1621 stores information in merged space 1615.
The headers 1803 and 1805 are created using the
Create a payload using a data unit. Tx organization data processor
When the 1621 creates the tissue frame 1801, the organization frame 1801 is
, 16 or 32 bit chunks. Details of Rx organization data processor 167 and Tx organization data processor 1621:
FIG. 17 shows the Rx organization data processor 1617 and the Tx organization data processor 1
FIG. 621 is a detailed block diagram of FIG. Start with Rx Organization Data Processor 1617
Then, Rx organization data processor 1617 couples to input data bus 1619
Input FIFO 1708, organization header interpreter 1707, header
Payload separator 1703, payload FIFO 1705, header
A tractor and interpreter 1701. Payload FIFO 1705
Is coupled to MUX 1605 via bus 1616 and includes header extractor and
And the interpreter 1701 passes the path 1614 to the extraction space 1613
1616 couples to the ring bus interface 1611. Compo
Nents 1701, 1703, and 1707 are used for RxSDP421 and TxSDP427.
Built using the same kind of programmable microsequences
It is. The operation of the Rx organization data processor 1617 generally corresponds to the operation of the RxSDP 421.
, Except that serial-parallel data conversion is not performed. Off
The bytes of the organization frame 1801 received from the replacement organization 222 are stored in the FIFO 1708 first.
And the organization processor 303 and the organization 222 are
It can operate at a lock speed. The switching organization 222 is located at the end of the FIFO 1708.
Write, organization header interpreter 1707 from the front of FIFO 1708
Read. The organization header interpreter 1707 reads the organization header 1803.
Then, the selected portion of the organization header 1803 is output to the extraction space 1613. Processing
The next stage is the header payload separator 1703, which
-The header 1808 is separated from the payload 1807, and the payload is
05, from which the payload is DMA processed to a buffer memory 229. F
IFO 1705 is the payload until DMA access to DMEM 1603 becomes possible.
Is large enough to hold Next, the frame header 1808 is the header
Go to the extractor and interpreter 1701, where the header is interpreted
And extract information from the header to extract space 1613 and / or ring bus interface.
Output to the face 1611. The Tx organization data processor 1621 has three programmable components.
And two FIFOs. As with the Rx organization data processor,
The configurable component is constructed utilizing microsequences. Blog
The ramming-enabled component is configured by the organization control engine 1601 by the merged space 1615.
Generator 17 that generates frame header 1805 using the information entered in
09 from the header 1805 and the buffer memory 229 via the path 1620.
A Header and Payload Merge 17 with Merged Payload 1807
11 and an organization header 1803, which is stored in the frame 1801 by the switching organization 22.
And an organization header generator 1715 to be added to the frame 1801 before being output to
I can. FIFO 1717 provides different speeds for tissue processor 303 and switching tissue 222.
And the FIFO 1713 copes with the delay in accessing the DMEM 1603.
Gives the flexibility needed for. Setting of switching system using DCP 203: FIGS. 19 and 20 The organization processor 303 determines that the DCP 203
01 can easily interact with switching components that can send and receive 01
So that 19 and 20 show three of the many possible settings
. The setting 1901 indicates that some DCPs share one switching organization 222, but already have
Is described in detail. In setting 1905, there is no other switching organization,
Switching is performed by connecting the two DCPs 203 to each other via the tissue processor 303.
Is performed by Connect several DCP203 tissue processors to one bus
And transmits a DCP 203 to the bus to regulate access, such as a token ring.
Or extend such a system by providing other mechanisms.
Can also be. In the setting 2001, several DCPs 20
3 as well as non-D for line interface 2003 that DCP 203 does not address
CP logic 2002 is connected. With such a setting 2002, existing devices can be used.
Can be integrated into the switching system using the DCP 203. Table lookup engine 301 and translation table memory 207
Details: FIG. 21 to FIG. 24 As described above, the table lookup engine 301 uses the channel
From the processor 307, the organization processor 303, and the execution processor 313.
In response to the message received on the translation table memory 207.
Performs a lookup operation on the translation table 209 of
A ring bus message with the operation result is returned to the device. FIG. 21 shows details of the preferred embodiment of the translation table memory 207. Conversion Te
The cable memory 207 is a 64-bit pipelined bursting star.
Built using tick RAM modules. Memory 207 has eight tables
Sub-pool 2101 (0 ... 7). Table pools are
Can be further subdivided into different sized table entries,
All table entries in a particular table pool must be the same size
Must. Two of these table entries are shown in FIG. Sand
That is, the link table entry 2111 and the data table entry 211
9 Table pool 2101 is a more contiguous table entry
Sub-component table 2106. Figure 2 of these
21. That is, the link table 21 of the table pool 2101 (1)
07 and the data table 2117 of the table pool 2101 (7).
Each table entry is stored in the component table 2106 to which it belongs.
Has an index. For this reason, LTE 2111 uses link index 210
9 and the DTE 2119 has a data index 2114. component
Entries in the table 106 in the table 2106 have a table
Multiply by the size of the entry in the
The location is specified by adding the result to the location of the point. There are generally two types of component tables 2106. That is,
A link table and a data table. Which kind of component
Table 2106 is also used with keys associated with the data in the data table.
It is. For example, the translation table 209 identifies the VPI / VCI pair in the ATM packet header.
Queue in queue memory 213 that is to receive the ATM packet descriptor
It is converted to the number in column 215. The VPI / VCI pair is the key, and its position
The specified data table entry 2119 contains the queue number. Search al
The algorithm determines how to use the key in the translation table. Link
Table contains other index table entries or data tables
Contains the index of the file entry. This is the data table entry
It is used together with the converted key to specify the position of 2119. Link Te
The fact that table entries are used to locate other entries
, The link table entry 2111 contains the control information 2
113 and link information 2115 are included. The control information 2113 is the link information 2
With the key to be converted to determine which index in 115 to follow
You can. The exact nature of the control information 2113 and link information 2115 depends on the link text.
Is determined by a search algorithm of the conversion table 2109 to which the cable 2107 belongs.
. The data table entry 2119 stores the key 2120 and the data 2121
Including. If the key to be converted matches the key 2120, the
Data 2121 includes key translations, eg, queue numbers for VPI / VCI pairs. The conversion table 209 stores the search algorithm number 21 in the preferred embodiment.
25. The search algorithm number is the component in the conversion table.
Virtual table number 2127 for specifying the table 2106 and the conversion table 2
Algorithm Specifier 2 for specifying the type of search algorithm used with 09
129 are identified. The virtual table number is TLE30
1 decodes to table pointer 2105 for component table
The component table 2106 is identified by the number. Virtual table number
Channel processor and organizational processor
More component tables 2106 than table memory 207
And change the table pointer 2105 represented by the virtual table number.
One component table 2106 to another component table
To be exchanged with. For example, execution processor 313 may
Component tables can be built, channel processors and organizational
Sessors use a specific component table to determine the virtual table number.
The table pointer 2105 in the register in the TLE 301
Ring bus message with writereg command 2415 to change to
Just send a page and you can replace a specific table with a new table.
Wear. The specific conversion table 209 has a maximum of four component tables 2106.
Built from. One of the component tables is a data table 2117
The other table is the link table 2117. In FIG.
The translation table 209 shown includes two component tables:
There is a link table 2107 and a data table 2117. Component
The table is identified by its virtual table number in the translation table descriptor 2124.
Be identified. The conversion performed by the hashing algorithm uses the conversion table 209.
Can be seen as an example of how to convert a key into data. Hashing a
Algorithms are well known. It does this by replacing the bits of a long column with the bits of a shorter column.
Mapping to bits. In this case, the bits in the long column are the key,
The shorter column bits are the index of the table entry. Hashing
The algorithm is a conversion text that contains only the data table component 2117.
Cable 209. Data Table Component 2
When 117 is set, the data table entry 2119 stores the data for that.
Key is hashed, and the data table entry for that key is hashed.
Is indexed by the hash algorithm where possible (i
), Otherwise the first available following index i
Index is created. The key hashed to the index i is changed to a subsequent key (
Called i). When key (i) is provided to the hashing algorithm,
The algorithm returns index 2114 (i). DT corresponding to the key
If E2119 is at index 2114 (i), the search ends, otherwise
Hash collision, that is, two or more keys have the same index (i).
Thing. In this case, the DT whose key hashes to the same index (i)
Data table 2117 so that ES has an index following 2114 (i)
Is set, and as a result, the search algorithm uses the index 2114 (i)
Beginning with the key 2120 in the next data table entry 2119
Compare, key 2120 finds a key that matches the key, or does not match
If so, this is continued until the end point of the data table 2117 is reached. At the end
If it does, report no match. If you want a faster speed,
Set up link table with LTE for index 2114 where collision occurs
And apply an index to the linked table after a collision has occurred.
You. The link table indexes the entry corresponding to the index in the DTE.
Will be given a job. The table lookup engine 301 responds to ring bus messages.
In response, the search and maintenance operations relating to the search table 209 are executed. table·
The lookup engine 301 has a hashing algorithm, a binary trie
Algorithm (binary trie algorithm) and Patricia tri algorithm
Search using a variety of search algorithms, including the algorithm (Patrcia trie algorithm).
Do. Table maintenance uses lookups and table entry indexes.
Executed. In general, messages identifying table maintenance operations are
Provided from the server 313. Ring Bus Message: FIG. 28 All interactions between TLE 301 and other components of DCP 203
Via a message on the bus 311. XP 313 is a ring bus message
The packet processor sets and maintains the conversion table 209 by using the
The item to be converted is sent to the TLE 301 using the ring bus message, and the
Numeral 301 returns a conversion result using a ring bus message. FIG.
4 illustrates a ring bus message in a preferred embodiment. Message 2801 is
Has two main components, data 2817 and control 2803
. The data can be any type of 64-bit data. Ring Ba
If the message is addressed to TLE 301, data 2817 contains the TLE command.
Including. The TLE 301 executes the command and reports the result to the source of the TLE command.
Is returned in the data 2817 of the ring bus message delivered to. Control 2
803 has the following fields: M field 2805 is set by hardware and the message is 64 bits
Be included in the sequence of messages in consecutive slots.
• The TY field 2807 indicates the type of the message;
There are: Unoccupied: the ring bus slot does not contain a message; the message is an indication; the message is a confirmation; the message is a request; the message is a response. LEN field 2809 indicates the length of the message in data 2817; SEQ field 2811 allows the order of the response messages to be determined
The DEST field 2813 is a sequence number that can be set by the sender as described above.
Indicates the device; • The SRC field 2815 indicates the source device. The type of the indication and confirmation message depends on the link of the device connected to the ring bus.
Used to determine if the bus interface is functional
Not just. When a device receives an indication message from another device, it sends a confirmation message to that device.
Return the message. Equipment on the ring bus is used for other equipment
If an operation is desired, a request message is sent to the device. Other devices
Performs the action, sends the result back to the sender device using the result message
I do. As described above, the table lookup is executed by the table lookup.
The intended channel processor sends a request message of the request type and
In the channel processor, source itself and destination TLE301
To specify. Data 2817 includes a TLE command for the operation,
811 allows the channel processor to identify the response message
Is set to the value TLE301 executes the TLE command of the message and executes
By sending the result of the request to the channel processor in the response message.
Respond to messages. The result is in data 2817, where TLE uses itself as the source
, And also designates the channel processor as the destination, and SEQ2811
With the values in the di. FIG. 24 shows that the table lookup engine 301 connects the ring bus 311
Table lookup operation that responds when receiving a command via
This is a list of commands. Each command has a row in the table. The first row is a frame
The second column specifies its ID number, and the third column specifies the data it returns.
The fourth column shows the effect of the command. Table lookup is FindR
Command 2409 is executed, and the remaining commands are set in conversion table 209.
Configuration and maintenance, initialization of table lookup engine 301 and TLE function
Used for testing whether or not The command determines how the entries in the table are positioned and
Depending on the operation to be performed on the entry, it can be further subdivided. Key·
The command 2423 specifies the position of the entry using the key: The Find command 2405 takes the key and the algorithm number as arguments, and
Table 209 and the search algorithm specified by the algorithm number
Search data table entry 2119 for data entry 21
Returns the contents of 19 or an error if the key entry is not found
I do. • The FindW command 2407 contains the key, algorithm number, data to be written,
And the offset and length specifiers as arguments;
Search data entry 2119 related to key using algorithm and specify length
Entry starting from the position in the entry specified by the data length to be offset
Write to. FindR command 2409 takes the same arguments as FindW, but key entry 211
Read the data length starting from the offset from 9, and return it. The index commands 2421 and 2425 include a virtual table number and an index.
Use the index to locate the entry in the component table 2106.
Set. Commands belonging to the group 2421 include entries specified in the command.
Read data from the memory and write data to it. Top belonging to group 2425
The command changes the data of the entry specified in the command. Write command 2401 points to component table 2106
Specify the virtual table number to be specified and the entry in the component table
Specify the index, the data to be written, and the part of the data to be written
The mask, the offset to start writing, and the length of the data to be written are used as arguments.
Have Command 2401 writes data as specified in the command
No. The Read command 2403 has the same arguments other than the mask. This frame
Command is the data at the specified location in the specified entry in the specified table.
Read the data and send it back. The XOR command 2411 specifies the specified entry of the specified table.
XOR operation or CRC calculation using the data in the command
Execute In the case of CRC calculation, the CRC is returned. The Add (addition) command 2423 is a specified entry of the specified table.
Adds the data in the command to the data at the specified position in. The register command 2427 is transmitted to the TLE 301 by reading a register (2417).
Write (2415) is performed. Registers are specified by register addresses.
These commands are in the translation table, in the component table 106 and
The information required to locate the code of the search algorithm
Initialize, simply write context information to TLE 301 and read it. An Echo (echo) command 2419 simply returns the data in the command to the sender.
Send. This command is applied to the ring bus 311 and the ring bus in
Used to check whether the interface is functioning properly. A Nop command 2420 is a command that does nothing when executed. The TLE 301 executes the following basic loop: 1. Read commands from the ring bus; Execute the command; and3. Return the result via the ring bus. When the command is an operation related to a table, the next stage is executed in the execution stage of the command.
Includes: a) determining the index of the table entry; and b) the action indicated for the data at the specified location in the table entry.
Perform the work. For commands containing keys, the index of the table entry is
Determining includes the following steps: i. Convert the key to a first index value; ii. The key stored in the translation table entry specified in the index value
Remove; iii. If the key matches the retrieved key, go to step v; iv. If not, calculate new index according to search algorithm
Go to step ii; and v. Operate on the data stored in the table entry specified by the index value
Execute FIG. 22 shows the internal architecture of the table lookup engine 301.
Show. The ring addressed to the table lookup engine 301
A bus message is received at ring bus node 2201. In the message
Command is the command processor 2203 and the table lookup engine
Process 301. Information required for processing
Is stored in the register storage unit 2205, and the program for the algorithm is controlled.
It is stored in the storage unit 2215. FIG. 23 shows details of the register storage unit 2205 and the control storage unit 2215. Description
For this purpose, four types of registers of the register storage unit 2205 will be described. That is,
Algorithm setting register 2301, table setting register 2311, virtual table
File setting register 2341 and message context register 2319
is there. The algorithm setting register 2301 stores the algorithm used in the command.
Table 209 in the control storage unit 2215 and the hash code 23
23. For each of the tables 207 currently used by the TLE 301
Algorithm configuration register (ACR) 230
1 and the index of ACR 2301 (i) is the algorithm number 312
5 FIG. 23 shows one ACR 2301 (i). Specific ACR2301
Is the virtual table number of the component table constituting the table 207
Is included. LVT12325 is a virtual table for the first index table.
LVT22327 is a virtual table for the second index table.
LVT32329 is a virtual table for the third index table.
Table number. Finally, the DVT 2333 provides a virtual table for the data table.
Table number. HASHF # 2331 is a hash used for virtual table search.
Function number. The component table setting register 2311 stores the component table in the SRAM 207.
Describe the Nent table 2106. In each component table 2106
Is the CTCR 2311 (i), and the index of the table 2311 is that of the table
It becomes a logical table number 2343. Each CTCR 2335 has a table type 2
335, the size of the table entry 2337 and the table in the SRAM 207
Of the start point 2339 of FIG. Finally, the VTCR 2341 is currently used
Describe the virtual table that is present. Each table number 2127 has one VTCR 2341
VTCR 2341 (i) of a specific virtual table number has VTCR 2341 (i).
) Physical table of the component table currently specified by VT # 2127.
Cable number 2323 is included. Component represented by specific VT # 2127
To switch the event table, PT # 2 of VTCR2341 corresponding to VT # 2127
323 may be changed. The message context register 2319 stores the current table lookup.
Associated with the ring bus message being processed by the
Including data. There are four message context registers, TLE3
01 can process four ring bus messages simultaneously. Waiting method
Messages are stored in the input FIFO 2202 or on the ring bus 311 itself
Is done. FIG. 23 shows only one message context register, the message
Page context register 2319 (k) is shown. Each message
Context register 2319 has three types of data therein. Ie
, Message information from ring bus message 2321, table look
Generated and used during processing of a ring bus message within the up engine 301.
2329 including the processing information 2327 and the current processing result. Processing is over
When finished, the origin of the message whose result is processed in the ring bus message
Will be returned to The message information 2321 is transmitted together with the command type and the command.
The information that is attached, the processor that is the source of the ring bus message, and the message
Contains the sequence number of the message. The processing information 2327 includes the algorithm code 2
323 and the last link text retrieved by the search.
Table entry 2111 and the link table entry to be fetched next.
And the address in the SRAM 207 of the bird 2111. The result 2329 is
Contains information on execution results. For the FindR command, the result shows that the command is the key
Data that specifies to read from related data table entry 2119
, Or null if the data table 2111719 for that key is not found.
Value is included. Returning to FIG. 22, the components 2203, 2207, 2213, 2209,
2211 and 2219 are stored in the control storage unit 2215 and the register storage unit 2205.
Constructed by accessible processing elements. Component 2209
Is read from the table memory 207 via the SRAM memory controller 2217.
Component 2219 can execute the table memory 2
07 via the SRAM memory controller 2217.
Can be. Message destined for TLE 301 is on ring bus 311
And the ring bus node 2201 puts the message at the end of the input FIFO 2202.
The command processor 2203 reads the forefront of the FIFO 2202.
Command processor 2203 converts information from the message into a set of message
It is stored in the context register 2319 (i). This message context
The set of strike registers 2319 (i) indicates that the other components
Used when executing a command. The functions of the components are as follows: The initial index generator 2207 is a set of context registers 2319
Generate initial index of component table entry from key (k)
The address generation component 2209 calculates the component
Generates the address of the table entry and the component table entry
The compare and fetch register component 2219 includes a context register
Retrieve the key stored in the set of 2319 (k); SRAM data latch 2219 compares the retrieved key with the stored key
, Data table entry 21 for the key stored based on this comparison
It is determined whether 19 has been found. If found, the data table
And retrieve the ring bus menu with the contents of the data table entry.
Send the message to the output FIFO 2221; otherwise, the link table
Fetch the entry and place it in the context register 2319 (k)
Processing continues with index generation 2213; index generation component 2213 is retrieved with stored keys
Using the link table entry, the next table entry 2111 (1
), And the index is stored in the context register 231.
9 (k); the address generation component 2219 uses it to
Generate the address of a table entry. Take a ring bus message including the findR command 2409 as an example, and
If alg # in the command specifies a hashing algorithm, the command
The processor 2203 is in the context register 2319 (k) for the message
When the message information 2321 is set in the
Execute the hashing algorithm with the key from the command to obtain the value l. Ad
The address generation 2209 uses the l to generate the data table entry 2119 (l).
The address is calculated, and the SRAM data latch 2219 takes the entry 2119 (l).
Start. If the key field 2120 contains a key, a search is performed and the SR
AM data latch 2219 contains a data field containing data in data field 2121.
Create a response bus response message. Otherwise, index generation 221
3 increments the DIX 2114, and the address generation 2209 sets the address of the next DTE 2119.
Generate the source, retrieve it, and perform the above test. Its key fields
If a DTE 2119 whose 2120 matches the key is found or the data
Execution continues in this manner until the end of the bull is reached. Other Uses of the Table Lookup Engine 301 As will be apparent from the presence of the XOR 2411 and Add 2413 commands, TLE
301 can do more than maintain a table and verify information in it. Pake
Each processor has a certain maximum waiting time for the TLE 301.
In general, TLE301 and conversion table
Incoming packets being processed by the packet processor using memory 207
Can store and process contextual information about
And the relatively small amount of DM that the packet processor can use
The constraints imposed by EM 405 can be overcome. To perform address translation
The information required for is one example of such context information. In addition, another package
Information needed to verify the correctness of the packet transmitted as the payload of the packet.
There is information. The verification of the correctness of the packet is performed by checking the cyclic redundancy code (CRC: cyc
lic redundancy code). CRC is used when creating a packet.
When the packet arrives at its destination, the CRC is recalculated and the packet is
Compared to the CRC included in the packet. If they are the same, the packet is
There is a very high probability of arriving without being returned. If not, the packet has been forged
The likelihood is equally high. In the latter case, the packet is dropped and the packet retransmitted
A message requesting attachment is sent to the sender. SDP 420 is in the incoming packet
Check the CRC of the packet and provide the CRC of the outgoing packet.
Must be able to calculate the CRC of the When a packet is received or output
Many algorithms are known for calculating the CRC during processing in the event that
. As is clear from the above, to calculate the CRC in SDP 420, the packet
CRC information must be maintained for the entire duration of the packet as it passes through SDP420
It is said. The packet for which the CRC is being calculated is smaller than the payload in the transport packet.
Pay for payloads that are high-level packets and belong to different high-level packets.
A transport packet carrying the load is transmitted to or received from SDP 420.
The problem becomes more complicated when pinched by a stream of packets. like this
In such cases, a separate CRC calculation must be performed for each high-level packet.
No. In the DCP IC 203, the problem of calculating the CRC is to process an intermediate result using the TLE.
It is solved by storing. The higher level packet that is calculating its RC
As each part of the packet passes through the SDP, the CPRC 401
Gather the information needed to calculate the CRC between
Link with commands that specify how to apply to the previous intermediate CRC of the
Send a bus message to the TLE 301. The last part of the high-level part
The last ring bus message with that information is sent and TLE3
01 executes the command to complete the CRC calculation. Next, the CPRC 401 reads the result.
Send a read command 2403 to determine whether or not the packet has been falsified
Bus message that TLE 301 sends to the end of the packet with the result
Compare the results returned in the page. [0133] The packet stream context can be stored using the TLE 301.
Another area that can be identified is traffic figures. These numbers are
In response to a ring bus message from the
Can be read by the execution processor 313 and executed by the execution processor 313 or
On the network to which the DCP 203 belongs.
Thus, the DCP 203 can be set according to the current traffic requirements. Details of the queue management engine 305 The queue management engine 305 waits according to the specification by the packet processor.
Descriptor 217 is placed in column 215, also according to the specification by the packet processor.
Fetches the descriptor from the queue. When the packet processor works alone
Usually puts descriptors in two or more queues and takes them out of only one queue
Not issued. When the packet processor is integrated, all packets to be integrated
The processor typically reads from one queue. QME305 is
Status information about the queue itself, involved in other enqueue and dequeue operations
To the packet processor. QME 305 reads the queued descriptor
Or the particular packet processor decides which queue to take next.
Not specified. The queue is stored entirely within the DPC 302 and includes
And / or stored in external queue memory 213 or external queue
Stored and managed in the logging and scheduling unit. In the latter case,
QME 305 sends enqueue and dequeue commands to the packet processor
To the external queuing and scheduling unit for command
Return the results and status information to the packet processor. In this case, the queue is
The method used is, of course, the external queuing and scheduling unit.
Completely dependent on. [0134] The contents of the descriptor are the packet pro- cessor that sends the descriptor to the QME 305 and enqueues it.
The descriptor is completely determined by the processor and the contents of the descriptor
Note that it is fully interpreted by the packet processor. For this reason,
QME 305 is a packet belonging to a switching system in which DCP 203 is one component.
Message transmission between the packet processor and the packet processor
Transfers information to and from the queuing and scheduling units of the department
It is a general system. FIG. 29 shows the QME interface 2 for the channel processor 307 (i).
901, the other packet processors also have the QME3
It has the same interface except that it has its own private connection to 05. QM
Starting from the interface part inside E305, the local
Memory is, of course, part of the global address space 321, and
7 (i). Waiting in the local memory of QME305
Column status information 2902 is included. As shown in more detail below, queue status information 2
902 causes channel processor 307 (i) to determine which wait in QME 305.
Retrieve the descriptor in a matrix and determine its queue status. For this reason,
The CPRC 401 of the channel processor 307 (i) accesses the QSI 2901
, You can determine which of the queues will take the next descriptor.
Wear. For each of the packet processors, a queuing mailbox
Box 2903. CP3 to put or remove descriptors on the queue
07 (i) transmits a queuing command 2913 through the payload bus 317 to the CP 30
7 (i) to the QMB 203. In response to the dequeue command, QME 305
The dequeue message 2907 is transferred via the payload bus 317 to the CP 307 (i
). The dequeue message 2907 contains a description
Retrieves the predicate and the protocol data unit and descriptor that it represents
And information on the state of the queue that has been placed. QME 305 also
Using the spare cycle in the val bus 319, the queuing status report (BQSR
: Queue status reports) 2915, the queue corresponding to the packet processor
To the individual packet processors involved in These reports are
Which queues the processor has been emptied of, and no longer empty
Let me know. These reports provide the local address of the packet processor.
Queue status report (RQSR: receive) of the queue status register 601 in the
ived queue status reports) 2915. Finally, CP307 (i)
Has a queue operation status register, in which the QME 305
Two bits indicating the status of execution of the last queue command received are included. Four
Possible situations are: • executed successfully and / or idling • failed • in use, waiting to start command execution • in use, command execution by QME. Assuming that the CP 307 (i) performs both reception and transmission of a packet, usually,
The source is used as follows: a descriptor for the received packet is created and dequeued.
CP 307 (i) obtains the information necessary for
Is set, the enqueue command is sent to the QMB 2903 of the CP 307 (i), and the QOS
Check 2911 to make sure the mailbox is not in use,
-Start DMA to send command. Descriptor enqueuing operation like this
RQSR2915 is checked periodically, and the
Determine if any of the matrices are not empty. Non-empty
The CP 307 (i) is exactly the same as described for the enqueue command.
Send the dequeue command in the same way. QME305 is decued with DEQM2907.
In response to the command, CP 307 (i) uses the descriptor contained in DEQM2907.
And sends the packet it represents. Using other information included in DEQM2907
Schedules the transmission of the packet represented by the descriptor, or
You can update your own copy of the state. CP 307 (i)
Without accessing the QME 305 portion of the dress space 321,
Be able to do all of the above without burdening bus 319
Please pay attention. Of course, CP 307 (i) tries to write or read
If you need more information about the status of your queue, access QSI 2902
Can be Details of Queue Command 2913: FIG. 30 In the preferred embodiment, the packet processor tells QME 305 the following:
It can be instructed to perform four operations: queuing; putting a descriptor in the queue (enqueue); removing a descriptor from the queue (dequeue); Put the descriptor. Commands related to these operations are transmitted via the payload bus 317 to the QME 30.
5 is sent. Transactions on payload bus 317 have two parts
There are: addresses and data. Queue pieces related to a single queue
In commands, addresses are used to specify operations and queues. This to 3001
Show. Count field (CNT) 3003, transaction number (T #) 3
005 and a pool identifier (PI) 3007
Common to load bus addresses. CNT 3003 is read by transaction
T # 3005 specifies the number of 16-bit quantities to be written or written;
Differentiate transactions to a specific destination by one source; PI 3007
, Buffer pools in BME 315 or buffer pools executed by BME 315
Pool reserved for tagging and queuing performed by QME 305
Specify the destination of one of the numbers. Address where PI3007 specifies QME305
Then, the address further includes an operation specifier 3009 for specifying one of the above operations.
For operations related to a single queue, the queue number 3011 is also included.
. The content of the data portion of the command changes depending on the command. Queue setting command
, The data 3013 is the queue specified in the address 3011
The maximum number of descriptors 217 that can be included in 3015 and the description in 3017
The descriptor pool in the QME 305 from which the child is fetched, and the
A descriptor allowable value 3019 that specifies the number of descriptors 217 not used is specified. Waiting
The queue setting command causes the packet processor, which reads a specific queue, to
The amount of resources allocated to the queue can be changed dynamically in response to changes
. For example, the channel processor 307 transmitting from the queue may output the corresponding output port.
When a traffic burst occurs for a channel, the channel processor 3
07 increases the maximum number of descriptors or descriptor allowed values using the Queue Set command
And at the end of the burst, the channel processor 307 sends the descriptor
And / or the maximum value of the descriptor tolerance can be reduced. For the unicast enqueue command, 2-word data 3021
There is. The first word contains a descriptor weight 3023, which is queued
The amount of data in the DRAM 229 represented by the descriptor is specified. The second word is the finger at 3011
Includes a queued descriptor 217. About the dequeue command
Also has data 3025 of two words. The first word is the description taken from the queue.
The descriptor weight of the predicate 3023 and the total number of descriptor weights of the descriptors still in the queue
A queue weight 3027 and a queue length 2039 which is the number of descriptors remaining in the queue
And The second word is a descriptor taken from the queue specified by 3011
217. A packet processor that receives the descriptor 217 extracted from the queue.
The Sessa uses the information in the first word to queue the processor
From which of them the next dequeue command is issued, or
Issues a queue setting command to change the amount of resources available for use
be able to. The address part is indicated by 3031 and the data part is indicated by 3035.
A multicast enqueue command is issued by two or more packet processors.
Queue the descriptor for transmission. Address part 3031 and address part 3
The only difference from 001 is that the queue level
(QLEV: queue level) field 3033. Queue level
• Field 3033 contains the maximum number for the queue that is to receive the descriptor.
Specify a minimal service or priority level. Command data part 303
5 in the first word indicating which packet processor outputs the queue,
A multicast vector (MCV: multicast vector) 3707 is included. No. 1
The code also includes a descriptor weight 3023 for the descriptor 217 in the second word.
As the data in the command indicates, the multicast enqueue command is
Specify a packet processor and service level instead of a specific queue, and use QM
E305 specifies the specified packet with at least the minimum service level.
The processor places the descriptor 217 in the corresponding queue. The descriptor is actually
Not all queues are copied. This is discussed in more detail below.
I will tell. Receiver sending multicast enqueue command to QME305
The packet processor of BME 315
-A command to set the BT233 counter specified in the command descriptor
Send it. The sender's packet processor uses the multicast
Receives the queued descriptor (shown) and is designated in the descriptor BT233
Each time a PDU is transmitted, the transmitting packet processor counts the BT233 counter.
A command for decrementing by 1 is sent to the BME 315. Details of the Queue Data Structure: FIGS. 31 and 32 FIGS. 31 and 32 illustrate the buffer management engine 305 in the preferred embodiment.
Shows details of the data structure for constructing the queue 215. Features where DCP203 is adopted
Depending on the number and size of queues required for a given situation, the data structure
Are all in the memory inside the DCP 203 or the queuing control data structure is
In the queue memory, the queue itself is in the queue memory 213, or
All queue data structures are in the queue memory 213. Queue 215 is a linked list of descriptor records 3111. All
Descriptor record 3111 is the same size, but its size is
Is set by parameters. The descriptor record contains a plurality of descriptor pools 3109 (
0 ... q), and the size and number of pools are
Depends on quantity. Descriptor records 3111 belonging to a specific queue all have one record.
Must be from predicate pool 3109 (i). In each descriptor record 3111
Contains at least the following fields: • In-use count (IUC) 3139, the descriptor is currently in
Indicates the number of queues to be queued; and • next pointer (NPTR) 3115, keeps track of the next buffer in the queue.
Point. Descriptor sends information about buffer 231 from receiving packet processor
Descriptor record 3111 if used to communicate to the side packet processor
Also includes the following items: Descriptor weight (DW) 3137, Descriptor buffer tag
Indicates the size of the buffer represented by 233; and the buffer tag (BT) 233 and the buffer of the SDRAM 229 represented by the descriptor.
This is a buffer tag for the buffer. Alternatively, the contents of the descriptor 217, and thus the descriptor record 3111, may be
Determined by the source packet processor. For example, the originating packet
Stream where the Sesser is the final destination of the packet is multiple Ethernet nodes
The packet processor in the Ethernet
If the sending packet processor outputs packets to the LAN to which the card belongs
The descriptor 217 contains the buffer specified by the buffer tag 233.
Will contain the Ethernet address of the packet created from the content. Figure
Reference numeral 31 denotes a multicast list record (MCLR) 31
23 pools 3121 are also shown. As explained in more detail below, this
These records are used in multicast. Each queue 215 is represented by a queue record 3103 in the queue list 3101.
It is. The queue list 3101 is a buffer list of the global address space 321.
Processing engine 305, and consequently by the packet processor.
Is read. The queue number 3105 of the queue is its queue in the list 3101
This is an index of the column record 3103. Queue list 3101 contains section 3
107, and each section transmits a packet.
About Sassa. All queues for a particular packet processor are listed 310
In a contiguous set of queue records in section 3107 of one packet processor
Is represented by Setting information in the QME 305 part of the global address space 321
The report contains the base of each packet processor section of the queue list 3101.
Contains address 3108 and the number of queues read by the packet processor
You. As a result, the packet processor knows which queue is which packet processor.
The queue number, the queue record 310
3 can be found. The queue list 3101 is further provided by the QME 305.
Broadcast queuing on which queues a particular packet processor
Used to determine whether to receive a status report 2915. Each queue record 3103 contains the following fields: head pointer (HDPTR) 3113, the front of the queue for recording
Points to the descriptor record 3111 currently present in the record; tail pointer (TPTR: tail pointer) 23113;
Queuing length (QL) 3129, the descriptor record in the queue of the current record
3111 number; ・ Total descriptor weight (TDW) 3131, in queue of record
Sum of the values of the DW fields 3137 of all the descriptor records that have been allocated; ADA: allocated descriptor allowance (ADA) 3133, waiting
A number greater than the number of actual descriptors in the queue allocated to the column; and a queue length limit (QLL) 3135,
specify. The ADA 3133 and the QLL 3135 provide a pool 3809 which is a source of a queue descriptor.
Together with the queue setting command. FIG. 31 shows one queue 215 (0). The queue 215 (0) is a descriptor notation.
Record 3111 (i ... k), and the descriptor record 3111 (i) is at the forefront of the queue.
Therefore, it is indicated in the HDPTR 3113 of the QR 3103 (0), and the descriptor record 311
1 (k) is at the end and is shown in TPTR3117 of QR3103 (0). descriptor
After record 3111 (k), the link descriptor of allocation descriptor record 3111 (q ... t)
The strike 3119 follows. These descriptor records are assigned to queue 215 (0).
However, since it follows the end of the queue 215 (0), it is not part of it. ADA
Field 3133 is a descriptor description that can be included in linked list 3119.
Determine the maximum number of records. When the queue 215 (i) is initialized by the queue setting command, the QME 305
Sets the linked list 3119 of the allocation descriptor record 3111 and sets the head
Counter 3113 and tail pointer 3117 are the first entry in link list 3119.
The queue record 3103 (i) is set to point to the predicate record 3111, and the QL fee is set.
Field 3129 is set to zero. When the QME 305 executes the operation, the QOS register 2
Let 911 mark the situation. The enqueue command is sent to the queue 290 of the packet processor.
3, the QME 305 retrieves the descriptor 217 in the command and
First descriptor record 311 of list 3119 belonging to the queue specified in the command
1, the QL 319 is incremented, and the descriptor record 3111 is written in the descriptor
Record 3111 is updated to point to TPTR 3117. In link list 3119
If there is no descriptor record 3111, QME 305 returns the number specified in ADA3133.
To the strike. Also in this case, the QME 305 operates using the QOS register 2911.
Indicate the situation. Queue of queue 215 before descriptor 217 is queued
If the length is 0, QME 305 broadcasts 2
905 is the queue's packet processor indicating that the queue is not empty.
Send to When a dequeue command is received, the QME 305 sets the head pointer 3113
To locate the descriptor record 3111 at the forefront of the queue, and from there
The descriptor 217 is read, the head pointer 3113 is updated, and the next
Descriptor record 3111 of the file. Also, than allowed by ADA field 3113
If fewer descriptor records 3111 are in list 3119, the previous head description
The child record 3111 is added to the list 3119. Also in this case, the QOS register 291
1 indicates an operation status. The descriptor 217 is returned in the return data of the command.
You. If the dequeued descriptor is the last one in the queue, QME30
5 sends BQSR 2905 indicating that the queue is currently empty. Multicast enqueue operation and dequeue operation: FIGS. 32 and 33 As shown in the description of the queue command, the multicast enqueue command
Allows one descriptor to be used by more than one sending packet processor.
Thus, it allows the packet processor to queue. FIG.
4 illustrates a method for implementing a multicast enqueue operation in a preferred embodiment. Waiting
In addition to the queue in the queue list 3101, the queue management engine 305 has one queue.
The multicast list 3201 is maintained. QME 305 is a multicast
The descriptor 215 received in the queue command is stored in the multicast list 32.
01 in the descriptor record 3111, and the descriptor is the protocol indicated by the descriptor.
All packet processors that are to send
It remains in the multicast list 3201 until it does so. Continuing with the multicast list 3201, this
Represented by a multicast list record 3203 pointing to the first DR 3111 (g) of the
It is. The packet processor still has the protocol data in descriptor 215
DR3 in list 3201 representing the descriptor 215 to which the unit must be sent
111 has one or more multicast list records 3123 associated with it.
You. The multicast list record 3123 relating to the DR 3111 contains a pointer
The strike 3209 is stored. The pointers in the multicast list 3201
Pointer to next DR3111 and to DR311 in unicast queue
Pointers. FIG. 32 shows the pointer of DR3111 (h) in detail. DR3111 (h
) Is placed in the queue by the multicast enqueue command.
As a result, the descriptor 215 is placed in the unicast queue 215 (i), 2
15 (j). For this reason, the DR 3111 (a) in the queue 215 (i)
NXTPTR 3115 of DR 3111 (h) of multicast list 3201
The same applies to NXTPTR 3115 in DR 3111 (k) of queue 215 (j).
. NXTPTR3115 of DR3111 (h) is the first MCLR for DR3111 (h)
Refers to a certain MCLR3123 (r). MCLR3123 (r) has three pointers
. That is, one is a pointer 3211, and the pointer 3211 in the multicast list 3201.
It points to the next DR3111 and the other at 3212 in the queue 215 (i)
11 (h), the third is 3213, DR3 in queue 215 (j).
MCLR 3123 (s) having a fourth pointer 3214 to the DR following 111 (h)
). FIG. 33 shows details of the MCLR 3123. Each MCLR3123 has two queue points
And a queue number (3203) and a queue number (3203).
A next pointer (NPTR) 3205 for the next designated DR 3111 (h);
A next MCLR pointer (NXTMCLR) 3213 that points to the next MCLR for 111
You. To the first MCLR for a particular DR 3111 in the multicast list 3201
, The first QPTR 3301 points to the next DR 3111 in the multicast list
. As can be seen from the above, the DR 3111 (h) is assigned to the preceding DR in each queue 215.
3111 directs the DR 3111 (h) to the MCLR 312 for the DR 3111 (h).
3 by including a pointer to the next DR 3111 in each queue.
It can be a DR in the unicast queue 215. Multicast Enki
The view operation is thus a DR operation on the descriptor 217 placed in the list 3201.
Add 3111 and decide which unicast queue 215 descriptor 217 to put in, depending on the need for unicast queue 215
MCLR3123 is added, and the leading DR31 in the unicast queue is added as shown in FIG.
11 and the tail pointer in the unicast queue 215 is
Set to point to DR3111 in the multicast list and use count 313
9 to indicate the total number of unicast queues with descriptors 217
That is. Unicast queue follows DR3111 in multicast queue
When the DR3111 is queued, the NPTR3205 is transferred to the QPTR330 in the MCLR3123.
Set to 1 to indicate the newly added DR3111. Which Unique QME305
The method for deciding whether to include a descriptor in the last queue is described in more detail below. A dequeue operation by the DR 3111 in the multicast list 3201 is as follows.
Proceed as follows. As long as the busy count is greater than 1, the dequeue operation is multi-key.
Functions as described for DR3111 not on the cast list 3201
However, each dequeue operation decrements the busy count by one and a new tail DR3111
NPTR 3115 is set from NPTR 3205 of QPTR 3301 in the unicast queue.
The only difference is that If the in-use count of DR3111 is 1, dequeue
The operation further sets the use count of DR3111 to 0, and sets its NPTR31
15 is set to point to the next DR 3111 in the multicast list and its MC
Return LR3123 to the free list. Selection of unicast queue in multicast enqueue operation The multicast enqueue command specifies the queue in which descriptors are placed.
Not determined, queued with sending packet processor (MCV field 3037)
Specifies the service level (QLEV3033). specific
Means the queue or service level of the packet that is reading the queue.
It is entirely determined by the manner in which the processor is programmed. Multicast
When executing the enqueue command, the QME 305
Must be converted to a queue number. This is the queue number map shown in FIG.
Performed by ping table (QNMT: queue number mapping table) 3303
Is done. How the transmitting packet processor takes advantage of queuing or service levels
To give a simple example of how to use it, service levels simply define the priority between queues.
If it indicates purely, that is, the higher the number, the higher the priority,
Processor has a specific priority as long as there is a high priority, non-empty queue.
It will not correspond to a queue having a rank. The queue number mapping table 3303 contains information on each packet processor.
3307. This part is arranged in order of packet processor number.
It is. Each part 3307 includes an entry (QNMTE) 330 for each service level.
5 In the preferred embodiment, there are eight service levels. Packet
FIG. 33 shows an example of the portion 3307 relating to the processor 0. Here, the service
A simple priority system with higher priority at higher packet levels
The processor 0 uses the service level 0, 3, 4
It is assumed that there is a queue. Packet processor 0 has no queue
Each entry 3305 for a service level has a null value. Packet pull
Each entry 3305 for a service level for which processor 0 has a queue has
Includes QROFF. This is the queue for the service level in the queue list 3101
This is the block offset of the queue record 3103 for the column. In addition, ent
The number of queues of the packet processor having the service level of the packet is included. The QNMTE 3305 has a packet processor number and a
It is addressed by the queue level number. Therefore, the address 3309 is
If packet processor number 0 and queuing level 3 are specified,
The entry 3305 whose position is specified is 3305 (0, 3). Entry 330
5 uses the QROFF specified in 3305 (0, 3), the QME 305
To find the first queue record 3103 and the queue level of the processor.
Wear. QME 305 may choose to use the queue, or
The queue specified by another queue record 3103 for the queue having the queue level
You can also select a matrix. Address 3309 is associated with the queue level.
QNMTE 330 with null value indicating that the packet processor has no queue
If 5 is specified, QME 305 generates QNMTE 3305 for higher queuing level.
Raise part 3307 until you find it, and queue at that level as described here
Select Queue management by QME 305: FIG. 34 As described above, queue 215 managed by QME 305
Depending on the password, it is either completely contained in the memory of the QME 305 in the DCP IC 203 or extended.
Queuing and scheduling included in queue memory 213 or external
Management unit. FIG. 34 shows the external scheduling unit.
The following shows examples of settings with and without settings. In this drawing, the flow of the descriptor 217 is
Wide, light gray arrows indicate the flow of protocol data units.
Shown by dashed dark gray arrows. [0158] Reference numeral 3401 includes a queue in a storage directly managed by the QMU 305.
A stand-alone DCP 203 is shown. 3403 includes external queuing and
Shows standalone DCP with added scheduling and scheduling unit 3405
Is done. In such a configuration, external queuing and scheduling
The unit is responsible for the number of queues, queuing levels and
And issues such as multicasting. External queuing and scheduling
QME 305 with QU 305, QME 305 has memory in DCP 203
It just works. Descriptor 2 sent to the external unit 3405 is stored in the memory.
17 for transmission by the transmitting packet processor.
Packet receiving the descriptor 217 sent from the external unit 3405 to the sender
There is a queue for each of the processors. These queuing functions are
Between the external processor and the external queuing and scheduling unit
Is to provide a buffer. At 3407, the two DCPs 203 (0, 1) are connected by the switching organization 222
The setting is shown, and the queue management of both DCPs 203 is performed by the QME 305 of DCP 203 (1).
This is performed by (1). QME 305 (0) communicates with the organization
Waiter read by the organization processor 303 (0) that sends a command to the processor 303 (1).
It only contains the enqueue command for the descriptor 217 to be put on the matrix.
The organization processor 303 (1) transmits the command to the QME 305 (1). QME30
5 (1) puts the descriptor in the queue 215 according to the indication of the command. Queue 21
5 is a packet packet on the transmitting side of either DCP 203 (0) or DCP 203 (1).
This is a queue read by the processor. Packets in DCP203 (0)
Queue status information on the queue read by the processor is set from QME305 (1).
Via the weave processor 303 (1), the tissue 222 and the tissue processor 303 (0)
Is transmitted to the QME 305 (0), and the QME 305 (0)
Set the recipient's QOS register 2911 or wait for broadcast
Send column status report 2915 to recipient. In the dequeue command, the command
Is transmitted to QME 305 (1) as described above, and is dequeued in response to the command.
The returned descriptor is returned to QME305 (0) as described for status information
Then, the packet is returned from the QME 305 (0) to the transmitting packet processor. The protocol data received by one of the packet processors of DCP 203
If the sender unit attempts to send a data unit from the other DCP,
The BME 315 in the DCP to which the processor belongs belongs via the organization processor to the receiving packet processor.
By transferring the buffer tag to Sessa's buffer management engine
, Responding to the request of the transmitting packet processor. The receiving packet processor
Sends the protocol data unit through the organization processor to the sending packet
Respond to buffer tags by sending them to the processor's buffer management engine.
You. The engine then sends it to the sending packet processor. 3409 is similar to 3407, but the queue is managed by QME 305 (1)
Except for the external queuing and scheduling unit 3411
The structure is shown. The queuing command, status information and descriptor are stored in the DCP 20 as described above.
3 (0) and DCP 203 (1), but QME 305 (1)
To the external queuing and scheduling unit 3411 and
The difference is that the descriptor is received therefrom. 3413, QME305 (0) and QME3
External queuing and scheduling directly corresponding to both
-The structure which has the unit 3415 is shown. Operation is the same as above, except that one QME
305 is an external unit on its own or on behalf of the other QME 305
3415. External Interface of QME 305: FIG. 35 In the preferred embodiment, QME 305 is configured with an external synchronous SRAM memory bank.
Or with the queuing and scheduling unit described above
It has a 55-pin external interface. FIG. 35 shows the external input in each case.
Shows how the interface is used. 3501 has a memory external interface
Show the face. 32 bidirectional data lines 3503 and 20 unidirectional addresses
There are lines 3505 and four or five control lines 3506. Memory bank 21
Reading from and writing to 3 are performed in the usual manner. At 3507, queuing and scheduling of the 55-pin external interface
And a method for use with the switching unit 3508. Also in this case, 32 interactive data
Data line 3509, 16 command lines 3511, and 8 control lines 3513.
You. As far as the interface is concerned, QME 305 is the master and scheduler 3508
Is a slave. Both scheduler 3508 and QME 305 send messages to other
QME 305 determines the direction in which the message is sent. Me
The flow of the message transfer is controlled. That is, scheduler 3508 and QME3
05 are able to receive messages from each other,
That the recipient can accept the message.
Otherwise, the sender will not send the message. QME305 is an interface
Clock signal source. The message has four possible sizes: 12 bytes; 4 bytes of which are commands, 8 are data and 2 clocks
Sent within a cycle; 24 bytes; 8 of which are commands, 16 are data, and 4 clock cycles
36 bytes; 12 of which are commands, 24 are data, and 6 clocks
48 bytes; 16 of which are commands, 24 are data, and 8 clock
Sent within the cycle. The size of the message is determined when the DCP 203 is initialized. message
Of course is determined by the dialogue between QME 305 and scheduler 3508.
However, in many cases, the queue is
Alternatively, the descriptor 217 extracted from the queue managed by the scheduler 3508 is
Including. [0164] Flow control is such that the QME 305 acts on behalf of all sending packet processors.
Each of these packet processors schedules at specific moments.
To receive or not receive the descriptor from the ruler 3508
Is somewhat complicated. In the preferred embodiment, the most
There are about 25 queues. 16 channel channels, one for execution processor 313
One for each of the processors 307 and eight for the tissue processor 303.
The organization processor 303 is responsible for all communications through the switching organization 222
Therefore, they have eight queues.
Contains control information as well as protocol data units. In addition, different species
Devices that require a type of frame may be connected by a single tissue processor.
is there. When used with an external scheduler 3508, the QME 305 has one receiver
There is a queue (RQ: receiver queue) 3519 in which the QME 305
Packet packet to the receiver 3508 before it can be output and queued.
Put all of the descriptors 217 received from the processor. QME305 sends
Transmit queue (TQ) 35 for each of the side packet processors
21. When TQ3521 for the transmitting packet processor is full
, QME 305 has a descriptor 21 for the queue of its transmitting packet processor.
7 can no longer be received. Since there is only one output queue, a message addressed to scheduler 3506 is output.
Flow control is simple. Scheduler can accept messages
When the signal is activated, the signal is activated by the control 3513 and the scheduler flow control register 351 is activated.
7 indicates the state of the signal, and the QME 305 indicates that the control register 3517 indicates it.
All that is required is to wait for the next message to be sent. Turned to QME305
The message flow control is performed by the DCP flow control register 3 in the scheduler 3508.
535. This register contains the possible sender packet processor
Include 25 flow control bits, one for each. DCP flow control register
The flow control bits for the transmitting packet processor in the
Only if so, the scheduler 3508 determines that its final destination is a specific sender
Send a message that is a packet processor. QME305 is the scheduler 3
The portion of each message that is sent to
Used to set or clear, the QME 305 is
Set bit for transmitting packet processor when 521 is full
Send the message, and if transmission queue 3521 again has room for the descriptor
Send a message to reset the bit. An external interface of the QME 305 is generally used for communication with a queue management device.
But need not do so. The contents of the descriptor are the packet
The external interface is completely determined by the
Used by the Sessa to transfer data to devices accessible via an external interface
And / or read data from the device.
One way to take advantage of this feature is to have the packet processor "packet sniff".
File, which simply collects information about the packets in the packet stream.
Is to program as a device. Each packet from the packet stream
The RxSDP 421 is programmed to extract the desired information about the
This can be sent to the CPRC 401. The CPRC 401 puts information into descriptors,
The descriptor is transferred to an external device capable of storing and analyzing information by QME3.
05 can be queued for distribution. Details of the scheduler external interface: FIGS. 36 and 37 FIG. 36 shows how the individual pins of the external interface are
Indicate how to use. In FIG. 8, a row denoted by a pin 3601 is a single group.
The number of pins constituting the loop indicates the number of pins, and the arrows in the column marked direction 3603 indicate the information flow.
This indicates the direction. DCP → SCHE shows the flow from QME 305 to scheduler 3508
DCP ← SCHE indicates the opposite direction. Start with eight control pins 3513; clock pin 3605 clocks from QME 305 to scheduler 3508
D_flow_ctrl 3607 provides 3 bits of flow control information from QME 305
Provide each cycle to the scheduler 3508;
Using the 6 bits of D_flow_ctrl 3607 received in the first two cycles of
, Set or clear a bit in the D flow control register 3515; S_flow_ctrl 3609 is a
QME 305 uses the value of pin 3609 to control the S flow control
Xfer_rqst 3611 sets a message to the QME 305
Xfer_ctrl 3613 is a signal that is activated by scheduler 3508;
The QME 305 has a scheduler 35 to indicate how to interpret
08 are two bits to be sent; details will be described later. Command pin 3511 is bi-directional; it includes 16 command bits and
One parity bit is included. Data pin 3509 is also bidirectional; 3
Two data bits and one parity bit are included. The operation of the interface 3507 is controlled by Xfer_ctrl3613. 2
The meaning of the four values of the three lines is as follows: 00: not a clock cycle followed by a message;
The first two cycles required to send the message
D_flow_ctrl 3607 transfers flow control information to scheduler 3508 during
10: Two messages after scheduler 3508 to QME 305 after two cycles
The first cycle is the clock cycle that follows; needed to send the message
During the first two cycles, D_flow_ctrl 3607 schedules the flow control information.
11: two clock cycles followed by two clock cycles, followed by two clock cycles
In this, the flow control information is sent to the scheduler 3508 via the D_flow_ctrl 3607.
Information is forwarded. As can be seen from the above, when no message is being transferred,
6 bits of flow control information every 2 clock cycles with potentially QM
The data is transferred from the E305 to the scheduler 3508. A 6-bit value indicates disabled operation
The specified value and the scheduler 3508 send the
Separate flow control bits for each of the 25 queues of the receiving packet processor
And a value that responds by setting or resetting. As described above, messages are 2, 4, 6 or 8 cycles long and each
Cycle transfers 16-bit command data and 32-bit descriptive data
. The meaning of the command data is determined by the scheduler 3508 and the QME 305.
Determined by the method of ramming. However, the scheduler 3508 sends the QME 30
5, the first cycle of command data at 3514
It must take the form shown. That is, the first 6 bits correspond to pattern 3
615 and the last six bits do not contain the number of the queue to which the message is addressed
Must. This number is, of course, the message
Determine if you have been. FIG. 37 shows an interface 350 using two-cycle and four-cycle messages.
7 shows an operation example. The two cycle message is shown at 3701. In 3703,
The clock cycle for the interface is shown. 3613
The value of Xfer_Ctrl 3613 during the cycle is shown. 3511 contains the command
• What is at the data pin 3511 is shown. 3509 includes descriptor data
What is at pin 3509 is shown. 3607 includes D_flow_Ctrl pin 360
7 are shown. Thus, in cycle 1, Xfer_Ctrl 361
3 is set to 01 and the next subsequent cycle (cycle 3) is scheduled from QME305.
First cycle of two-cycle message 3702 addressed to Jular 3509
Is shown. In cycle 2, Xfer_Ctrl 3613 is set to 00.
The next cycle may not be the first cycle of the message.
Is shown. In cycle 3, command 3511 and data 3509 are transmitted in the first cycle.
D_flow_Ct, including command data and descriptor data of the
rl3607 is flow control data on scheduler 3508 for the first cycle
including. Xfer_Ctrl3613 is set to 01 again, and schedule from QME305
That the first cycle of another message to the
And In cycle 4, the latter half of message 3702 is sent and command 3511
And data 3509 include command data and descriptor data for the second cycle.
Only, the D_flow_Ctrl pin 3613 contains the flow control data for the second cycle. Xf
er_Ctrl 3613 is set to 00 again. In cycles 5 and 6, the second menu
A message is sent and in cycle 5, Xfer_Ctrl 3613 starts in cycle 7.
Indicates that a third message will follow. Two Four-Cycle Messages 37 from Scheduler 3508 to QME 305
07 is shown at 3705. In cycle 1, Xfer_Ctrl 3613 is set to 10.
Indicates that the first message starting in cycle 3 is addressed to QME 305
. In cycles 2-4, the message is 4 cycles long, so Xfer_Ct
rl3613 is set to 00. In cycles 3-6, for the first message
Command data 3511 and descriptor data 3509 for four cycles of
You. D_Flow_Ctrl 3613 is the first two cycles of the message,
It is transmitted only in vehicles 3 and 4. Xfer_Ctrl3613 returns to 10 in cycle 5
Set, the first cycle of the second message begins in cycle 7. Transmission of flow control information to scheduler 3508 is a two-cycle message
Works the same as sending, but with Xfer_Ctrl 3613 two times from the start of the flow control sequence.
The difference is that it has the value 11 before the cycle. In cycle 3, the first three of the flow control information
Bits are sent on D_Flow_Ctrl 3607 and in cycle 4 the next 3 bits are sent
Be trusted. Scheduler 3508 and QME 305 provide command data 351
Ignore 1 and the value of descriptor data 3509. Detailed description of the buffer management engine 315 and the buffer memory 229 The main function of the buffer management engine 315 is that the protocol data unit
A buffer stored from when received by the DCP 203 until it is transmitted to the DCP 203
This is to manage the buffer 231 of the memory 229. The following description is based on
Buffer memory 33 that the file management engine 315 provides to the packet processor.
9 interface, then interface details and BME 315 run
And other functions will be described. FIG. 38 shows the buffer memory 2 created by the buffer management engine 315.
29 shows an interface to the E.29. Buffer memory 229 is a preferred embodiment.
Are divided into a maximum of 32 buffer pools 3803. n is the number of pools
Then, buffer 231 is included in n-1 of these pools,
1 includes a protocol data unit 2503. pool of n-1
The size and the number and size of the buffers 231 are determined when the DCP 203 is initialized. 1
One pool has a maximum of 64K buffers, and all of the buffers 231 are the same size
Which, in the preferred embodiment, is between 64 bytes and 64K bytes
. Each pool 2803 is identified by a pool ID 3819, and each buffer in the pool is
Keys are identified by buffer tags 233. In buffer 233, the position is
Specified by offset 3802. Here, the offset is the PDU 3804
Identify the starting point. In the preferred embodiment, the offset is 16 bytes of data.
Identify the starting point of the chunk. The nth buffer pool 2803 has buffer tag 2 for that buffer.
33 are included. buffer pool for each of the n-1 buffer pools 2803
There is a tag queue 3805. Buffer for buffer pool 2803 (i)
The tag queue 3805 (i) is stored in the buffer pool 2803 (i).
Buffer 231 including buffer tag entries 3806 for each of
The buffer tag entry 3806 (i, j) of 1 (i, j) is
1 (i, j) buffer tag 233. Each queue 2805 is a queue
A pointer 3807 to the forefront and a pointer 3809 to the tail of the queue
And When the DCP 203 is initialized, a queue is set. Receive DCP203
Buffer for pool 2803 (i) buffer for receiving packet processor
If you need a tag, pick it up from the front of queue 3805 (i)
take. When the sending packet processor releases the buffer tag, the tag is
It is returned to the end of the queue 3805 (i). [0177] Of course, the multicast command assigns a particular buffer tag (i, j).
Put the accompanying descriptor in two or more queues 215 in the queue management engine 305
, The buffer tag (i, j) is the last core tag of the buffer tag (i, j).
Until the p is returned, it cannot be returned to the end of the queue 3805 (i).
This problem is, in the preferred embodiment, a problem with the buffer tag counter 3811.
Will be dealt with more. Buffer touches in two or more queues 215 in QME 305
Entry 3813 in the buffer tag counter 3188 for each of the
And its entry contains the count of the queue in which the buffer tag is currently
It is. This entry is addressed by pool ID and buffer tag
can do. The receiving processor sends a multicast enqueue command for the descriptor
Once created, a message is sent to the BME 315 indicating the number of queues with descriptors.
Send it. Descriptors received by the sending packet processor include the
Includes the INC value from DR3111. If INC is greater than 0, the packet
The processor sends the counter decrement to the BME 315, and the
Notifies that the BTAG counter should be decremented. When the counter decrements to 0
, Buffer tag 233 returns to the end of buffer tag queue 30 待 805
Is done. The BME 315 writes to the buffer 231, reads from the buffer 231,
Maintain buffer tag, return buffer tag, payload bus 317
And decrement an entry in the BT counter from the packet processor via the
Receive a command to The command to read / write the buffer is 3901 in FIG.
It has the format shown in The fields have the following meanings: • The CNT field 3903 indicates the number of valid contiguous 16-byte quantities being transferred
T # 3905 distinguishes transactions by a particular packet processor
Pool ID 3907 identifies buffer pool 3803 (0 ... n-1); Offset 3909 is the offset in the buffer identified by BTAG 3911
BTAG 3911 identifies the buffer 231 that is reading or writing. The pool ID 3907, offset 3909, and BTAG 3911 are all buffer
The dress 3913 is formed. More details in the payload bus description below
However, whether a command is a read command or a write command
Determined by emerging payload bus cycles. Pool ID value 0 is the BT pool 38
03 (n), and the pool ID 0x1F specifies the command of the QME 305. Reading
In the case of a command, the QME 305 stores the specified amount of data in the specified buffer.
To the requesting packet processor along with transaction # 3905
You. In this way, the requester uses the transaction number to return the returned data.
Data can be tracked as to which request is being served. [0181] The packet processor associates the BTAG 233 in the BTAG pool 3803 (n).
The following BTAG read operations can be performed: allocating BTAG 233; and reading CNT entry 2813 of BTAG 233 in BT counter 211; BTAG write operation is as follows: BTAG 233 initialization; -Release of the BTAG 233 assignment;-Set the BTAG 233 counter to the counter 3811;-Decrement the BTAG 233 counter. The format of these commands is shown in 3915. BT pool ID 3907 is specified by BTAG
BTAG pool 3803 (n), where BTAG is the BTAG pool for which the count is specified.
Field 3911, which is in CNT 3903. Also, offset 3909
Affects the command value 3917 specifying one of the BTAG commands and the BTAG command
And a pool ID 3919 that specifies the buffer pool to which the BTAG to receive belongs.
If the command requires a response, transaction number 3905 is returned with the response.
Sent. Fields are employed in BTAG read commands as follows:
CNT3903 determines the number of BTAGs requested by the packet processor issuing the command.
Show. According to the value, the requester can retrieve 8 pools from the pool specified in the pool ID 3939.
, 16, 24 or 32 BTAGs 233 will be received. BTAG field
3911 is, of course, ignored. BME 315 sends to requester on payload bus
To return the BTAG 233 to the requester. In the counter read command, CNT 3903 is set to 0 and BTAG 39
11 includes a BTAG 233 from which the count value in the BT counter is read, and a pool
The ID 3919 includes the pool identifier 3819 of the pool 3803 to which the BTAG 233 belongs.
No. The BME 315 returns the count value by writing to the requester on the payload bus.
Send. Continuing with the BTAG write command, the value of the BTAG 233 is
Is set to BTE3806. In this command, BTE 380 that CNT is initialized
Specify the number 6. Possible numbers are 8, 16, 24, 32. Pool ID 3919
Specifies the pool 3803 to which the BTAG 233 to be initialized belongs. For this reason,
The incoming buffer tag queue 3805 is also specified. The data allocation release command returns one BTAG 233 to the BME 315 and reuses it.
You. In the command, the buffer to which the BTAG 233 to which the pool ID 3919 is returned belongs
A pool 3803 is designated, and the BTAG 3911 includes the BTAG 233. [0187] In the counter command, the pool ID 3919 is set and the counter is set.
Specify the BTAG 233 buffer pool ID to be
11 designates the BTAG 233 itself. In the counter set command
, CNT 3903 include the value at which the counter is set. QME 315 is
Create a CNT entry 3813 in the BT counter and specify it in the command
Responds to a set counter command by setting it to a value. counter
The set command is sent by the receiving packet processor to the multicast
Send a queue command to QME 305 together with a descriptor for the PDU represented by BTAG 233.
Issued by the receiving packet processor. Counter decrement command
Is the protocol data unit that is multicast when the PDU is sent
Issued by each transmitting packet processor. Counter decremented
Reaches 0, the BTAG 233 to which the CNT 3813 belongs is buffered by the BTAG 233.
Returned to the end of BTQ3805 in the pool,
Entry becomes invalid. Details of execution of BME 315: FIGS. 40 and 41. Writing to buffer 231 and assignment and return of buffer tag 233.
In addition to functioning as an interface, BME 315 also provides a comprehensive interface to SDRAM 229.
Interface. FIG. 41 shows the contents of the SDRAM 229. 4103 B
In addition to TAG and buffer pool 3803 (0 ... n), SDRAM 229 has the following elements:
Includes: ・ Specifies the settings of the memory setting information 4111 and the SDRAM 229; ・ At the time of initialization of the packet processor code and data 4109 and the DCP 203
Contains the code and data that XP 313 loads into the packet processor;
In a kernel processor, code and data are stored in a serial data processor.
Contains code and data used to initialize the server. In the conversion table 4107, the XP 313 stores the conversion table when the DCP 203 is initialized.
A translation table to be loaded into memory 207; RTOS 4101 is a real-time operating system
XP data memory 4105 is used to execute RTOS 4101
Includes data used by the XP 313. The XP 313 stores the data in the RTOS 4101 and the XP data memory 4105 as necessary.
Then, the instructions are extracted into the IMEM 1503 and the DMEMs 1507 and 1508. FIG. 40 is a block diagram of hardware of the BME 315 according to the preferred embodiment of the present invention.
FIG. The BME 315 is connected to the global bus 319 and the payload bus 317.
Combined to both. BME 315 communicates with BTAG and
Receive and respond to buffer commands. BME 315 is a global
Receives a memory read request from the XP 313 on the
Respond to read requests via Initialization of the packet processor is performed in the same way
Is done. Each of the transaction requests that the BME 315 receives over these buses includes
, A command 4004 and an address 3919, and the write command
18 is also included. How the address is interpreted, of course, depends on the command
Depends on the type. Commands are decomposed in a command parser 4003. SDRA
Commands that set M229 are treated differently from other commands. 4001
This command proceeds to the DRAM configuration logic 4035 where the data
Is transmitted to the setting FIFO 4037, from which the data is stored in the DRAM setting register 4030.
Loaded. [0191] Other commands can be used to determine whether these are read or write commands or other commands.
It depends on the command. Other commands go to the command FIFO. Read frame
The address for the command proceeds to the read address FIFO 4013, and the address for the write command.
Goes to the write address FIFO 4021. The data is the write data FIFO 40
Proceed to 17. The data read in response to the command is the data read (READ DAT
A) Go to FIFO4043. These FIFOs are provided between the DCP 293 and the SDRAM 227.
It functions to give the required elasticity to the interface. For addresses,
Address generation block 4011 is used for buffer and address used in BTAG command.
Address to the appropriate format for SDRAM 229. To do this,
The address generation block 4011 determines which buffer 231 in the SDRAM 229 is currently
Include a buffer configuration file that specifies whether the Real as it is now
When it is displayed, the address of the SDRAM 2029 corresponding to the specific buffer address 3913 is displayed.
The dress is determined as follows: SDRAM address = pool base address (pool ID) + ((B tag & B tag mask (pool ID)) >> B tag shift (pool ID) CAT ((offset & Offset mask (pool ID))) From the FIFO, the command, read address and write address are queued, respectively.
Proceed to 4067, 4015, 4025. DR is the first command in the queue 4067
Read by AM CTRL4009. This is because the command is sent to the DRAM setting register 403
9 according to the needs of the current settings, and the necessary control signals are
, SDRAM 229 address driver 4019 and data transceiver 40
Send to 41. The foremost address of the read address queue 415 is sent to the address generator 4027.
Read, which sends this address to the driver 4019, indicating a read operation.
I do. The foremost address of the write address queue 4025 is also an address driver.
4019, the address and the write command are read by the address driver 419.
Given to. At the same time, the data at the forefront of the write data queue 4029 is
-Output to the transceiver 4041 and input it to the SDRAM 229.
Can be. The address generator 4017 provides a PD to the transmitting packet processor.
Because the preparation of U is more time-sensitive than storing the PDU in SDRAM 229,
The priority is given to the address queue 4015. Read operation of data waiting to be written in the write data queue 4029
To avoid the situation where the work is read and the data becomes outdated as a result, BME3
15 is provided with CAM4023. The address is at the end of the write address queue 4025
When written to the tail, an entry for the address is created in the CAM 4023. Address
Is written to the end of the read address queue 4015,
3 is output. If they match, the address in the write address queue 4025 is
The next address in the read address queue 4015 is the address generator.
Empty before being read to 4017. BTAG cache 4031 stores BTAG2 from the front of each of BTAG queues 3805
33. The rest of queue 3805 is in SDRAM 229. About BTAG233
Request to arrive from the packet processor, if possible, the BTAG cache
Satisfied from 4031. Otherwise, the queue 3805 in the SDRAM 229
Are filled from the part of the queue, and the BTAG cache of the queue is
Will be reloaded. The BTCNT 3811 realizes a BT counter 3811. Buffer Tag Cow
The event command sets, reads, and decrements the value in BTCNT 3811. BTA
Each time a G decrement command is received, the CNT value in the BTAG CNT entry is
Is decremented to The PDU read from the SDRAM 229 is output to the read data FIFO 4043. FI
The output from FO 4043 is DRAM setting 4035, BTAG cache 4031 and BT
With the output of the CNT 3811, all proceed to the MUX 4046, where the read data waits.
Output to column 4045 is selected and queue 4045 is placed on payload bus 317.
Output. Details of Ring Bus 311: FIGS. 28 and 42 The ring bus 311 is mainly used by a packet processor to transfer protocol data.
Used to send to TLE301 for conversion and receive the conversion result from TLE301
You. However, the ring bus 311 is stored in any node on the ring bus 311.
It is also used to send messages and receive replies. In the preferred embodiment
, The nodes are the packet processor and the TLE 301. Ring bus 311 provides access bandwidth for messages between nodes of the bus.
It is designed to guarantee and limit latency. The bus is 91 bits wide and 27 bits
The bits are for control information, and 64 bits are transmitted from the transmitting node to the receiving node.
For data sent to the server. Bus time-divided into a variable number of slots
Multiplexed, each slot consists of one core clock cycle.
Each slot is communicated between nodes in a bucket gligade fashion. Currently
The node's slot is unoccupied (ie, ring bus message 28
01 is not included), the node sends a message about one of the nodes in the slot.
Can be written (in other embodiments, a single slot can be
You can write a message about it.) The message is sent when the destination node
Cycle through the nodes until the message is removed from the slot. Each node has in its ring bus 311 a message whose source is a node.
Has 1 to 5 slots. Node does not use more than one slot
Otherwise, these slots do not exist on the ring bus 311. This explanation
As you can see, sending a message from one node to another on the bus
The time required depends on the number of messages on the bus. The upper limit is set by each node.
The time required if you have 5 slots containing messages on the
is there. There are five types of message 2801. The type of each message is
It is indicated by the value of the type field 2807. The node that originated the message
Is indicated by SRC 2825 and the destination node is indicated by DEST 2813
You. The types are: • Unoccupied • Indication, the source asks whether the destination is responding to the ring bus message.
Used to join. Signs do not include data. The destination of the confirmation / sign is used to respond to the source of the sign. Data for confirmation
Is not included. A spontaneous message with a request and data, by which the destination operates. In case
Therefore, a response message with the operation result is returned to the source of the request.・ Response, the destination of the request is performed by the destination of the request,
Message sent with the result of the action taken. FIG. 42 shows a ring bus interface that each node has for the ring bus.
FIG. There are two FIFOs for messages whose destination is a node.
FIFO 4203 contains the request message. FIFO 4209 has its destination as a node
Contains the response message. Both FIFO4203 and FIFO4209 are read by node
It is. The overflow FIFO 4211 indicates that the destination has not yet read the ring
Messages originating from nodes that must continue to circulate on bus 311
Used for When a message destined for a node arrives at that node, the message
The sage is put into the FIFO required by its type. There is no room for that FIFO
If the message continues to cycle. Node Outputs Message on Ring Bus 311 via Buffer 4214
I do. Buffer 4214 contains rbus_in4 containing the request message sent by the node.
202, message from overflow FIFO 4211 and request FIFO 4217
To receive. If the overflow FIFO 4211 is empty, its source is a node.
As soon as a message is received by the node, it is
It is output in the slot where it arrived. If the overflow FIFO 4211 is not empty
, The newly received message whose source is node is overflow FIFO
Message placed at the end of 4211 and at the forefront of the overflow FIFO 4211
Is placed in buffer 4214 and the slot in which the newly arrived message arrives.
Output in the The newly arrived message is empty and overflow FIFO 42
If 11 is not full, the first message in request FIFO 4217 is an empty message.
Enter the slot of the page. Otherwise, before the overflow FIFO 4211
Some messages enter the slot. This mechanism allows other nodes to send
Only when processing a message inside is a node
Make sure you send new messages through. Marking and confirmation are performed by the interface 42
01 is processed at the hardware level and is not queued. Global Bus and Payload Bus The following description of the implementation of these buses will refer to one bus used for both buses.
Start with a description of the structure. Next, the bus itself will be described in detail. Request Bus and Return Bus: FIGS. 43 and 44 In the preferred embodiment, the global bus 319 and the payload bus 317
Is time-multiplexed on a single lower layer bus structure. This bus structure is shown at 430 in FIG.
It is shown in FIG. Bus structure 4301 is a slotted multi-channel, shared arbitration bus
Yes, pipelined to allow overlapping operations. Each operation consists of 5 clocks
Begin with a request to occupy a cycle slot. The bus has a clock speed of 166MHz
Work at degrees. Packet processor 4303, BME 315 and QME 305
All are connected to a bus structure and are referred to herein as bus nodes. [0203] The bus structure 4301 has two parts. That is, if the bus node
A request bus 4305 for making requests and providing addresses and data for the requests;
A return bus 4 used to return the result of the bus request to the requesting bus node
317. The request bus 4305 has three channels. The two are commands
Command / address channel carrying address and global bus activity
Global bus command / address carrying address and command for operation
Channel 4307 and carries addresses and commands for payload bus operation
Payload bus command / address channel 4309, one for global
Data channels that carry data for both global and payload buses
4311. In the preferred embodiment, each of the command-address channels
Each is 32 bits wide and the data channel 4311 is 128 bits wide.
The return bus 4317 has two channels, ie, an interface for returning a request and return data.
Return address channel 4321 carrying the address and return address carrying the returned data.
There is a send data channel 4319. Also in this case, the return address channel 43
21 is 32 bits wide and return data channel 4319 is 128 bits wide.
You. A node that can access the slot to perform a bus operation
Required for operation on one of the command-address channels 4307.
Command and address and required for operation on the request data channel 4311.
And place the data. When the operation returns the data to the requestor, the bus control 4315
Sending a request to the source of the return data on the return address channel,
The address to which the return data should be returned is sent, and the source of the return data is
Data into the return data channel 4319. Bus structure 4301 with nodes
Access to is controlled by the bus control 4315. More details below
However, the bus control 4315 sends a request bus 4305 and return
The bus 4317 provides a guaranteed portion of both bandwidths. FIG. 44 shows how bus operations are performed on nodes. Each slot is
Occupies 5 bus cycles. Command-address channel 4307 or 4
At 309, the information on the bus during the slot cycle is shown at 4402.
Cycle 0: request 4405, specify operation; cycle 0: address 4407, specify operation address; cycle 2: bus grant 4409: bus control 4315 is required during this cycle.
The requesting node returns a signal indicating that the access has been received; cycle 3: acknowledgment 4411: the operation specified in the preceding slot succeeds
Then, the bus control 4315 returns an acknowledgment signal in this cycle. Cycle 4: Address 4413, specifying the second address of the operation. As described in more detail below, the use of an address is defined by the operation
. The operations that a node can execute by the bus structure 4301 generally include two operations.
There is a class of short-term operation to transfer 4-byte data and 64-byte data
It is a long-term operation to transfer. Each class has a read operation and a write operation. Specific
Within lot 4402, one packet processor 4303 reads the class.
Write operation different from the write operation. Short-term operation is a global bus command
Long-term operation is specified on the dress channel 4307 and the payload bus command
Specified on the do-address channel. In FIG. 44, the short-term operation is shown at 4425. In short-term operation, the data
If written, the operation must be on request command-address channel 4303.
The first address of the requested slot 4402 is the write address 4415,
When the data is read, the last address is the read address 4417. write
In operation, a node that has been granted access to request bus 3305 is
4 bytes of data to be written to the address specified by the
The request data channel 4311 in the fifth cycle of 402 is entered. In the case of a short-term read operation, the bus controller 4315 controls the bus for the read operation.
Upon authorization, a request 4421 for the node is made in the fourth cycle of slot 4402.
To the return address channel 4321. The bus controller 4315
Return address for data 4423 in the first cycle of next slot 4402
Into the return address channel 4321, and the node specified in the request 4421 is
The return data 4420 itself is returned in the third cycle of the next slot 4402.
Put into address channel 4321. [0209] Reference numeral 4427 shows a long-term operation. Slot 440 where node requires long-term operation
During two cycles, the node sets the read address 4417 for the long-term read operation to
Place on cycle 1 request address bus. The node is responsible for long-term write operations
Write address 4417 is placed on the request address bus in cycle 4. Long-term write operation
In operation, if access is granted to a node, the request data channel 431
64 bytes of data 4429 to be written to the next slot 4402
Put them in 16 byte chunks of channels 1-4. In the long-term read operation, the node
When access is granted, the bus controller 4315 designates the response node.
Address 432 in the fifth cycle of slot 4402
Put in 1. Also, the address of the requesting node is set to the first size of the next slot 4402.
Into the return address channel 4321 in the vehicle. The responding node must be a valid
A count value 4435 indicating the number of 16-byte chunks in the returned data is stored in the next space.
Put on return address channel 4321 in the second cycle of lot 4402,
The responding node has four 16-bars starting in the third cycle of the next slot 4402.
Return data 4437 on return data channel 4319 in the write chunk
Insert The realization of the global bus 319 and the payload bus 317 on the request and return buses
Current: FIG. 45 FIG. 45 shows that both the global bus 319 and the payload bus 317 have a bus structure.
It shows how it is multiplexed on structure 4301. As is clear from FIG.
Lot 4402 is 5 cycles long and is returned with long data 4429 to be written
The long data 4437 is 4 cycles long, and the short data 44
19 and the returned short data 4420 are each one cycle long. Therefore, as shown in FIG. 45, short-term operation and long-term operation are performed on the bus structure 4305.
Can be duplicated so that each of the requested data channels 4311
Four of the five cycles are used for payload data and the fifth cycle is used.
Cycle for global bus data and the same cycle for return data
Available for channel 4319. In FIG. 45, the global
The short-term operation of building bus 319 is depicted in the upper half of the drawing, and global bus 3
The long term operation of building 17 is depicted in the lower half of the figure. Request command in the center of the drawing
The payload, as indicated in the representation of the address channels 4307, 4309
Slot 4507 starts one cycle earlier than global slot 4504
You. Therefore, long data 4 written for payload slot 4507
429 is short data written for the global bus slot 4503
4419 and short data written for global bus slot 4505
And appears between them. Similarly, the return bus 4317 sends the payload request 4
The long return data 4437 returned for 509
Short data returned for the global request 4505 and short data returned for the global request 4505.
Data channel 4319. Bus Access and Addressing on Global Bus 317: FIG. 45 FIG. 45 shows slots on the global bus 319 and the payload bus 317.
4402 shows a state where 4402 is divided into even-numbered slots and odd-numbered slots. Even slot
The pair of the slot and the odd-numbered slot constitute a 10-cycle period 4502. Even and odd
The number of slots corresponds to the even and odd groups of the packet processor 4303.
Corresponding to The composition of the group is as follows: Perform four global bus transactions during each period 4502
be able to. In even slots: short-term read and short-term write operations; In odd slots: short-term read and short-term write operations. There is a separate token for each of these transaction types. toe
Kun rotates between the packet processors in the group in a circular fashion,
The packet processor with the token is responsible for its operation in the group
Has the highest priority. A transaction whose packet processor has a token.
If no transaction is requested, the requesting packet closest to the token in ascending order
The bus is granted to the processor. Pake to get access to the bus
The maximum wait time of a packet processor is 100 cycles. A file that has a write request
Slots without a packet processor are used by the queue management engine 305 to
Broadcast a queue status report 2915 to the packet processor. In the global bus transaction, the read address 4417 and the write
The write address 4415 is exactly a 32-bit address. Return data channel
The address of the packet processor 4319 is a valid bit,
Followed by a processor identifier, BME315, QME305, which identifies the recipient. Bus access and addressing on payload bus 317: FIG. 45 Bus access on payload bus 317 is related to global bus 319.
And functions as described above. Also in this case, each period 4502 is an odd slot.
And the even numbered slots, and the packet processor
Are assigned to odd and even slots. Again, one period 4
Within 502 are slots for four payload bus transactions.
is there. In an even slot: a long-term read operation and a long-term write operation; In an odd slot: a long-term read operation and a long-term write operation. In the same manner as described for the global bus, there is an advantage between the packet processors.
Tokens are used to determine priorities. However, QME305 and execution
There is no special arrangement for processor 313. For address, long term
The address for the read / write operation corresponds to the payload buffer code shown in FIG.
Mand. Return payload data on return address channel 4321
The address is similar to that of the returned global data, except that the 3-bit
The difference is that it further includes a Zaction number. This is the bus controller 4315
Is the transaction in the payload buffer command where the data is returned
The number is copied from 3905. DCP 203 as a generalized data stream processor The above description shows how DCP 203 can be used in a packet switch
However, DCP 203 can be used in any application where a stream of data is processed.
Will be apparent to those skilled in the art. By integration, DCP203
The channel processor 307 is connected to the serial bit stream, nibble stream.
Can be configured to process data from streams and byte streams,
The organization processor 303 processes data of a stream composed of 32-bit words.
Can be managed. The TLE 301 stores stream context information for each data.
Providing a mechanism to store and process, the QME 305
Stream containing the payload from the packet processor that receives the stream.
To the incoming packet processor and external units connected to the QME 305.
Provides a mechanism to convey information about the payload contained in the stream
I do. The organization processor 303 converts the DCP 203 to another DCP 203, a parallel bus, or the like.
Or switching to the switching organization, thereby allowing data from multiple DCPs 203 to be connected.
A large-scale device for processing data streams.
It can also be combined with other devices that process data streams. [0214] The packet processor is designed to handle all types of data streams.
Can be grammed. Programmable with programmable CPRC401
Combining the SDP420 with DMA and the DMA engine for each processor
Extract the control data in the stream from the payload of the stream,
, And the operation of transferring the payload to the BME 315 can be separated. CPR
Using the data scope in C401, SDP 420 and DMA engine
Processing of control data by maintaining information about the current state of trim processing
Can proceed in parallel with the movement of the payload between BME 315 and SDP 420
, The programming of the CPRC 401 is greatly simplified. The sending pro in SDP420
Pattern and bit count in the input stream to the processor and receiver
And can be programmed to respond to different bypass devices.
Easy setup of send and receive processors to handle different types of streams
can do. Equipment and channels to set SDP to recirculate stream
Configure the processor with high-speed serial streams or nibbles or bytes
Equipment that integrates to handle incoming streams and transmission media with different I / O pins
Equipment that is configured to work with provides additional flexibility. The DCP 203 has a minimum wait for communication between the packet processor and the TLE 301.
Using a ring bus that guarantees time, the BME 315 and the packet processor
A slotted bus that transfers bursts of data for payload transfer during
Transfer and parsing of buffer tags from BME 315 to packet processor
By using the transfer of descriptors between the packet processor and the QME 305,
Address the inherent timing constraints of data stream processing. Packet pull
Coordination between the processor, QME 305 and BME 315 is controlled by these devices.
Realized by a global address space that allows access to local memory
Will be revealed. In the case of a cluster of packet processors, the members of the cluster
Quick access to local memory. The above detailed description is designed for those skilled in the art to process and deliver packets.
For processing data streams in digital communication processor integrated circuits
The best mode currently known to the inventor employing is disclosed. For those skilled in the art,
Individual features of digital communications processors in contexts other than those disclosed herein.
And may differ from those disclosed herein.
You will immediately understand that they can be combined in a way. Those skilled in the art
It will also be appreciated that many different embodiments of this feature are possible. All of the above
The detailed description should, in all respects, be considered as an example and not restrictive.
Should not be considered. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a packet switch in a network. FIG. 2 illustrates a packet switch including the digital signal processor of the present invention.
FIG. 3 is a high-level block diagram. FIG. 3 is a high level block diagram of the digital communication processor of the present invention.
You. FIG. 4 shows the high level of the channel processor in the digital communication processor.
-It is a block diagram. FIG. 5 is a map of a global address space. FIG. 6 is a map of a local memory of a channel processor. FIG. 7 is a flow chart of the processing of a packet received in a channel processor.
is there. FIG. 8 is a flowchart of processing of a packet output by a channel processor.
It is. FIG. 9 shows receive and transmit data scopes. FIG. 10 is a detailed block diagram of a reception processor 421. FIG. 11 is a block diagram of a receive byte processor. FIG. 12 is a detailed block diagram of a transmission processor 427. FIG. 13 is a block diagram of a cluster of channel processors. FIG. 14: Local and shared for a cluster of channel processors
It is a block diagram of a memory. FIG. 15 is a block diagram of an execution processor 313. FIG. 16 is a block diagram of an organization processor 303. FIG. 17 is a detailed block diagram of the Rx and Tx organization data processors.
. FIG. 18 shows a switch created by connecting two DCPs. FIG. 19 shows a switch created by connecting a plurality of DCPs to a switching organization.
Show. FIG. 20: Connecting DCP and another kind of digital switching logic to the switching organization
Shows how a switch is created. FIG. 21 shows details of the table memory 207 in the preferred embodiment. FIG. 22 shows the internal architecture of TLE301. FIG. 23 shows details of a register storage unit 2205 and a control storage unit 2215.
You. FIG. 24 shows commands executed by the TLE 301. FIG. 25: the receiving channel processor 307 (i) and the transmitting channel
The processor 307 (j) cooperates to switch the sequence of transport packets.
Here's how. FIG. 26 shows an example of integration of RxSDP 421 in a cluster. FIG. 27 shows an example of integration of TxSDP 427 in a cluster. FIG. 28 shows a ring bus message. FIG. 29 shows a channel processor interface for QME305.
Show. FIG. 30 illustrates the queuing commands employed in the preferred embodiment. FIG. 31 shows a queue data structure in a preferred embodiment. FIG. 32 illustrates a multicast data structure in a preferred embodiment. FIG. 33 shows details of the MCL 3123 in the preferred embodiment. FIG. 34 shows various settings for managing a queue. FIG. 35 shows an extension interface of QME305. FIG. 36 shows details of a scheduler extension interface. FIG. 37. Timing of messages on the scheduler interface
Indicate FIG. 38 shows a logical overview of buffer management. FIG. 39 shows details of a command of the BME 305. FIG. 40 shows details of hardware of BME 305. FIG. 41 shows details of the contents of the SDRAM 229. FIG. 42 shows details of the ring bus node interface. FIG. 43 shows that a global bus 319 and a payload bus 317 are constructed.
Shows the bus structure to be used. FIG. 44 illustrates long and short operations for the bus structure of FIG. 43. FIG. 45 shows an execution example of the global bus 319 and the payload bus 317.
The details are shown below. FIG. 46 shows details of various settings for configurable pin logic 443. FIG. 47 is used to configure pins and receive and transmit processors.
Indicates the register to be used. [Procedure amendment 2] [Document name to be amended] Drawing [Item name to be amended] All drawings [Correction method] Change [Contents of amendment] FIG. 2 FIG. 3 FIG. 4 FIG. 5 FIG. 6 FIG. 7 FIG. 8 FIG. 9 FIG. 10 FIG. 11 FIG. FIG. 13 FIG. 14 FIG. FIG. 16 FIG. FIG. FIG. FIG. FIG. 21 FIG. FIG. 23 FIG. 24 FIG. 25 FIG. 26 FIG. 27 FIG. 28 FIG. 29 FIG. FIG. 31 FIG. 32 FIG. 33 FIG. 34 FIG. 35 FIG. 36 FIG. 37 FIG. 38 FIG. 39 FIG. 40 FIG. 41 FIG. 42 FIG. 43 FIG. 44 FIG. 45 FIG. 46 FIG. 47

────────────────────────────────────────────────── ─── Continuation of front page    (81) Designated country EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE), OA (BF, BJ , CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, K E, LS, MW, SD, SL, SZ, UG, ZW), E A (AM, AZ, BY, KG, KZ, MD, RU, TJ , TM), AL, AU, BA, BB, BG, BR, CA , CN, CU, CZ, EE, GE, HR, HU, ID, IL, IS, JP, KP, KR, LC, LK, LR, L T, LV, MG, MK, MN, MX, NO, NZ, PL , RO, SG, SI, SK, SL, TR, TT, UA, US, VN, YU (72) Inventor John F. Brown             Welle, Massachusetts, United States             Slay, Washburn Avenue 30 (72) Inventor James A. Farrell             Herba, Massachusetts, United States             , Olin Lane 3 (72) Inventor Andrew D. Funk             Bock, Massachusetts, United States             Sford, Willow Road 81 (72) Inventor David Jay Hussack             United States New Hampshire             Indam, Lancaster Road 15 (72) Inventor Edward Jay McClellan             Hollis, Mass., USA             Ton, Washington Pass 5 (72) Inventor Donald A Priore             Meina, Massachusetts, United States             Mode, Dix Road 27 (72) Inventor Mark A. Sankey             Act, Massachusetts, United States             Newton Road 90 (72) Inventor Paul Schmidt             Pudding, Massachusetts, United States             Ston, Whittaker Lane 26 F term (reference) 5K030 GA01 HA08 HC01 HD09 KA01                       KA12 KX11 KX23

Claims (1)

Claims: 1. A plurality of data stream inputs and / or outputs for receiving and / or transmitting a data stream; a plurality of data stream processors for processing the data stream, each data stream processor comprising: A plurality of data stream processors coupled to a data stream input and / or a data stream output and having a writable instruction memory containing instructions; and the data stream processor; A receiving processor for sequentially executing predetermined instructions for processing the data stream received from a stream input, and / or sequentially executing predetermined instructions for processing the data stream output to the data stream output. A transmitting processor to execute; Integrated circuit, characterized in that.