AU4071499A - Digital communications processor - Google Patents

Digital communications processor

Info

Publication number
AU4071499A
AU4071499A AU40714/99A AU4071499A AU4071499A AU 4071499 A AU4071499 A AU 4071499A AU 40714/99 A AU40714/99 A AU 40714/99A AU 4071499 A AU4071499 A AU 4071499A AU 4071499 A AU4071499 A AU 4071499A
Authority
AU
Australia
Prior art keywords
digital communications
communications processor
processor
digital
communications
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU40714/99A
Inventor
Thomas B. Brightman
Andrew T. Brown
John F. Brown
James A. Farrell
Andrew D. Funk
David J. Husak
Edward J. Mclellan
Donald A. Priore
Mark A. Sankey
Paul Schmitt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
C-PORT Corp
Original Assignee
PORT CORP C
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PORT CORP C filed Critical PORT CORP C
Publication of AU4071499A publication Critical patent/AU4071499A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/50—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/56—Routing software
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
    • H04L47/2441—Traffic characterised by specific attributes, e.g. priority or QoS relying on flow classification, e.g. using integrated services [IntServ]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
AU40714/99A 1998-05-08 1999-05-07 Digital communications processor Abandoned AU4071499A (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US8470698P 1998-05-08 1998-05-08
US60084706 1998-05-08
US10582398P 1998-10-27 1998-10-27
US60105823 1998-10-27
PCT/US1999/010002 WO1999059078A1 (en) 1998-05-08 1999-05-07 Digital communications processor

Publications (1)

Publication Number Publication Date
AU4071499A true AU4071499A (en) 1999-11-29

Family

ID=26771325

Family Applications (1)

Application Number Title Priority Date Filing Date
AU40714/99A Abandoned AU4071499A (en) 1998-05-08 1999-05-07 Digital communications processor

Country Status (6)

Country Link
EP (1) EP1082668A1 (en)
JP (1) JP2003527755A (en)
KR (1) KR100633755B1 (en)
CN (1) CN100422976C (en)
AU (1) AU4071499A (en)
WO (1) WO1999059078A1 (en)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7649901B2 (en) 2000-02-08 2010-01-19 Mips Technologies, Inc. Method and apparatus for optimizing selection of available contexts for packet processing in multi-stream packet processing
US7032226B1 (en) 2000-06-30 2006-04-18 Mips Technologies, Inc. Methods and apparatus for managing a buffer of events in the background
US7155516B2 (en) 2000-02-08 2006-12-26 Mips Technologies, Inc. Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory
US7058064B2 (en) 2000-02-08 2006-06-06 Mips Technologies, Inc. Queueing system for processors in packet routing operations
US7165257B2 (en) 2000-02-08 2007-01-16 Mips Technologies, Inc. Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts
US7032223B2 (en) 2000-03-01 2006-04-18 Realtek Semiconductor Corp. Transport convergence sub-system with shared resources for multiport xDSL system
US6871257B2 (en) * 2002-02-22 2005-03-22 Sandisk Corporation Pipelined parallel programming operation in a non-volatile memory system
FR2856863B1 (en) * 2003-06-30 2005-08-19 Thales Sa METHOD AND DEVICE FOR MANAGING REDUNDANCY OF A REDUNDANT COMMUNICATION NETWORK
US7924872B2 (en) 2003-08-27 2011-04-12 Thomson Licensing Transport network multiplexing for transport and ethernet packets
KR20060133581A (en) * 2004-02-19 2006-12-26 코닌클리즈케 필립스 일렉트로닉스 엔.브이. An electronic stream processing circuit with test access
EP1647894A3 (en) * 2004-10-12 2007-11-21 NEC Electronics Corporation Information processing apparatus with parallel DMA processes
US7831749B2 (en) * 2005-02-03 2010-11-09 Solarflare Communications, Inc. Including descriptor queue empty events in completion events
US8724636B2 (en) * 2008-03-31 2014-05-13 Qualcomm Incorporated Methods of reliably sending control signal
US9129072B2 (en) * 2012-10-15 2015-09-08 Qualcomm Incorporated Virtual GPIO
US10318305B2 (en) 2013-09-06 2019-06-11 Huawei Technologies Co., Ltd. System and method for an asynchronous processor with pepelined arithmetic and logic unit
US9674086B2 (en) * 2013-11-05 2017-06-06 Cisco Technology, Inc. Work conserving schedular based on ranking
CN105791296A (en) * 2016-03-08 2016-07-20 浪潮集团有限公司 Method for quickly scrambling and descrambling network message
CN105847233A (en) * 2016-03-10 2016-08-10 浪潮集团有限公司 Switch for subfield encryption transmission
CN105978681A (en) * 2016-05-13 2016-09-28 浪潮集团有限公司 Anti-eavesdrop safe switcher
CN112486704B (en) * 2020-11-27 2024-02-06 中船重工（武汉）凌久电子有限责任公司 Multi-core multiprocessor synchronization and communication system based on shared storage

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4314355A (en) * 1977-05-18 1982-02-02 Martin Marietta Corporation Apparatus and method for receiving digital data at a first rate and outputting the data at a different rate
US4935674A (en) * 1988-12-27 1990-06-19 Rca Licensing Corporation Digitally controlled convergence system
WO1994003852A1 (en) * 1992-08-05 1994-02-17 David Sarnoff Research Center, Inc. Advanced massively-parallel computer apparatus
US5526051A (en) * 1993-10-27 1996-06-11 Texas Instruments Incorporated Digital television system
US5870436A (en) * 1997-01-02 1999-02-09 Raytheon Company Uniform discrete fourier transform filter parameter encoder

Also Published As

Publication number Publication date
KR100633755B1 (en) 2006-10-16
CN100422976C (en) 2008-10-01
CN1319209A (en) 2001-10-24
WO1999059078A1 (en) 1999-11-18
EP1082668A1 (en) 2001-03-14
KR20010043460A (en) 2001-05-25
JP2003527755A (en) 2003-09-16
WO1999059078A9 (en) 2000-06-02

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase