JP2003524916A - Encoding method for performing cryptographic processing - Google Patents

Abstract

(57) [Summary] The present invention relates to an encoding method and an encoding device. Data _x i that is digitally stored as data bit words, at least one of the encryption processing by _{k i y i = f i (} x i, k i) is executed, the result or an intermediate result _{y i} as the data bit words Stored digitally or temporarily. Optionally, at least one of the data x _i , k _i and the result or at least one intermediate result y _i are complemented bit by bit according to a random number-based control signal r _i / x _i , / k _i , and / y _Determines whether to compute at least one of _i .

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention is disclosed in the introductory part of claim 1 of the appended claims, wherein at least one crypto-sub-operation y _i = f _i (x _i , k _i ).
To the data x _i , k _i which are stored digitally as data bit words, and digitally store or buffer the associated result or intermediate result y _i as data bit words. It is a thing. The present invention also relates to the encryption device disclosed in the introduction section of claim 8. The cryptographic device comprises a processor and a register R _i , which for the operands x _i , k _i digitally stored as data bit words in the register R _i has at least one cryptographic sub-operation y _i = f _i ( x _i , k _i ) and digitally store or buffer the associated or intermediate result y _i as a data bit word in register R _i .

[0002]

Current cryptographic computation of the Prior Art technique, so as to protect the operation of the data processing device, or the data sent to the device, is executed in a number of data processing devices. The arithmetic operations required for this purpose are performed by standard processors and dedicated cryptographic processors. A typical example of the latter processor is formed by a chip card or an IC card. As shown in FIG. 1, for such cryptographic calculations, it is often necessary to initialize the associated store or register of the data processor whose operands are x _i , k _i . During the i th calculation, the intermediate result y _i is probably stored in a store or register R _i , or afterwards the calculation result is stored in a store or register for another process. The register R _i is located between the preceding i-th cryptographic calculation and the subsequent (i + 1) -th cryptographic calculation. The data x _i , k _i or the intermediate result y _i used in this context typically constitute security-related information such as, for example, cryptographic keys or operands.

To calculate the cryptographic algorithm, the data processor forms a logical combination of operands k _i or intermediate values y _i or x _i , x _{i + 1} . Depending on the technology used, the processing, in particular the loading of data into the storage or registers, will increase the current consumption of the data processing device. Complementary logic, eg C
In the case of MOS, an increase in current consumption occurs when the value of the bit storage cell changes, that is, when its value changes from "0" to "1" or from "1" to "0". This increase in consumption then depends on the number of changed bit positions in the memory or register. In other words, pre-erased register loading causes a current consumption increase proportional to the Hamming weight of the operand (= the number of bits with the value "1") or the number in the Hamming weight. The analysis of the current changes enables the retrieval of information about the operations performed and thus the successful cryptographic analysis of secret operands, such as cryptographic keys. For example, in the case of very small signal changes, multiple current measurements can be made on the data processing device to retrieve the appropriate information. On the other hand, this kind of cryptographic analysis, in which multiple measurements can possibly also enable the required differentiation, is called "differential power analysis (Different
Also known as "ial Power Analysis", this allows outsiders to perform cryptographic work, cryptographic algorithms, cryptographic operands or possibly unauthorized parsing of cryptographic data simply by observing changes in current consumption of the data processing device. I can succeed.

From US Pat. No. 5,297,201, it is known to combine a radio frequency emitting computer with a device which also emits radio frequencies similar to that computer.
As a result, unauthorized third parties can no longer decode the high frequencies emitted by the computer. However, this system cannot prevent cryptographic analysis by a third party who directly accesses the computer.

In order to eliminate the correlation in the chip card between the output of the result of the cryptographic processing or the transfer of the key information for the cryptographic processing and the cryptographic processing itself, Japanese Patent Publication No. 10-06.
From the abstract of Japanese Patent No. 9222, it is known to delay the transfer of the result of the cryptographic process or the key information for the cryptographic process. However, this system can also be analyzed by differential power analysis. The reason becomes clear in the current consumption of the data processing device even for the delayed data transfer.

[0006]

[Problems to be Solved by the Invention]

It is an object of the present invention to overcome the drawbacks described and to obtain an improved method and an improved device of the type described which prevents cryptographic analysis by observing the current consumption of a data processing device.

[0007]

[Means for Solving the Problems]

This object is achieved by a method of the kind characterized as disclosed in claim 1 of the appended claims.

[0008]   To this end, according to the invention, the data x_i, K_iAnd the result or
At least one intermediate result y_iControl based on at least one of
Signal r_iComplementary calculation is performed depending on / y = f (/ x_i, / K_i) And / or / y _i Or not is performed.

This allows other bit sequences to be processed or, in the case of repeated executions of the same cryptographic process, therefore each cryptographic process or each execution of several cryptographic processes is subject to different current changes in the data processing device. Cause Sub result (sub
Irrespective of the actual value of -results), in the case of iterative execution of the whole calculation, each data path is from "0" to "0", from "0" to "1" if it is a pure sequence of random numbers. , "1" to "0" and "1" to "1" the same number of times, or in the case of a pseudo-random number sequence, the same number of changes in practice. However, since the control signal r _i based on random numbers is unknown or not predetermined, there is no correlation between the current change and the data and the resulting bit value, and therefore the differential power Parsing no longer makes cryptanalysis successful. In other words, the average current consumption of the entire device does not contain useful information about intermediate results used in sub-operands or sub-processes.

[0010]   Further advantageous further aspects of this method are disclosed in claims 2-7.

It is preferable to form one or more XOR combinations (exclusive OR combinations).

[0012]   The data includes, for example, at least one of an encryption key and an operand.

The intermediate result y _i is preferably buffered in the register R _i during the execution of the subsequent cryptographic sub-processing and used as the operand x _{i + 1} for the subsequent cryptographic sub-processing.

If the data x _i , k _i of the preceding sub-processing _i were bit-wise complemented to form the original value which was not inverted after each sub-processing, the preceding sub-processing The complement of the bit string x _{i + 1} = y _i extracted from the intermediate result y _{i of i is set} to / x _{i + 1} for each bit.

[0015]   In a particularly advantageous way, the data bit word x_i, K _i Or y_iAt least one bit value of, especially even and odd bit values
, Or invert all bit values. Then the data bit word x_i, K _i Or y_iBit value or bit address of
It is especially possible to invert by an XOR operation (EXCLUSIVE OR operation).
It is profitable.

[0016]   The above-mentioned device according to the invention can be controlled by a control signal and the data x_i, K _i And the result or at least one intermediate result y_iWork for at least one of
At least one inverter that triggers, a random number generator that generates random numbers, and a random number
Based on the control signal r_iAnd a device for generating the
Control signal r_iDepending on the bit string x_i, K_iOr y_iFor each bit
Is complemented to_i, / K_iAnd / y_iOr keep them immutable
I will do it.

This has the advantage that other bit sequences are processed or stored in the case of the same cryptographic process, and thus other current changes occur in the data processing device during each execution of the cryptographic process or multiple cryptographic processes. Is brought about. Irrespective of the actual value of the sub-result, in the case of repeated execution of the whole calculation, each data path is "0" to "0", "0" to "1" in the case of a pure random number sequence. , From "1" to "0" and from "1" to "1" the same number of times, or in the case of a pseudo-random number sequence, the same number of changes in practice. However, whether the control signal r _i based on random numbers is known,
Since it is not predetermined, there is no correlation between the current change and the data and the resulting bit value, and thus the differential power analysis no longer makes a successful cryptographic analysis. In other words, the average current consumption of the whole device is
ub-operands) or sub-processing does not contain useful information about intermediate results.

[0018]   Further advantageous embodiments of this device are described in claims 9-14.

In the preferred embodiment, at least one register R _i is followed by an inverter which receives the same control signals as the inverter for the data x _i , k _i preceding the i th sub-process. The inverter following the register Ri of the i-th sub-process is
It is preferably combined with an inverter for the input data x _{i + 1} preceding the th sub-process. It is preferred that the combined inverters receiving a control signal r _i of the i-th sub-processing the preceding, after the control signal r _{i + 1} of the (i + 1) th sub-process.

[0020]   The data includes, for example, at least one of an encryption key and an operand.

In the preferred embodiment, a register R _i stores the intermediate result y _i of the preceding i th sub-process between the preceding i th sub-process and the subsequent (i + 1) th sub-process. , This intermediate result is sent to the next sub-process as the input value x _{i + 1} .

The bitwise complementing operation preferably inverts at least one bit value of the data bitwords x _i , k _i or y _i , in particular even bit values, odd bit values or all bit values.

[0023]

In a first preferred aspect of the encryption method of the embodiment of the invention] As shown in the preferred embodiment Figure 2 The present invention, the overall cryptographic process, one or more exclusive in that XOR (EXCLUSIVE
OR) performed by a series of sub-processes f _i (x _i , k _i ) such that a combination is formed. The figure shows two sub-processes, i-th sub-process 10 and i + 1-th sub-process 12. Each sub-process is executed by the arithmetic unit. Each sub-process 10, 12 is followed by a storage cell or register R _i 14 and a storage cell or register R _{i + 1} 16, respectively. Sub-processes 10, 12 have as their input values data x _i , x _{i + 1} and operands k _i , k _{i + 1,} which may be data bit words.

[0024]   Data x before each sub-processing 10, 12_i, X_{i + 1}Each control for
Possible inverters 18, 20 and operand k_i, K_{i + 1}Controllable for
Inverters 22 and 24 are provided respectively. Furthermore, each sub-process 10, 1
2 to the associated register R_i14 and R_{i + 1}16 followed by intermediate result y_i, Y _{i + 1} Controllable inverters 26, 28 are provided. Intermediate result
Fruit is related register R_i14 and R_{i + 1}Input to subsequent sub-processing 12 by 16
Data x_i, X_{i + 1}Each is transmitted as. Inverters 18-28 are selected
The associated control signal r to the associated data bit word depending on the selection_i, R_{i + 1}To
In accordance with this, it is determined whether or not the complement is taken for each bit, and the control signal r_i, R_{i +1} Can be controlled respectively. Then all of the subprocess's
Inverters 18, 22, 26 and 20, 24, 28 have the same control signal r_i,and
r_{i + 1}Receive each. In other words, related to the inverters 18 to 28
The inverters 18 to 28 are executed in such a way that the input value is executed or the input value is not processed.
Of the additional control signal r_i, R_{i + 1}By it
Each is done. This arrangement of registers 14, 16 between sub-processes 10 and 12 is
Sub-process 10, 12 is 1 so that sub-results must be buffered
It is especially used when it is calculated sequentially by two identical units at a given time.

The control signal, depending on the value of the random number, the sub-process produces the original result y = f (x, k) or the bit-inverted result / y = / f (/ x, / k). Thus, it is controlled by a random value from a random number generator. Therefore, the calculation and the register R _i 14,
The accumulation of data in R _{i + 1} 16 is done with the original value or the bit-inverted value. Therefore, in the case of iterative execution of the whole calculation, each data path is converted from "0" to "0", "0" to "1", "irrespective of the actual value of the sub-result.
That is achieved by changing the same number of times from "1" to "0" and from "1" to "1". Therefore, the normal current consumption of the whole work is
Contains no useful information about the sub-operands k _i or intermediate results y _i contained in The inverters 26, 28 after the registers 14, 16 are again in the next subprocess 1
Regain the original, non-inverted value for 2.

The second preferred aspect of the inventive cryptographic method shown in FIG. 3 corresponds to the first aspect shown in FIG. 2, the only difference being the inverters 26, 28 after the registers 14, 16. Are associated with each inverter 20 of the next stage 12 so as to form an inverter 30.

The inverters, for example, invert only part of the bit values of the associated data bit word. For example, even bit words, or odd bit words,
Alternatively, only the bit address is inverted. The bit value is inverted by, for example, an exclusive logical sum XOR (EXCLUSIVE OR) operation.

[Brief description of drawings]

[Figure 1]   The flowchart which shows a part of encryption process by the present technology.

[Fig. 2]   6 is a flowchart showing a portion of the first preferred aspect of the cryptographic process of the present invention.

[Figure 3]   6 is a flow chart showing a portion of a second preferred aspect of cryptographic processing of the present invention.

[Explanation of symbols]

10 i-th sub-process 12 i + 1 sub-process 14 Register R _i 16 Register R _{i + 1} 18 x _i Controllable inverter 20 x _{i + 1} controllable inverter 22 k _i Controllable inverter 24 k _{i + 1} controllable Inverter 26 y _i controllable inverter 28 y _{i + 1} controllable inverter 30 combined inverter

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE), JP, US F-term (reference) 5J104 AA47 JA04 NA02

Claims (14)

[Claims] 1. At least one cryptographic sub-processing y _i = f _i (x _i , k _i ) is performed on and associated with data x _i , k _i which are digitally stored as data bit words. An encryption method for digitally storing or buffering a result or an intermediate result y _i as a data bit word, wherein at least one of the data x _i , k _i and the result or at least one intermediate result y _i is selected. , An encryption method characterized by performing a complement operation for each bit depending on a control signal r _i based on a random number to determine whether or not the complements / x _i , / k _i , and / y _i are obtained. 2. One or more exclusive-or XORs (EXCLUSIVE) during cryptographic sub-processing.
An encryption method according to claim 1, characterized in that an OR combination is formed. 3. The encryption method according to claim 1, wherein the data includes at least one of an encryption key and an operand. 4. The intermediate result y _i is buffered in a register R _i between executions of subsequent cryptographic sub-processes and used as an operand x _{i + 1} for subsequent cryptographic sub-processes. 4. The encryption method according to any one of 1 to 3. 5. The complement of the bit string x _{i + 1} = y _i derived from the intermediate result y _i of the preceding sub-process i, if the data x _i , k _i of the previous sub-process _i are complemented bit by bit. 5. The encryption method according to any one of claims 1 to 4, wherein is set to / x _{i + 1} for each bit. 6. Inverting at least one bit value, in particular even bit value, odd bit value, or all bit values of a data bit word x _i , k _i or y _i during bitwise complement processing. The encryption method according to any one of claims 1 to 5. 7. An exclusive-or operation XOR (EXCLUSIVE) of bit values or bit addresses of data bit words x _i , k _i or y _i during bitwise complement processing.
7. The encryption method according to any one of claims 1 to 6, wherein the encryption is performed by an OR operation. 8. A processor and a register R _i , the processor comprising at least one cryptographic sub-process y _i for operands x _i , k _i which are digitally stored as data bit words in a register R _{i of the} cryptographic device. = F _i (x _i , k _i ) and an associated cryptographic or cryptographic device that digitally stores or buffers the associated result or intermediate result y _i as a data bit word in register R _i , controlled by a control signal At least one inverter capable of operating on at least one of the data x _i , k _i and the result or at least one intermediate result y _i , a random number generator for generating a random number, a device for generating a control signal r _i is provided, controllable inverter, depending on the control signal r _i, bit sequence x A cryptographic device, characterized in that each of _i , k _i or y _i is a bit-wise complemented value / x _i , / k _i and / y _i , or they remain unchanged. 9. at least one register R _i, data x _i that precedes the i-th sub-process,
9. An encryption device according to claim 8, characterized in that it is followed by an inverter receiving the same control signal as the inverter for k _i . 10. The cipher according to claim 9, characterized in that the inverter following the i th sub-process is combined with an inverter for the input data x _{i + 1} preceding the later (i + 1) th sub-process. Device. 11. combined inverters the prior control signal r _i of the i-th sub-process of, after the (i + 1) -th claim 10, wherein the receiving the control signal r _{i + 1} sub-process Encryption device. 12. The encryption device according to claim 8, wherein the data includes at least one of an encryption key and an operand. 13. An intermediate result y _i of the preceding i-th sub-process is stored by the register R _i between the preceding i-th sub-process and the subsequent (i + 1) -th sub-process, and the intermediate result y _i is stored. The encryption device according to any one of claims 8 to 12, wherein the encryption value is sent as an input value x _{i + 1} to a subsequent sub-process. 14. The bitwise complement operation comprises inverting at least one bit value, in particular even bit value, odd bit value, or all bit values of a data bit word x _i , k _i or y _i. The encryption device according to any one of claims 8 to 13, which is characterized in that.