JP2003524248A - Method and apparatus for preventing cache data eviction during atomic operations and maintaining high snoop traffic performance - Google Patents

Abstract

(57) [Problem] To provide an apparatus and a method capable of performing snoop filtering while an atomic operation is not completed. An apparatus of the present invention has first and second request queues and a cache. The first request queue tracks cache access requests, and the second request queue tracks snoops to be filtered. The cache has a dedicated port for each request queue, the first port dedicated to the first request queue is a data and tag read / write port that can modify both data and tags on the cache line, and a second request port. The second port dedicated to the queue is a tag only port. Since the second port is a tag-only port, the snoop filter link can be continued while the cache line is locked without fear of modification of the data associated with the atomic address. Also includes an atomic address block that prevents eviction of cache addresses during atomic operations.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a method and apparatus for maintaining cache data eviction and maintaining high snoop traffic throughput during atomic operations.

[0002]

[Prior art]

FIG. 1 illustrates in block diagram form a typical conventional multiprocessor system 30. The system 30 includes a number of processors 32a, 32b, 32c coupled to a main memory 36 via a shared bus 35. Each processor 32 has its own non-blocking cache 34, which is N-fold set-associative. Each cache index includes a tag to identify the data and the memory address associated with that data. In addition to this, a coherency bit is associated with each item of data in the cache to indicate the cache coherency state of the data entry. According to the MOSI cache coherency protocol, each cache data entry is one of four states: M, O, S, or I. The I state indicates an invalid state. Owned state, O, indicates that the data associated with the cache index is valid, has been modified from the in-memory version, is owned by a particular cache, and another cache has a shared copy of that data. Indicate that you will. A processor having a request line in the O state responds to a request from another processor with data. The shared state, S, indicates that the data associated with the cache index is valid and one or more processors share a copy of the data. The modified state, M, indicates that valid data has been modified since it was read into the cache and the other processor does not have a copy of it.

The cache coherency state helps determine if a cache access request is a miss or a hit. A cache hit occurs when one of the states in the cache index contains a tag that matches the requested address and a cache coherency state that does not indicate invalid data. A cache miss occurs when none of the tags in the index set match that of the requested address, or the matching tag is in a state that contains invalid data. FIG. 2 illustrates how the MOSI cache coherency state transitions in response to various types of misses. MOSI
The events that cause transitions between states are IST, ILD, FST, and FL, which are initials.
It is shown using D. "ILD" used here is an internal load,
That is, it indicates a load request from the processor associated with the cache. Similarly,
“IST” indicates internal storage. "FLD" indicates an elsewhere load that caused a transition, ie, a load request to the cache coming from a processor that is not associated with the cache. “FST” indicates the memory of another place.

“Snooping” refers to the process by which one processor in a multiprocessor system determines if a cache elsewhere stores a desired item of data. As used herein, snoop represents a potential future request for eviction on a particular address, eg FLD or FST.
Each snoop indicates the desired address and operation. Each snoop is a broadcast to each processor 32 in the system 30, but only one processor 32 responds to each snoop. Responsive processor 32 is associated with cache 34 which stores data associated with the desired address. Each processor 32 in system 30 includes an external interface unit (EIU) that handles snoop responses.

FIG. 3 is a block diagram form of the EIU 40 and its bus 35 and cache 3.
Binding to 4 is shown. The EIU 40 receives the snoop from the bus 35. EIU40
Transfers each snoop to the cache controller 42 and stores the snoop in the request queue 46 until it can be filtered. Snoop filtering involves determining if a snoop hits or misses in cache 34 and directs it to EIU 40. In the configuration of FIG. 3, under the best of circumstances, the latency between receiving and responding to the snoop by the EIU 40 is very long. Snoop wait times are usually, for example, unfinished atomic operations,
In response to another outstanding cache access request, increase from its theoretical minimum. Atomic operations are computational tasks that must be completed without interruption. Processor 32 typically performs atomic operations as two sub-operations on a single address. A sub-operation on an address that follows another operation without interruption. One atomic operation is, for example, an atomic load. This is a load followed by immediate storage at the same address without interruption. To protect the data associated with an atomic operation while the atomic operation is pending, most snoops are for addresses other than those associated with the pending atomic operation, but some processors do snoop filtering. Abort. Two elements are needed for this approach. First, the cache contains a single data and tag read / write port, which allows modification of both the cache line data and the tag in response to a hit. Second, most processors respond to snoop hits by immediately initiating data eviction. This is not allowed during an atomic operation, so all access to cache 37 is suspended while the atomic operation is incomplete. However, the latency of atomic operations is so long that the EIU 40 is forced to back throttle the snoop. Other operations will also snoop, regardless of the address at which the processor should be snooped.
Will stop filtering. Therefore, there is a need for improved methods and apparatus for filtering snoops independently of other outstanding access requests.

[0006]

DISCLOSURE OF THE INVENTION

One embodiment of the present invention provides an apparatus that allows snoop filtering while atomic operations are being performed. The device includes first and second request queues and a cache. The first queue keeps track of cache access requests, while the second queue keeps track of snoops that still have to be filtered. The cache contains a dedicated port for each request queue. First
The port is dedicated to the first request queue and is a data and tag port,
Allow modification of cache contents. In contrast, the second port is dedicated to the second request queue and is a tag-only port. Since the second port is a tag only port, snoop filtering can continue snoop filtering during atomic operations without any fear of modifying the data associated with the atomic address.

Another embodiment of the present invention provides a method and apparatus for preventing flushing cached data during atomic operations. This device includes a first request queue, a second request queue, and a second request queue.
Includes request queue and atomic address block. The first request queue stores an entry for each cache access request. Each entry includes a first set of address bits and an atomic bit. The first set of address bits represents the first cache address associated with the cache access request, and the atomic bits indicate whether the cache access request is associated with an atomic operation. The second request queue stores an entry for each cache eviction request. Each entry in the second request queue includes a second set of address bits indicating a second cache address associated with the cache eviction request. The atomic address block prevents eviction of the third cache address during atomic operations on the third cache address. During the first clock cycle, the atomic address blocks receive and parse a first set of signals representing the first entry in the first queue to determine if they represent an atomic operation. If so, the atomic address block sets the third set of address bits to a value representing the first cache address. During the second clock cycle in which the atomic operation is being performed, the atomic address block determines if the second set of address bits represents the same cache address as the third set of address bits. , Receiving and analyzing a second set of signals representative of the second set of address bits. If so, the atomic address block stops servicing the second request queue, thus preventing eviction of data from the cache where the atomic operation is being performed. Additional features of the present invention will become apparent upon reading the following detailed description of the invention with reference to the accompanying drawings.

[0008]

[Detailed description]

A. Snoop Filtering Circuit Overview FIG. 4 illustrates, in block diagram form, a portion of processor 33 of multiprocessor system 50. Processor 33 improves snoop latency by continuing to filter snoops during incomplete atomic operations. Processor 33
Achieves this improvement by using cache 37, cache access request queue 52, and snoop filtering request queue 54. The cache controller 43 uses the cache access queue 52 to keep track of native or internal cache access requests and the snoop filtering request queue 54 to filter snoops. At each clock cycle, even during execution of atomic operations, cache access request queue 52 and snoop filtering request queue 54 couple requests to a dedicated port of cache 37. Since the port of the snoop filtering request queue 54 is a read-only port, there is a danger during an atomic operation that the atomic operation modifies the data associated with the address (atomic address) being executed through the read-write port. You can keep it off and continue snoop filtering. When a snoop is hit, the cache 37 notifies the external interface unit 40 so that it can issue a eviction request to the eviction queue 58. In addition to this, the processor 33 includes an atomic address block 56 that protects the atomic address from eviction during atomic operations. The atomic address block 56 is a cache
The start of an atomic operation is detected by monitoring the cache access request from the access request queue 52. The atomic address block 56 then monitors the eviction queue 58 to detect when an atomic address eviction is requested. The atomic address block 56 prevents the atomic address from being flushed by outputting a blocking signal that blocks the cache controller 43 from selecting the flush request from the flush queue 58.

B. Snoop Filtering Circuit Queue Cache access request queue 52 is preferably implemented as a memory device that stores an entry for each outstanding access request to cache 37. FIG. 5 shows the entry 60 of the cache access request queue 52. The maximum number of entries that the cache access request queue 52 can support is a design choice. Entry 60 contains information about a single outstanding cache access request, and includes address bit 63, tag bit 63,
Includes atomic bit 64, Ld / store bit 65 and valid bit 66. Address bit 62 and tag bit 63 are the memory bits that the request seeks to access.
Specify the address. Atomic bit 64 indicates whether the cache access request is a sub-operation of the atomic operation. Ld / store bit 65 indicates whether the cache access request is for a load or store operation.
Valid bit 66 indicates whether the associated entry is valid. The cashier controller 43 controls the contents of the cache access request queue 52.

Cache controller 43 also controls the contents of snoop filtering request queue 54. Preferably, snoop filtering request queue 54 is implemented as a memory device that stores an entry for each outstanding snoop. FIG. 6 shows an entry 70 of the snoop filtering request queue 54. The maximum number of entries that the request queue 54 can support is a design choice. Entry 70 contains information about a single outstanding snoop, and includes address bit 72, tag bit 73, FLD / FST bit 74 and valid bit 76. Address bit 72 and tag bit 73 indicate the memory address the snoop seeks for access. FLD / FST bit 74
Indicates whether the snoop is associated with out-of-place load or out-of-place memory. Valid bit 76 indicates whether the associated entry is valid.

FIG. 11 shows the entry 55 of the eviction queue 58. Ejection queue 58
The maximum number of entries that can be supported by is a design choice. Entry 55 contains information about a single outstanding eviction request, and address bit 57,
And a valid bit 59. Address bit 57 points to the memory address where the eviction is performed. Valid bit 59 indicates whether the associated entry is valid. The cache controller 43 stops the service of the eviction queue 58 in response to the stop signal from the snoop filtering circuit 51.

C. Atomic Address Block FIG. 7 shows, in block diagram form, an atomic address block 56 and its associated cache access request queue 52, snoop filtering request queue 54 and eviction queue 58. The atomic address block 56 includes an atomic address register 80, an address write circuit 100,
It includes a lock bit control circuit 110 and an atomic hit decision circuit 130.
The address write circuit 100 and the lock bit control circuit 110 are
The access request queue 52 monitors cache access requests bound to the cache 37. When the cache access request includes the first operation of the atomic operation, the address write circuit 100 makes the atomic address atomic.
Stored in address register 80. The lock bit control circuit 110 responds to the same environment by locking the atomic address to prevent access to outstanding data during atomic operations. During the unsuccessful atomic operation, the atomic hit detection circuit 130 monitors the eviction request from the eviction queue 58. During atomic operations, servicing of eviction requests is allowed except for eviction requests for atomic addresses. When a eviction request hits an atomic address during an atomic operation, the atomic hit detect circuit 130 outputs its stop signal to stop the cache controller 43 from servicing the eviction queue 58.

Atomic address register 80 is preferably implemented as a memory device that stores an entry 90 for each atomic operation that allows processor 33 to be outstanding at the same time. In the preferred embodiment, the processor 33 is
Allow only one atomic operation to be outstanding at a time. FIG. 8 shows an entry 90 of the atomic address register 80. The entry 90 is
Includes address & tag bit 92 and lock bit 94. Address & tag bit 92 identifies the location in cache 37 at which the atomic operation is currently outstanding. Lock bit 94 indicates whether the atomic address is accessible. Lock bit 94 is output when a cache access request associated with the first sub-operation of an atomic operation is bound from cache access request queue 52 to cache 37. The lock bit 94 will not be output at the completion of the second sub-operation of the atomic operation. Therefore, lock bit 94 also indicates the validity of atomic address register 80.

Referring again to FIG. 7, the lock bit control circuit 110 includes an atomic
Controls the state of lock bit 94 of address register 80. Lock bit control circuit 110 monitors the signal coupled to cache 37 on line 112 by cache access request queue 52. The signal on line 112 represents a single entry 60 of the cache access request queue 52. If line 112
If the above signal indicates that the cache access request represents the first sub-operation of the atomic operation, lock bit control circuit 110 indicates lock bit 94 to indicate that the atomic address is unavailable. To fix. On the other hand, if
If the signal on line 112 indicates that the cache access request represents the completion of the second sub-operation of the atomic operation, the lock bit control circuit indicates that the atomic address is available, i.e. the entry key 90 is no longer present. Not valid,
Modify lock bit 94 to indicate

Atomic hit detection circuit 130 prevents the data associated with an atomic address from being evicted during an atomic operation. Atomic hit detect circuit 130 extracts the atomic address stored in atomic address register 80 on line 53 representing address bit 57 of a single entry 55 of eviction queue 58 (see FIG. 11). Identify the eviction request for the atomic address by comparing with the signal. If the two addresses match while the atomic address is locked, the atomic hit detection circuit 1
30 outputs a stop signal coupled to cache controller 43 on line 138. The cache controller 43 responds to the output of the stop signal by stopping the selection of the eviction request in the eviction queue 58. The cache controller 43 restarts the servicing request service when the stop signal is no longer output. The atomic hit detection circuit 130 does not output the stop signal when the atomic operation is completed.

D. Address Write Circuit FIG. 9 shows the address write circuit 100 in block diagram form. Address write circuit 100 is preferably implemented as a series of parallel latches 104, each having only one associated logical AND gate 103, although only one is shown for each. Each latch 104 stores a single bit of an address and tag pair. Each latch 1
The D input of 04 is the address and tag of the cache access request queue 52.
Combined with one of the lines 102b, which represents a bit of a bit. The enabling input of latch 104 is controlled by the output of logical AND gate 103. The logical AND gate 103 is for the current cache cache from the cache access request queue 52.
Latch 10 whenever the access request represents a valid request for an atomic operation.
4 is possible. In other words, the logical AND gate 103 causes the signal on line 102c representing the valid bit 66 and the signal on line 102a representing the atomic bit 64 (
Whenever (see FIG. 5) is active, its output is activated. Thus, the signal on line 102b is latched by latch 104 when the signals on lines 102a and 102c indicate a valid request for the atomic operation being serviced.

E. Lock Bit Control Circuit FIG. 10 shows the lock bit control circuit 110 in block diagram form. Lock·
The bit control circuit 110 includes a logic multiplexer (MUX) 150 and a selection control circuit 152. The output of MUX 150 on line 114 is the atomic address
Determines the state of lock bit 94 to be written into register 80. Input I
When 1 is selected, MUX 150 indicates that lock bit 94 should be locked. On the other hand, when input I0 is selected, MUX 150 drives a signal on line 114 where lock bit 94 is to be unlocked. Selection control circuit 1
52 uses the first selection control circuit 151 and the zero selection control circuit 156 to select between the inputs I1 and I0. The first selection control circuit 151 controls when the I1 input is selected by controlling the S1 signal on line 155. First selection control circuit 15
1 is implemented as a pair of logical AND gates 153 and 154. Logical AND
Gate 153 outputs its output signal to represent the first sub-operation of an atomic operation when its input signal on lines 112a and 112d indicates that the cache access request is being serviced. Logical A when the cache coherency state of the atomic address is M and the current operation is the first sub-operation of the atomic operation
The ND gate 154 outputs the output signal S1. Otherwise, the first selection control circuit 154 does not output the S1 signal. Input I0 of MUX 150 is S on line 157
Zero selection control circuit 156 controls when selected by controlling the 0 signal. Zero selection control circuit 156 includes one zero selection circuit 156a for each entry in the cache access request queue. FIG. 10 shows a zero selection control circuit 1
One example of 56a is shown. When a cache access is complete, the zero select circuit 156a examines its associated entry to determine if the associated cache access request has just completed. Comparator 158 performs this task. If the addresses match, then the cache access request entry 6
If the cache access request entry is associated with the second sub-operation of the atomic operation, as represented by the signal representing the atomic bit 64 of 0 and the Ld / store bit 65, the logical AND 160 outputs the SO signal on line 157. , Which unlocks the lock bit 94 of the atomic address register 80.

F. Atomic Hit Detection Circuit FIG. 12 shows the atomic hit detection circuit 130 in block diagram form. The atomic hit detect circuit 130 signals the eviction request cache hit to the cache controller 43 via the stop signal on line 138. atomic·
The hit detection circuit 130 includes a comparator 170 and a logical AND gate 172. Comparator 170 outputs the address of the eviction request represented by the signal on line 53 to line 92.
Compare with the atomic address represented by the signal above. A mere match between the eviction address and the atomic address does not necessarily mean that the eviction queue 58 should stop. Ejection is stopped only if the atomic operation is still outstanding. The logical AND gate 172 determines if this is the case by outputting its output on line 138, the stop signal, only when the lock bit 94 is output.

Alternative Embodiments Although the present invention has been described in the context of protecting atomic addresses while an atomic operation is incomplete, the description of the present invention is illustrative and not essential to the invention. It should not be understood as limiting. For example, the present invention can be modified to protect addresses that are desired to be locked. It will be appreciated that various modifications may be made by those skilled in the art without departing from the scope and spirit of the invention as defined by the claims.

[Brief description of drawings]

[Figure 1]   The figure which shows the conventional multiprocessor system.

[Fig. 2]   The figure which shows the state of the conventional MOSI cache coherency protocol.

FIG. 3 is a diagram showing a relationship between a conventional external interface unit and its cache.

[Figure 4]   FIG. 3 is a diagram showing a snoop filtering circuit according to an embodiment of the present invention.

5 illustrates a cache access request queue of the snoop filtering circuit of FIG.

6 shows a snoop filtering request queue of the snoop filtering circuit of FIG.

7 is a diagram showing an atomic address register and control circuit of the snoop filtering circuit of FIG. 4;

FIG. 8 is a diagram showing an entry address of an atomic address register used according to an embodiment of the present invention.

[Figure 9]   FIG. 8 is a block diagram of an address write circuit of the control circuit of FIG. 7.

[Figure 10]   The block diagram of the lock bit control circuit of the control circuit of FIG.

FIG. 11   FIG. 5 is a diagram showing a queuing queue of the snoop filtering circuit of FIG. 4.

[Fig. 12]   FIG. 8 is a block diagram of an atomic hit detection circuit of the control circuit of FIG. 7.

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE, TR), OA (BF , BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, G M, KE, LS, MW, MZ, SD, SL, SZ, TZ , UG, ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, B Z, CA, CH, CN, CR, CU, CZ, DE, DK , DM, DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, J P, KE, KG, KP, KR, KZ, LC, LK, LR , LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, R O, RU, SD, SE, SG, SI, SK, SL, TJ , TM, TR, TT, TZ, UA, UG, UZ, VN, YU, ZA, ZW (72) Inventor Kuttanna Belliapa M             United States Texas 78749 Oh             Austin South Mopac 5417             # 224 (72) Inventor Zen Alan             United States California             95135 San Jose Silverland             Drive 3083 F term (reference) 5B005 JJ11 KK14 MM01 NN74 PP22                       PP26

Claims (13)

[Claims] 1. A device for filtering snoops during an atomic operation without stopping, comprising a first request queue storing an entry for each cache access request, the first request queue comprising: Each entry includes an atomic bit and a first set of address bits, the first set of address bits indicating a first cache address associated with the cache access request, and the atomic bit indicating that the cache access request is atomic. A second request queue for indicating whether it is associated with an operation and storing an entry for each snoop to be filtered, each entry of the second request queue including a second set of address bits; The second set of address bits indicates the second cache address associated with the snoop, It has a cache with a first port and a second port, the first port is a dedicated data and tag port for the first request queue, and the second port is a dedicated tag-only port for the second request queue. And the cache allows simultaneous access to the same address by the first and second ports during the same clock cycle. 2. The first port of the cache is a read / write port.
The device according to. 3. The second port of the cache is a read / write port.
The device according to. 4. A method for filtering snoops without stopping access to a cache of a processor performing an atomic operation, the method including a first cache address associated with a first cache address during a first clock cycle. Receiving a first cache access request and a first snoop associated with a second cache address, and determining whether the first cache access request is associated with an atomic operation, and if the first cache access request is an atomic operation If relevant, set the first set of address bits of the atomic address register to the first cache
Setting to a value indicative of an address and filtering the first snoop during a second clock cycle during which the atomic operation is being performed. 5. The method of claim 4, wherein the second cache address of the first snoop is the same as the first cache address. 6. An apparatus for protecting cache data from eviction during atomic operations, the apparatus having a first request queue storing an entry for each cache access request, the first request queue of the first request queue comprising: Each entry includes an atomic bit and a first set of address bits, the first set of address bits indicating a first cache address associated with the cache access request, and the atomic bit indicating that the cache access request is atomic. It has a second request queue that indicates whether it is associated with an operation and stores an entry for each cache eviction request, with each entry in the second request queue being associated with a second cache eviction request.
During the first clock cycle, having an atomic address block that includes a second set of address bits to indicate a cache address and prevents eviction of the third cache address during an atomic on the third cache address. , The atomic address block receives a first set of signals representing a first entry in a first request queue, and a control circuit analyzes the first set of signals to determine whether they represent an atomic operation, If so, the third set of address bits is set to a value representing the first cache address, and during the second clock cycle during which the atomic operation is being performed, the atomic address block is The second set of signals representing the second set is received and analyzed to determine that the second set of address bits is the first set of address bits. Determining if it represents the same cache address as the three sets, and if so, stopping the service of the second request queue. 7. The atomic address block comprises an atomic address register including a third set of address bits and a control circuit for controlling the atomic address register, the first address register comprising:
During a clock cycle, the control circuit receives and analyzes the first set of signals to determine if they represent an atomic operation, and if so, the third set of address bits to the first cache address. And a control circuit receives and analyzes the second set of signals during the second cycle during which the atomic operation is being performed such that the third set of address bits is the same as the third set of address bits. 7. The apparatus of claim 6, determining whether to represent a cache address. 8. An atomic operation is performed as a first sub-operation followed by a second sub-operation, wherein each entry in the first request queue has a cache access request as a first sub-operation or a second sub-operation. 8. The apparatus of claim 7, including a sub-operation bit that indicates whether it is associated with. 9. The atomic address register includes a lock bit,
The lock bit has a locked state and an unlocked state, the locked state of the lock bit prevents access to the address represented by the third set of address bits, and the control circuit controls the first set of signals. The control circuit is configured to set the lock bit to the locked state when the parse represents the first sub-operation of the atomic operation, and the control circuit includes a second set of address bits of the first entry of the first request queue. 9. The apparatus of claim 8 configured to prevent access to the cache address represented by the third set of address bits when represents a same cache address as the third set of address bits. . 10. The control circuit further comprises a lock bit control circuit for controlling a lock bit state, the lock bit control circuit analyzing a first set of signals to determine if the first request queue is Set the lock bit to the locked state if the first entry represents the first sub-operation of the atomic operation, and if the first entry of the first request queue represents the second sub-operation of the atomic operation. 10. The device of claim 9 wherein the lock bit is set to an unlocked state. 11. The control circuit further comprises a write circuit for analyzing the first set of signals, wherein the atomic bit and the first sub-operation bit of the first entry queue of the first request queue are of atomic operation. First
11. The apparatus of claim 10, wherein the third set of address bits is set to represent the first set of address bits for the first entry of the first request queue if it represents a sub-operation. 12. A method of protecting cached data from eviction during atomic operations, wherein an entry for each cache access request is stored in a first request queue, each entry in the first request queue being An atomic bit and a first set of address bits, the first set of address bits indicating a first cache address associated with the cache access request, and the atomic bits indicating a cache bit
Indicates whether the access request is associated with an atomic operation, stores an entry for each cache eviction request in a second request queue, each entry in the second request queue is a second cache associated with the cache eviction request. Analyzing a first set of signals that includes a second set of address bits indicating an address and represents a first entry in the first request queue during a first clock cycle Determine if it represents an atomic operation, and if the first set of signals represents an atomic operation, the third of the address bits
Setting the set to a value representative of the first cache address and parsing the second set of signals representative of the second set of address bits to determine the address bits during the second clock cycle during which the atomic operation is being performed. A second set of address bits represents the same cache address as the third set of address bits, and if the second set of address bits represents the same address as the third set of address bits, then Stopping the service of the second request queue. 13. Saving an entry for each cache access request in a first request queue further comprises setting a lock bit in a locked state for each cache access request associated with an atomic operation to lock the cache access request. 13. The method of claim 12, wherein the locked state of the bits comprises preventing access to the address represented by the third set of address bits.