JP2003521810A - Surface mount IC lamination method and apparatus - Google Patents

Abstract

(57) Abstract: Stack packaged surface mount (SMT) chips with matched top and bottom contacts. The features of the chip have been chosen to be very easy to manufacture and to provide the desired connectivity between chip layers. In one embodiment, additional spacing and routing layers are optionally provided between the layers. In another, the chip is specialized by optionally providing different conductors and / or non-volatile cell configurations. Yet another is to configure a small number of substrate contacts to align with the spacing layer or dielectric region of the substrate to create a very low capacitance signal path between the stacked chips.

Description

Detailed Description of the Invention

(Related Application) This application is related to US Provisional Application No. 60/133, filed on May 7, 1999.
Claims the benefits of No. 019.

FIELD OF THE INVENTION The present invention relates generally to methods and apparatus for increasing the density of integrated circuits (ICs) located on a substrate such as a printed circuit board (PCB), and more particularly, A method and apparatus for stacking chips, including surface mount technology (SMT) chip packages.

BACKGROUND OF THE INVENTION Over the years, manufacturers of electronic and electromechanical systems have known that IC stacking methods and stacked devices can sometimes mount more components on a given area of a substrate. It was For example, US Pat. No. 5,612,570 (199 outside Aid
Filed April 13, 5), one chip is stacked on each of several frames,
Next, the construction of stacking these frames is taught. Signal routing between the chip leads and the frame is provided by lines through these frames.

While many known stacking methods can provide the desired PCB occupancy, the first issue that has not yet been adequately addressed is the vertically aligned group of identical (or very similar) chips. Requires at least as many routings as chip layers (ie, vertically offset horizontal conductors). Each alternating repetition of chip layers and interface structures adds to the cost of handling equipment required to assemble the stack.

US Pat. No. 4,956,694 (filed by Aid et al. On Nov. 4, 1988)
Teaches a configuration in which slightly different LCC chips can be stacked on a small substrate and then mounted laterally on a large substrate. This stacking device relies on small differences between the dies in order to function because the strict co-located IC dies connected in strict parallel cannot individually perform logical functions. A second problem that has not yet been adequately addressed by this technique is that this type of stacker configuration requires that the die be fabricated using different masks and then held in different inventory. Therefore, there is a need for a stacking device that is made with identically made dies and then made into separate chips in later steps of manufacture.

A third problem that exists with this technique is the provision of very long, high capacitance conduits typically between internal circuit elements on different dies. While some conventional stacked configurations happen to reduce the length and capacitance of such conduits compared to electrical paths that include the internal lines of the substrate, all known configurations are either difficult to manufacture or have relatively poor performance. There are difficulties.

SUMMARY OF THE INVENTION A method and apparatus are presented that can solve one or more of these problems. The present invention is useful for stacking packaged surface mount (SMT) chips, which are characterized by conductors extending to the outside of the package, each of these conductors being associated with a substrate on which the stacked device is to be mounted. It is of the type that has a top contact and a bottom contact. The top contact of each chip in the top layer preferably remains completely unconnected, and the bottom contact of each chip in the bottom layer is preferably configured to mate with a planar substrate surface. The preferred method and apparatus of the present invention simplifies manufacturing by leaving the chips, which must ultimately be specialized, in the manufacturing process substantially the same for many years.

The first embodiment of the present invention simplifies assembly by sandwiching any offset conductors or horizontal routing between chips in a stack, thereby allowing fewer interfaces than chip layers. In particular, the present invention provides a laminating method and apparatus. This provides a mechanism for combining the individual signals so that they can be handled by the exact same chip. Detailed examples are shown in FIGS. These include special equipment for testing, heatsinks, singulation, and interface construction.

A second embodiment of the present invention is characterized by the fact that the chips are arranged to be vertically aligned in the stack and specialized by providing different conductor and / or non-volatile cell configurations. And a device. This allows commonality between all dies and packages to be maintained at least until conductors are installed. Detailed examples are shown in FIGS. These include special equipment for controlling substrate connectivity, handling dissimilar chips, handling identical chips, specializing identical devices before or after stacking, and modifying chips using electrical, mechanical or optical means. Including.

A third embodiment of the present invention provides a stacking method and apparatus featuring a small number of chip contacts configured to align with a dielectric layer of a spacing layer or substrate. This allows a very short, low capacitance signal path between stacked chips in a very easily manufacturable configuration. Detailed examples are shown in FIGS. 5, 12, 15, and 17. These include special equipment for assembly, limited horizontal routing on the substrate surface, and in-chip routing.

DETAILED DESCRIPTION While each of the many examples below provides more than sufficient detail for one skilled in the art to practice the invention, the subject matter of the invention is broader than any single example below. However, the scope of the invention is defined explicitly in the claims at the beginning of this specification. Many of the terms used in this specification are provided consistent with their common usage in the art, but some have been described with great peculiarity.

The laminating apparatus of the present invention is configured to be bonded to a substrate. As used herein, "top", "bottom", "top", etc. refer to the substrate that should be "bottom" of this stacker, or the arbitrarily selected "bottom" of this stacker to which this stack should be mounted from the side It is described in the standard.

A “conductor” is a continuous structure or material that has an electrical conductivity that is approximately equal to that of a metal. A "contact" is a surface of a conductor that is configured to contact a portion of another conductor to simultaneously make a physical and electrical connection. As used herein, "contacts" of an IC die refer to these contacts outside the die.

The “internal circuitry” of an IC die includes the resistive and active elements on the die, but excludes fusible links connected very close to normal signal lines and die contacts.

As used herein, “directly coupled” refers to objects that are in physical contact. Two members are said to be "indirectly" physically bonded if they are both directly bonded to the third member or to the binder. The two conductors are electrically coupled "internally" if they extend together in an object such as an IC package, between which there is a continuous conductive path in the object.

As used herein, an IC “package” is a surface mount technology (SMT) package that has a dielectric body with a cavity large enough to accommodate the die for which the package is intended. It also has contacts inside the body for electrically coupling to the die and contacts outside the body electrically coupling with these internal contacts. The packages used in the present invention each have a matching "top" and "top" configured to facilitate chip stacking.
It has several conductors each having a "bottom" external contact. "Matched" pairs of contacts on opposite sides of the package lead do not touch each other.

The IC package of the present invention includes a conventional ceramic or plastic package for use in an IC die. As used herein, the term "package" excludes components traditionally added to the interior of the package (eg, bare die, epoxy coated die, tape-based die carriers such as TAB components, and bond lines), but the package It includes a lid and some routed conductors. Typically each conductor is an internal contact and socket configured to electrically couple to an IC die, a PCB pad, a jumper, or one or more external configured to electrically couple to some other conductor. Including contacts. The external contacts may include, for example, a portion of the surface and a portion of the bottom surface of the seagull wing or flat pack lead.

Each conventional IC package includes a dielectric body having a cavity large enough to accommodate the die for which the package is intended. It also has contacts inside the body for electrically coupling to the die and contacts outside the body electrically coupling with these internal contacts. The surface mount IC package used in the present invention has matched, non-overlapping "top" and "bottom" external contacts to facilitate chip stacking. Conventional packages typically have a simple body shape, such as a rectangular solid, with leads protruding outside. Two IC packages have the same internal package part of this simple shape, whether or not the leads protruding to the outside are the same,
Say “internally identical”.

As used herein, “internally couplable” refers to conductors and conductive contacts that are configured to be easily connectable to provide internal electrical coupling. As used herein, "disconnected" is constructed (or was) capable of being internally coupled to a target conductor (ie, of an IC die and / or package), but from this target by a dielectric. Refers to separate members. "Disconnected" is another term known in the art to describe some branch conductors and their contacts. Except for the above text, "conductor" as used elsewhere in this specification means a continuous conductor.

As used herein, a “chip” refers to a package that includes at least one die and has external contacts electrically coupled to at least some electrically functional contacts of the at least one die.

As used herein, the term “footprint” refers to a two-dimensional plan view, layout, or projected area of a device on a given plane, such as the mounting layout of a chip.

As used herein, “similar” dies are identically manufactured dies, and substantially all of the common electrically functional contacts are in exactly the same order for each internal circuit device. The die at the same nominal position. As used herein, "substantially all" means at least about 90%. Thus, a package that can accommodate a composite die can in fact accommodate a "similar" but simpler die. "Dissimilarity" used here is
A chip that contains dies that do not meet this definition, or dissimilar dies.

As used herein, “substantially identical” refers to a die in which all electrically functional contacts of one die are in the same nominal position with respect to their internal circuitry as the other die. Dies made with a mask made from the same data file, or all having the same structure with the same nominal placement, are "substantially identical." Even dies with one or two contacts that are different are still "substantially identical" if one serves another intended application and the difference does not require the vendor to change the product number. Multiple revision numbers for a single product are not uncommon in the IC industry.

As used herein, “identical” refers to a die in which all electrically functional contacts are configured identically. Manufacturing differences, such as those resulting from process variations or differences between identically manufactured masks, do not preclude two dies from being identical, provided that one can serve the other intended purpose. As used herein, "different" refers to dies that do not meet the definition of "identical" (such as still "substantially identical" but with modified electrical properties).

Two packages, if one can serve the other intended purpose,
Here, they are regarded as “identical”. Two packages are "internally" identical if they are identical except for the shape of the leads protruding from the package body. The packages can be internally identical, even though the contents of the cavities are different from each other. Two packages may be "substantially" identical if their contacts differ by one or two, and they are said to be such that if substantially all of their electrically functional contacts are of their intent. "Similar" if they have the same general arrangement in the intended application.

As used herein, the “inside” of a package refers to the contents of the package body and package cavity. These contents typically have internal contacts coupled to the die contacts by a "conduit arrangement." As used herein, "conduit configuration" refers to the number of conduits placed in the package and their approximate location with respect to the die or package interior, and the selection of die and package internal contacts is determined electrically by these conduits. Should be combined. So a "bond map" containing die and package specific information that the wirebonder needs
Is an example of a sufficiently complete "conduit construction" even though it lacks specific information about loop height.

As used herein, an “interface” is a set of contacts provided on each of two entities, together with the conductors coupled to those contacts and the structural member containing those conductors outside the two entities. Point to. Therefore, the die interfaces discussed herein each include at least two IC packages. The chip interface discussed here may only contain a pattern of solder bonds.

FIG. 1 illustrates a packaged memory chip 616 and a prior art routing layer 606.
Indicates. The packaged chip 616 has 18 gull wing leads 699, each having a bottom contact 691 located toward a corresponding inner contact 696 on the routing layer 606. The routing layer 606 insulates the inner contacts 696 from each other and provides an internal conductive path to some of the outer contacts 697. Each outer contact 6
97 is also electrically coupled to the bottommost contact 698 below this routing layer 606. Most outer contacts 697 couple via "normal" vertical conductors 693, while some outer contacts 697 couple via "offset" vertical conductors 694.

FIG. 2 shows a known laminating apparatus 600 mounted on a substrate 605, as taught in US Pat. No. 5,612,570. The device 600 includes several identical routing layers 606, each holding a corresponding packaged chip 616, 617, 618.
, 607, 608. Each outer contact 697 of the bottom path setting layer 606 is
Directly coupled to the corresponding bottom contact 698 on the underside of the second routing layer 607. Similarly, the bottom bottom contact 698 below the bottom routing layer 606 directly couples to a contact (not shown) on the substrate 605.

Depending on the known surface mount stacking interface scheme in which vertical conductors 693 are coupled with offset conductors 694, each packaged chip 616, 671, 618 is an “individual signal coupling”, ie another package of this stacking device 600. It has at least one signal path electrically isolated from the mold tip. This allows each packaged chip 606, 607, 608 to be uniquely specified even if the same packaged chip is used.

FIG. 3 shows an exploded view of the Seagate Cheetah 18LP disk drive sold prior to writing this. As will be described below, this electromechanical system requires a stacked IC device to meet its shape factor specifications. Briefly, the disc drive 10 includes a housing base 42 and a top cover 490,
They engage the gasket 495 to form a hermetic housing that maintains the interior of the disk drive 10 in a clean environment. A plurality of disks 46 are mounted for rotation on the spindle motor hub 44. A plurality of transducer heads 60 are mounted on the actuator body 56. The actuator body 56 is a head 60
Is pivotally controlled under the control of a voice coil motor (VCM) that includes a voice coil 54 and a magnet 50 to controllably move along the arcuate path 62 to the desired track 48. The signals used to control this VCM and head 60 enter and exit electronic circuitry on controller board 500 via flexible circuit 64 and connector 68. As shown, the controller board 500 includes a fiber channel interface 550, a serial port connector 560, and a spindle connector 570. In fact, this substrate 500 is very crowded.

FIG. 4 shows a controller board 501 modified from the board 500 of FIG. 3 by replacing the laminating apparatus 580, 581 of the present invention. The upper outer contacts of one lamination device 580 are all exposed to air, thus exposing the outer leads and spacing layer portions 584 under these leads. The top external contacts of the other stacking device 581 are all completely covered with a protective (solid) dielectric 585, such as a deposited epoxy. The chips shown are preferably all bonded to the substrate 501 by a single reflow operation.

FIG. 5 shows cross-sectional views of the laminating apparatus of the present invention at various stages of manufacture. A spacer layer 880, such as a printed circuit board, comprises solder paste on the contacts 891, 892 on its opposite surface. After preparing this layer, at least one tip 270 is placed on the work surface 83. An assembly component including a spacer layer 880 is placed in contact with the leads of each chip 270. At least one or more layers of chip 170 include solder 87 so that some of its contacts are directly bonded to contacts 892 on spacer layer 880. The electrical probe 86 is used to test which laminating device 580, 581 works. Clamping surface 88 is used to secure these devices, while a cutting device 79 such as a router separates them (single unit). These separate devices are taken out from the assembly equipment 83, 88. They can then be bonded to the substrate 503 having inner conductors 568, for example by soldering to contacts 592. In one embodiment, at least one bottom contact of the stack is coupled only to the dielectric area of the substrate, and all top contacts of the top chip 270 of the stack are dielectric 5.
It is covered with 85. Instead, at least one substrate contact 592 coupled to the stacker 580 is electrically isolated from any of the substrate's internal conductors 568.

FIG. 6 shows further details of the method of the invention consistent with FIG. The printed circuit board is inspected 1220 as is known in the art, then pretreated 1225 and screen printed 1240 with solder paste. Chips are picked and placed 1240 on the reflow pallet first, then additional substrates and chips are placed on the reflow pallet 1245, 1250. Place the top cover of this reflow pallet 1255,
Reflow 1265 as is known in the art. These devices undergo an electrical test 1270. In a preferred embodiment, step 1270 more specifically includes modifying all electrical properties of each, or at least one of, the vertically aligned chips of this stack. These steps are then singulated 1280 and inspected 1285, with any necessary rework prior to mounting on the substrate.

FIG. 7 shows a stacking device 582 of the present invention, which is used for stacking leaded chips 180, 280.
Shown in exploded view with the lower side 171, 271 tilted upward to show. Bottom chip 1
80 is a packaged device having 18 conductors 101-118 with gull wing leads projecting outwardly downward. As shown, each of the conductors 101 to 118 has an upper contact 192 and a primary P that are configured to be in direct contact with the two-membered spacing layer 880.
It has a bottom contact 191 which may be configured to be in direct contact with a CB (not shown).

A heat sink 780 shaped like an uppercase “I” with two narrow portions joined by a vertical portion is provided. Optionally, it makes direct contact with the bottom tip 180,
It is fixed there with a high temperature silicone adhesive. Although heatsinks are normally only used for large chips, heatsinks 780 are used for unusually small chips 18 for purposes of illustration.
0, 280, and the spacing layer 8 shown as interface 199.
80 and an offset conductor routing layer 980. In accordance with the preferred embodiment of the present invention, a stack having L chip layers requires only (L-1) such interfaces for proper routing. Interval holding layer 880 and routing layer 98
The zeros are preferably attached to each other prior to assembly with the chips 180, 280. Most of the conductors 801-818, 901-918 of these layers 880, 980 have contacts configured to mate directly with the contacts of the other layers, so that it is convenient to carry out this attachment with solder paste.

As shown, the line 168 on the bottom surface 971 of the routing layer 980 couples the conductor 901 to the conductor 913 so that the four package conductors 101, 113, 201, 2
Combine 13 If the chips 180, 280 of this stack are identical, this line does not allow individual signal coupling to these package conductors 101, 113, 201, 213. The lines on the routing layer that have conductors adapted to couple to conductors on more than one side of the stacked IC package 180 are nevertheless only the two-piece spacing layer 880 or the frame 606 of FIG. Give a new tolerance to.
That is, as shown in the drawing, the route setting layer 980 does not add to the area occupied by the laminating apparatus 582 even if the provisional heat sink 780 is omitted.

As shown, the routing board 980 has the additional feature of providing individual signal coupling. Other conductors 901-911 including contacts of the routing layer 980,
Unlike 913-918, the conductor 912 has its surfaces 971, 972 as shown.
Only one of them includes contacts 991 and 992. The preferred embodiment of the present invention features a routing layer with at least one offset conductor 169 made by methods known to those skilled in the art. In the preferred embodiment of the invention, conductors 114 and 214 are unconnected (
That is, a package conductor including a contact which is not internally connected to the internal circuit of this chip), and the chips 180 and 280 are the same. So, as shown, conductor 1
12 is electrically coupled to exactly one chip 180, and conductor 114 is electrically coupled to exactly one chip 280, which is a convenient implementation of individual signal coupling.

Still referring to FIG. 7, the top surface of the heat sink 780 is preferably coated with a dielectric coating to avoid electrical coupling with the conductor 168 on the routing layer 980 between the chips 160, 260. The materials that can be used for the heat sink 780 are known in the art, but are often electrically conductive. Instead, a spacing layer 880 (as shown) of sufficient thickness to provide a clearance underneath this routing layer 980.
Can be used with a heat sink 780 secured away from this routing layer 980.

FIG. 8 shows a cross-sectional view of the laminating apparatus 582 of FIG. The lower conductor 168 of the routing substrate 980 is electrically isolated from the heat sink 780 by a dielectric 195 between the substrate 980 and the heat sink. If the heat sink is fixed to the bottom chip 180, the dielectric 195 may be a void. Otherwise, the dielectric 195 can include a coating on the surface of the heat sink or substrate 980. As shown, in a flat configuration with an externally identical package, the spacing portion 584 preferably has a thickness 881 that is greater than the thickness of one chip 180 plus the thickness of one heat sink 780. As shown in FIGS. 7 and 8,
Each spacing portion 584 lacks horizon routing and is at least approximately its width 882.
It has a thickness of 881.

In another embodiment as shown in FIG. 8, the main body of the lower chip 180 is the lead 17
9 extends lower than the bottom surface. The primary substrate can accommodate such chips by providing an indentation large enough to accommodate the body of the lower chip, which is advantageous for accommodating, for example, flat package leads (see FIG. 11).

FIG. 9 shows a cross-sectional view of a stacking device 583 including an upper chip 280 having a package lead 279 that is longer than the leads 179 of the lower chip 180. Upper package 280
Of conductors include leads 279 each having an upper side 268 and a lower side 267. As shown, the lower portion of each lead is the lower external contact 191, 291. Variations on the outer lead configuration are well known in the art. Instead of the routing or spacing layer of the arrangement of FIG. 9, the lower external contact 291 of the long lead 279 is directly coupled to the upper external contact 192 of the conductor of the lower package 180. A large heat sink 780 is shown to accommodate large chips with high current (and / or leads on all sides).
Different lead configurations for internally identical packages are shown in Figures 5-8 and 12-
It is optionally used for certain advantages associated with the embodiment shown in FIG.

FIG. 10 illustrates a stacked configuration different from that shown in FIG. 7 with three important features.
First, interface 199 includes a single piece routing layer 980 that also provides spacing between each lower conductor 101-118 and respective upper conductor 201-218. The routing layer includes at least one recess 994 in which at least one chip 180 projects. The recess 994 may be a bathtub type for the chip 180 having terminals on four sides. Second, each layer of chips 180, 280 includes multiple chips. This is a valuable space saving feature that is not compatible with certain chip stacking systems. Thirdly, the routing layer 980 shown in the figure is used for the laminated chip 18
Includes a widened portion 996 that is wide enough to allow an outlying line 968 of any of the 0, 280 footprints with at most a slight increase in the footprint size of the laminator (ie, less than about 5%). . As shown, this flared portion 996 allows the at least one line 969 to be relocated to the outer portion of this layer 980 (ie, outside the footprint of the most recent chip). Next, this is done by replacing the top line 968 with each bottom line 1 of FIG.
Instead of 68, it eliminates the need for an insulator between routing layer 980 and heat sink 780. With at most minor modification, one of ordinary skill in the art will be able to utilize any of these three features in the embodiments shown in either Figures 5-7 or Figures 10-13 as described herein.

FIG. 11 shows a portion of a stacking device that includes three chips 180, 280, 380 and two interfaces 199, 299 each including a frame-type spacing layer 880 that is fully populated with vertical conductors (not shown). An exploded view is shown. The upper interface spacing layer 880 includes an assembly tab 888 having a tapered end 889.
The spacing layer is preferably made of a sheet containing a number of individual layers 880 joined together with tapered ends, and each contact is screen printed with reflow paste prior to lamination assembly. A number of bottom chips 180 can each be placed in a grid by a robotic assembly machine, such as that as a reflow pallet 81, in depressions 82 on the work surface. During reflow, the stack preferably sticks and is compressed by the downward force applied by the flanged plunger 85 or the like. After reflow, the laminator can be singularized by breaking the spacing layers at their tapered ends.

FIG. 12 shows a detailed example of the stacking device mounted on the primary substrate 502 according to the present invention. In this example, an IC die is incorporated into a "leadless" chip carrier (LCC) package 160, 260, and their conductors 101-158, 182, 1,
91,192 has this name because it does not project too much outside the basic shape of the body of this package. In FIG. 12, the bottom LCC package 160 is tilted downward so that its upper surface 172 is visible. The integrated LCC package 1160 above is 58
, As well as half of the outer line 198 (the line "outside" of this package, half of which is shown schematically), is tilted upward so that its bottom side 1171 is visible.

In FIG. 12, the interface 199 may simply include solder between the conductor 101 and the conductor 1101 and each of the other 57 mating conductors of the two lower packages. Optionally, it may include a spacing layer and / or heat sink, such as that shown in FIG. Optionally, the present invention provides a lower package 160,
Second integrated LC identical to 160 with 58 58 open contacts on top 2172
Includes C package 2160. This bottom LCC package 160 has internal circuit devices 100 coupled by a number of internal lines 197 to respective upper contacts 192 on the upper surface 172 of the package and to respective lower contacts 191 on the lower surface 171 of the package. Including die. Each of these internal lines 197 includes the external contacts 181 of the first die and the internal contacts 182 of the package, as well as the two external contacts 191, 192 of the package. At least half of these lower external contacts 191 each directly mate with a corresponding contact 592 on the primary substrate 502. However, as will be explained below, this fractional lower outer contact 191 of the bottom LCC is optionally uncoupled, for example by physically coupling to the dielectric 590 on the primary substrate 502. Examples are shown below conductors 130, 146 and 150. As shown by the conductors 146 and 1146 of the present invention, the laminated structure of the present invention is a chip having a very low capacitive load because it is electrically insulated from the inside of the substrate 502 on which this laminating apparatus is mounted. Optionally, one or more couplings between the conductors.

Each package 160, 1160 preferably includes at least one unbonded contact 189, 1189 outside the internal circuit arrangement 100, 1100 of the die inside this package. In the typical case, package conductor 1134 or internal circuit wire 1186 would be electrically coupled to one side of each uncoupled contact 1189, as is clearly shown for package 1160. The unbonded contacts 189, 1189 may be part of the die (such as bond pads with no bond lines attached) or part of the package (such as bond fingers with no bond lines attached). As will be explained below, the proper use of non-bonded contacts allows for improved performance and ease of manufacture not previously available.

Many contacts 181, 182, 189 inside package 160 are not shown in FIG. 12, and conductors that may electrically couple uncoupled contacts 189 to external contacts 191, 192 or internal circuit device 100 are also shown. It should be understood that it does not. Uncoupled contact 189,
1189 and the conductors to which they are attached are commonly referred to in the art as "disconnected."

Although most of the die contacts 181 may be uncoupled contacts 189, 289, most of the external die contacts 181 of each package 160 (ie, available external to the die) generally have corresponding internal circuitry. Electrically coupled to both device 100 and corresponding package contact 182. In some situations, more than one package contact 1116, 1
It is advantageous to have one or more internal lines 1185 each electrically coupled to 117.

FIG. 13 shows a Venn diagram for identifying suitable package sizes for a given set of chips to be stacked, particularly useful for dissimilar chips. Yen 1
Reference numerals 60 and 1160 each represent a package, and each “x” in the circle represents a conductor extending in the corresponding package. Therefore, the area 21 includes both packages 160 and 116.
Represents a conductor extending into zero. Recalling the package connected inside that 14, the conductors 101, 108, 111, 114, 117, 118, 119, 125, 1
Reference numerals 30, 133, 138, 146, 150, and 152 are respectively coupled to the corresponding internally connected package conductors in FIG. 12, and these 14 couplings are shown in the common region 21 by "x". Similarly, although coupled to chip 160, chip 1160
Thirteen other connectors, which are not coupled to each other, are indicated by "x" in each area 11. Therefore, a careful inspection of FIG. 12 or FIG. 13 reveals that a total of 27 package conductors in the chip 160 are interconnected (to the internal circuit arrangement 100 in the chip 160). As explained above, one aspect of the present invention is directed to individual signal coupling--changing the connectivity of chips 160, 1160, which first empties the "exclusive" regions 11 and 22.

FIG. 14 shows a Venn diagram similar to that of FIG. 13, adapted for bonding three or more layers. As shown, FIG. 14 illustrates how a stack of three dissimilar chips 160, 1160, 2160 can be formed in a substantially non-parallel configuration consistent with FIG. As shown, the third circle 2000 represents the top chip 2160. The ten conductors in region 44 are shared by all three chips, and region 21, which is shared only by lower chips 160, 1160 (excluding third chip 2160), has only four "composite" conductors. In general, each circle 160, 1160, 2000 represents a die or another layer having selectively provided coplanar contacts, such as substrate 502.

FIG. 15 illustrates a lamination device of the present invention, somewhat similar to FIG. 12, and teaches a chip specialization approach. Techniques for detecting any post-assembly induced chip differences taught herein are known. Using these teachings, it is simply a matter of design choice for one of ordinary skill in the art to provide suitable internal circuitry to respond to any of these differences. IC die 100 includes a storage cell 190, which may be any of the non-volatile storage devices known in the art, such as a laser modifying element. Cell 190 is E
It is further preferred to include an EPROM or other read only memory or fusible link, which may be one or more photosensitive components on the IC for use with a transparent IC package cover.

As shown, die 1100 and package 1160 are respectively
Substantially the same as 00 and 160. In one embodiment, the illustrated stacking device can function because the storage cells 190, 1190 are configured differently.
On the other hand, the unconnected contacts 189, 1189 present on one chip are not present on each other chip of this stack.

FIG. 16 shows an inventive arrangement of unconnected contacts 189, 289 for individual signal coupling to each chip of a two-layer stacker (ie one having two layers of chips). It is substantially consistent with FIG. 15 as described above, but the package 160
The external contacts 191 and 192 retracted from the side surface 163 of 260 are drawn. An integrated circuit die 170 having the internal circuit device 100 is mounted inside the bottom IC package 160. Inside this bottom IC package 160, internal lines 197 are connected to the external contacts 1 respectively.
91, 192 and the bond between the internal contact 182 of the package 160, bond wire 183.
, A contact 181 on the die 170, and a part of a signal line communicating with the internal circuit device 100. In FIG. 16, the unconnected contact 189 in the bottom package 160 is electrically coupled to the internal circuit device 100, but otherwise separated from the external contacts 191, 192 by a large dielectric gap. I know that

Substantially the same integrated circuit die 270 has substantially the same stacked IC package 26.
It is mounted inside 0, but connected with different bond wire configurations. In particular, the unconnected contacts 289 on the upper die 270 are not directly above the unconnected contacts 189 on the same lower die. The two dies 170 and 270 are the same and assembled in the same stacked package 160 and 260, and one die has first and second continuous contacts 181 corresponding to the same continuous contacts 281 of the other die. Package 160 has internal contacts of conductor 142 coupled to the first contact of this first die and another package 260 has internal contacts of corresponding conductor 242 coupled to the second contact of this second die. preferable.
In other words, each of the same die 170, 270 has a non-connecting contact 289 of another chip.
, 189, offset (ie, non-corresponding) unconnected contacts 189, 289 are desirable. In a more preferred embodiment, the continuous contacts 181, 281 of two identical dies 170, 270 have inverters 541, 54 in the internal circuit arrangement of each die.
Are connected to each other via 2.

FIG. 17 shows another inventive arrangement of non-contacting contacts 189, 289 for chip specialization in a stacking device, substantially consistent with FIG. 15 described above.
In FIG. 17, the chip interface 199 includes a spacing layer 880, which allows airflow and / or heat sink structures between the packages 160, 260. The illustrated spacing layer 880 includes vertical conductors 893 that couple the top contacts 892 to the bottom contacts 891, respectively. At least some lower contacts 2 of the upper package 260
91 is directly coupled to the upper contact 892 of the spacing layer 880. At least one
Not connected, but directly bonded only to the dielectric region 890 of the spacer 880. As shown, the lower outer contacts 19 of at least some of the package conductors 110, 112.
1 is similarly configured for direct coupling to the primary substrate 502.

FIG. 17 also shows fusible links 186, 187, 286, 287 which have been blown such that each die 170, 270 has a different configuration of fused links. In the preferred method of the present invention, all similarly fabricated IC dies are similarly packaged and electrically coupled prior to the link being blown. This facilitates production by reducing the types of parts that must be kept in inventory and delaying the time between making the difference between the upper and lower package devices. If you use all or nothing links, you can skip the two illustrated links into any of the four configurations. Each die has at least one configuration of conductors, such as fusible links 186, 286 in FIG. At least a log ₂ L configuration of conductors is used, where L is the number of layers in this stack. In FIG. 17, some of the package terminals 112, 212 have extra links 187, 287 coupled to them, for a two-layer stack, individual signal couplings log ₂ 2 = 1 on each die. The fusible links 186, 286 of FIG. Thus, one embodiment of the present invention uses extra links 18 on each die.
7, 287 are omitted. However, having such an extra link would not be possible until the same die 170, 270 were packaged and this stacker was about to be assembled.
Advantageously, they can be kept in inventory without deciding whether to use them for a 2, 3 or 4 layer stack.

FIG. 18 is a flow chart of the method of the present invention, consistent with FIG. The chip to be stacked is made at 1820 with elements in non-volatile configuration. This may be a cell 190 as described above with reference to FIG. 15, a fusible link 186 as described above with reference to FIG. 17, or similar items known in the art. The selected element is preferably of a type that can be easily modified without mechanical work such as bending, soldering, or cutting. As discussed above, many non-volatile devices that respond to solid state programming methods are available.

The internal chip characteristics were modified at 1830 and the stacked device was processed as described above.
Assemble with 00. In one embodiment, the package conductors have side contacts (such as those shown in FIGS. 7-12) in a stack of four or more layers of substantially the same chip.

Referring back to FIG. 17, programming conductors 111, 211 for each of the packages 160, 260 are shown. The preferred embodiment of the present invention provides a side contact for programming conductors (configurations of such side contacts are known in the art). Side contacts are used instead of the top or bottom contacts to provide access to programming lines for only one package at a time, or with a spacing layer having a dielectric region 890 such as that of FIG. be able to. For stacking several layers of substantially identical chips, the modification step 1830 of FIG. 18 includes the step of specializing each vertically aligned set of chips with such programming conductors. Is preferred.

In another embodiment, three identical chips are stacked with the spacing layer exactly as consistent with FIG. 17 (second spacing layer and third stacked chip not shown). The laminating apparatus of this embodiment is preferably laminated (assembled) before modifying the internal chip characteristics at 1830. Advantageously, this eliminates the need to keep track of which chip is which until these stacks are assembled. The bottom die 170 includes conductors 110 and 11
Specialize from the others 270, 370 by applying a large current during one, thereby blowing the link 186. The top die 370 is the package conductor 312.
Specialize from the other 170, 270 by skipping the link bound to. After at least a portion of this chip specialization 1830 and assembly 1840, the laminating apparatus is ready 1850 for installation on a substrate.

FIG. 19 illustrates another flow chart of the present invention, consistent with FIGS. 15, 16 and 20. The die are packaged 1920 in a package without specialization, thereby exploiting some of the commonality principles. The first conduit configuration is used to install the conduit in the first package at 1930 to couple the required contacts of the first die.
A second conduit configuration different from the first is used to place the conduit at 1940 in the second package, thereby specializing the chip. After these are installed, IC chips are stacked at 1950.

FIG. 20 shows some unconnected contacts 189, 289, 389 of a configuration of the present invention, as described above, in a three layer stack, consistent with FIG. Integrated circuit die 170
, 270, 370 are packaged within respective integrated circuit packages 160, 260, 360. The top external contacts 392 of the top chip 380 are all physically separated from each other by a dielectric gap 396 and a full dielectric cover 395, such as air or deposited coating 585 similar to those shown in FIGS. 4 and 5. There is. Upper external contacts 192, 292 of lower chips 180, 280 are similarly separated by dielectric gaps 196, 296, but external lines 198, 298 are offset from at least a portion of any corresponding dielectric cover. .

All of the steps and structures described above will be understood by those of ordinary skill in the art and will enable practice of the present invention without undue experimentation. While numerous features and advantages of various embodiments of the invention have been set forth in the foregoing description along with details of the structure and function of the various embodiments of the invention, it should be understood that this disclosure is merely exemplary. is there. Changes may be made in these details, particularly with respect to structure and arrangement of parts, within the principles of the invention, to the full extent shown by the broad, general meaning of the terms expressing the claims. For example, a particular element may vary depending on the particular application of the system, while maintaining substantially the same functionality without departing from the scope and spirit of the invention. Moreover, while the preferred embodiments described herein are directed, in large part, to increasing areal density of PCBs and simplifying the manufacture of components for laminator equipment, those of ordinary skill in the art will appreciate that the teachings of the present invention cover the scope and scope of the present invention. It will be appreciated that it can be applied to improve other performance aspects without departing from the spirit.

In summary of the method of the present invention, the layers of chips 280, 380 are assembled into a floor 81 of an assembly facility,
Place directly on 82, 83. Spacing and / or routing layers 584, 880 are placed directly on the contacts 291, 292 of the chip and additional layers of chips 180, 280 are placed directly on this layer 584, 880. These layers, for example, solder reflow 1
After bonding by 265, the laminator 580 made by this method is optionally tested at 1270 prior to removal from the facility.

Another method is the die 170, 270 (they may be similar or identical).
In a package 160, 260 (which may also be similar or identical). Chips 180 and 280 made by this method are used to connect conduits (
For example, by placing a bond wire 183 and a connection 189) on each, 1940, or otherwise modifying their electrical properties at 1830 (eg, by skipping link 186 or programming cell 190). (By minging)). The installation steps 1930, 1940 may be different by simply horizontally offsetting one connection 189 from another 289.

In another method, substrate 503 is constructed with many conductive contacts 592 and many internal lines 568. The laminating apparatus 580, 582 is assembled with several substantially coplanar conductive contacts 191. Although some of the device contacts 191 are physically coupled to contacts 592 on the substrate, at least one of the device contacts 191 is, for example, coplanar with the substrate contact 592 and aligned with the at least one device contact 191. By providing a dielectric region 590, it is electrically isolated from all internal lines 568.

Devices made by each of these methods, or having the structures described, are also embodiments of the invention. One such device is the top and bottom package 16
0, 260, each of which has a winged winged lead that projects outwardly and downwardly from at least opposite sides. Means for physically coupling these leads are provided as taught above and optionally include two elongated printed circuit board (PCB) portions 584 between the leads of the top and bottom packages. Means for electrically coupling these leads are also taught, optionally on this PCB portion 58.
4 includes one or more horizontal circuit lines.

[Brief description of drawings]

[Figure 1]   1 illustrates a prior art implemented memory chip and routing layer.

[Fig. 2]   2 shows a known stacking device including the chip of FIG.

FIG. 3 illustrates a prior art electromechanical system having a congested controller board of the general type that can benefit from the present invention.

FIG. 4 illustrates a crowded controller board of the present invention modified from the controller board of FIG. 3 by replacing the laminating apparatus of the present invention.

[Figure 5]   FIG. 4 shows a cross-sectional view of the laminating apparatus of the present invention in a series of manufacturing steps.

[Figure 6]   6 illustrates further details of one method of the present invention consistent with FIG.

FIG. 7 illustrates the stacking device of the present invention in an exploded view, tilted upward to reveal the underside of the chip, which features the package with seagull wing leads and heat sinks.

[Figure 8]   FIG. 8 shows a sectional view of the laminating apparatus of FIG.

[Figure 9]   FIG. 3 shows a cross-sectional view of a lamination device of the present invention in which leads are stacked on the leads of the present invention.

FIG. 10 shows a stacked configuration where two or more chips are shown per layer and a single item routing layer also has features that have flared portions for routing outside the area occupied by the chips.

FIG. 11 shows a partial exploded view of an inventive stacking device including three chips and two interfaces.

FIG. 12 shows a detailed example of a stacked LCC tilted apart to show the interface between the interior (showing the original features) and the chip (generally shown).

FIG. 13 shows a Venn diagram for identifying suitable package sizes for a given set of chips to be stacked, particularly useful for less similar chips.

FIG. 14   FIG. 14 shows a Venn diagram similar to FIG. 13, adapted for joining two or more layers.

FIG. 15 illustrates a stacking device of the present invention, somewhat similar to FIG. 12, showing other features for specializing substantially identical chips.

FIG. 16 illustrates an inventive configuration of in-package conduits and unconnected contacts for individual signal coupling to each chip of a two-layer stacker.

FIG. 17 shows another inventive configuration of non-contacting contacts for chip stack specialization, which is substantially consistent with FIG.

FIG. 18   18 shows a flowchart of the method of the present invention, consistent with FIG.

FIG. 19 shows another flowchart of the present invention, consistent with FIGS. 15, 16 and 20.

FIG. 20 shows some non-contacting contacts of the inventive construction in a three-layer stack, consistent with FIG.

─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Fabry, Michael, Earl             Apple, United States Minnesota             Ary, Forest Rain 14054 (72) Inventor Junge, Terry, A.             United States California, Scot             Ts Valley, Zinfandel Sir             Curu 162 (72) Inventor Tian, Fee, Inn             Singapore, Singapore, number               04-54, Serangoon Central             Live, block 255 (72) Inventor Tune, Anne, Au             Singapore, Singapore, number               03-217, Yishun Avenue             11, block 350 rays (72) Inventor Olson, Jonathan, Yi             Minneapolis, Minnesota, United States             Su, Apartment 2, Pen Aveni             South South 5034 F term (reference) 5E336 AA04 AA11 AA13 AA16 CC55                       DD21 DD26 DD37 GG09 GG14                       GG30

Claims (10)

[Claims] 1. A method of stacking chips by placing at least two chip layers, each layer comprising at least one chip, in an assembly facility including a floor, comprising: (a) directing the first chip layer directly Positioning on the floor; (b) positioning a first spacer layer on the first chip layer; (c) positioning at least one additional chip layer on the spacer layer; (d) these Laminating the layers together; and (e) removing the joined layers from the assembly facility including at least one laminating apparatus. 2. A laminating device made by the method of claim 1. 3. A method for stacking similar, packaged first and second dies, comprising: (a) mounting at least one said first die within a first package; (b) several Placing an electrical conduit in the first package in a first conduit construction; (c) attaching at least one second die to a second package; (d) some electrical conduits in the second package. Installing in a second conduit structure different from the first structure so that the mounting step (c) is completed before the installation step (d) is completed; and (e) the A method of stacking first and second dies comprising electrically coupling one package to the second package to form a stacking device. 4. The method of claim 3, wherein only one said first die is laminated with only one said second die, and said first and second dies are substantially Each die having an internal circuit device and a set of nominal contact positions for the circuit device, the first set of nominal positions including a second set of nominal positions, and each package having an interior. Where each interior and each die includes several contacts; each conduit is a bond line connecting one of the die contacts to one of the internal contacts;
) And (d) each include coupling each of several bond lines directly to one of the die contacts and to one of the internal contacts; installation step (b) includes Resulting in electrical coupling, which forms the first conduit configuration, as well as installation step (d), which results in the second set of contacts being electrically coupled, which results in the second conduit configuration. Forming a first die and a second die. 5. A laminating device made by the method of claim 3. 6. A method of making a stacking device including at least a first integrated circuit (IC) die and a second IC die: (a) assembling a first IC chip having the first die in a first package; (B) A second IC chip having the second die is assembled in a second package, the second die being the same as the first die, and the second package being internally the same as the first package. (C) encapsulating the package; (d) modifying at least one electrical characteristic of the chip; and (e) stacking the first chip electrically coupled to the second chip. A method of making a laminated device including the steps of making the device. 7. The method of claim 6, wherein said modifying step (d) comprises the step of blowing at least one fusible link present on at least one of said dies. 8. A surface mount integrated circuit device for coupling to a substrate comprising: a top package and a bottom package, each lead including an IC die and having an external configuration including a number of protruding leads, each lead being A package having a top surface and a bottom surface, the surface of each lead of the top package being covered with an insulator, and the bottom surface of some of the bottom packages being configured to bond to the substrate; A circuit arrangement comprising a combination of interfaces for coupling the bottom surface of some leads of a package to the surface of some leads of the bottom package. 9. A stacking device for bonding to a substrate comprising: at least two integrated circuit (IC) chips including surface mount packages; and a stack for mechanically and electrically bonding the IC chips together. Laminating apparatus including means. 10. A disk drive including the electrical system of claim 9, wherein the stacking means is a set of solder contacts and at least one of the surface mount packages is a set of substantially coplanar packages. A substrate having contacts and further having contacts and a dielectric region, some of the package contacts coupled to some of the substrate contacts, at least one of the package contacts contacting the dielectric region Disk drive to do.