JP2003510750A5 - - Google Patents

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Publication number
JP2003510750A5
JP2003510750A5 JP2001527280A JP2001527280A JP2003510750A5 JP 2003510750 A5 JP2003510750 A5 JP 2003510750A5 JP 2001527280 A JP2001527280 A JP 2001527280A JP 2001527280 A JP2001527280 A JP 2001527280A JP 2003510750 A5 JP2003510750 A5 JP 2003510750A5
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JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2001527280A
Other versions
JP2003510750A (ja
Filing date
Publication date
Priority claimed from US09/407,775 external-priority patent/US6424480B1/en
Application filed filed Critical
Publication of JP2003510750A publication Critical patent/JP2003510750A/ja
Publication of JP2003510750A5 publication Critical patent/JP2003510750A5/ja
Withdrawn legal-status Critical Current

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JP2001527280A 1999-09-28 2000-09-21 プログラム可能な書き込み−読み取り移行ノイズ抑圧回路を有する読み取りチャネルを持つ磁気媒体記録装置 Withdrawn JP2003510750A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/407,775 US6424480B1 (en) 1999-09-28 1999-09-28 Magnetic medium storage apparatus with read channel having a programmable write-to-read suppression
US09/407,775 1999-09-28
PCT/EP2000/009224 WO2001024178A1 (en) 1999-09-28 2000-09-21 Magnetic medium recording apparatus with a read channel comprising a programmable write-to-read transition noise suppressing circuit

Publications (2)

Publication Number Publication Date
JP2003510750A JP2003510750A (ja) 2003-03-18
JP2003510750A5 true JP2003510750A5 (ja) 2007-11-15

Family

ID=23613476

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001527280A Withdrawn JP2003510750A (ja) 1999-09-28 2000-09-21 プログラム可能な書き込み−読み取り移行ノイズ抑圧回路を有する読み取りチャネルを持つ磁気媒体記録装置

Country Status (5)

Country Link
US (1) US6424480B1 (ja)
EP (1) EP1141955A1 (ja)
JP (1) JP2003510750A (ja)
KR (1) KR100810829B1 (ja)
WO (1) WO2001024178A1 (ja)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6518839B2 (en) * 2000-06-28 2003-02-11 Texas Instrumetns Incorporated Method and apparatus for effecting programmable gain amplification
US6621649B1 (en) * 2000-11-10 2003-09-16 Texas Instruments Incorporated Write-to-read switching improvement for differential preamplifier circuits in hard disk drive systems
US7292400B2 (en) * 2001-04-23 2007-11-06 Seagate Technology Llc Device for limiting current in a sensor
US6724556B2 (en) * 2001-06-29 2004-04-20 Texas Instruments Incorporated Single pole voltage bias loop for increased stability
US7106541B2 (en) 2001-09-14 2006-09-12 Convergent Systems Solutions, Llc Digital device configuration and method
US6973535B2 (en) * 2001-09-14 2005-12-06 Cornice, Inc. Digital device configuration and method
US6700427B1 (en) * 2002-08-28 2004-03-02 Adam J. Sherman Wideband DC-accurate series resistance compensator
US7480347B2 (en) * 2003-09-11 2009-01-20 Xilinx, Inc. Analog front-end having built-in equalization and applications thereof
WO2005039041A1 (en) * 2003-10-14 2005-04-28 Audioasics A/S Microphone preamplifier
US7391873B2 (en) * 2003-12-01 2008-06-24 Audioasics A/S Microphone with voltage pump
US7339760B2 (en) * 2004-01-30 2008-03-04 Agere Systems Inc. Integrated bias and offset recovery amplifier
US7697600B2 (en) * 2005-07-14 2010-04-13 Altera Corporation Programmable receiver equalization circuitry and methods
US7701654B2 (en) * 2005-09-23 2010-04-20 Agere Systems Inc. Apparatus and method for controlling common mode voltage of a disk drive write head
US7667914B2 (en) * 2006-04-17 2010-02-23 Hitachi Global Storage Technologies Netherlands B.V. Direct coupled wide-bandwidth front-end with smart bias control amplifier
JP2010108560A (ja) * 2008-10-31 2010-05-13 Toshiba Storage Device Corp 信号増幅装置、記憶装置
US9240199B2 (en) * 2014-03-12 2016-01-19 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for distortion characterization
US10715358B1 (en) * 2018-11-29 2020-07-14 Xilinx, Inc. Circuit for and method of receiving signals in an integrated circuit device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04328976A (ja) * 1991-04-27 1992-11-17 Rohm Co Ltd アクティブフィルタの特性切り換え回路
JP2625609B2 (ja) * 1991-07-10 1997-07-02 インターナショナル・ビジネス・マシーンズ・コーポレイション ディスク記憶装置
FR2694469B1 (fr) * 1992-07-31 1994-10-28 Sgs Thomson Microelectronics Dispositif de commutation écriture/lecture d'une tête de magnétoscope.
JP2933449B2 (ja) * 1992-09-22 1999-08-16 日本電気株式会社 自動利得制御回路及びこれを用いたデータ記憶装置
US5416646A (en) 1992-11-12 1995-05-16 Kabushiki Kaisha Toshiba Data recording and reproducing apparatus having read/write circuit with programmable parameter means
KR100309085B1 (ko) 1993-10-06 2001-12-17 요트.게.아. 롤페즈 기록매체상의트랙으로부터정보를판독하는장치
US6172548B1 (en) * 1994-12-30 2001-01-09 Stmicroelectronics, Inc. Input stage with reduced transient time for use in multiplexing transducers that require a switched DC bias
US5768320A (en) * 1995-09-05 1998-06-16 Analog Devices, Inc. Read system for implementing PR4 and higher order PRML signals
US5949820A (en) * 1996-08-01 1999-09-07 Nec Electronics Inc. Method for optimizing an equalization and receive filter
US6219194B1 (en) * 1999-04-09 2001-04-17 Guzik Technical Enterprises MR head read amplifier with improved write to read recovery time

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