JP2003505952A - Method of transmitting data in viewable part of video signal - Google Patents

Abstract

(57) Abstract: Data is encoded in a visible portion of a video signal (11) to be transmitted without deteriorating the display of a received video signal (21), and data in the received video signal is decoded. (11) method. Each data bit group (21) to be transmitted, called a data symbol, is associated with one of several longer predetermined chip sequences (23). Each chip sequence is divided into a plurality of chip lines (23), and each chip line, along with its inverse, is embedded in pairs for each line pair computed to detect the chip line they represent. , Each of several chip sequences is correlated with the detected chip line to derive a degree of correlation. The chip sequence having the largest correlation is selected as the chip sequence in which the data symbol has been transmitted.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD OF THE INVENTION

The present invention relates to data transmission on video signals, and more particularly to data transmission on the viewable portion of analog video signals.

[0002]

[Prior art]

In the past, attempts have been made to superimpose data on video signals. The most common method is to insert data during the vertical blanking period, such as the generation of a closed caption signal. Another approach is the visible portion of the video signal (visib).
The data is arranged in the "le portion". 1 of the latter method
One advantage is that it may be possible to detect data optically as well as electrically.

An example of an optical detection technique is described in the patent to Brownton et al., Patent No. 4,807,031.
No. The basic technique disclosed in this patent is to represent data by increasing or decreasing the brightness of a continuous horizontal line within a designated viewing area. The effect is imperceptible to the eye because the average brightness of two adjacent lines remains the same, but it is possible to detect the data by sensing the change in brightness increase or decrease by a suitable television receiver. it can. B
As described in the patent by Roughton et al., this technique is equivalent to superimposing a 7.867 kHz subcarrier frequency on the video signal, which can be detected by appropriate filtering. Broughton et al. Also teach how to determine in which field the data should be superimposed. For example, fields that are too white or too black are not suitable for inserting data.

[0004]

[Problems to be Solved by the Invention]

A general object of the invention is to insert data into the visible portion of the video signal by changing the brightness of oppositely paired lines, although much higher data rates are possible and conventional. Do this in a way that allows the data to be detected much more accurately than was possible in the art.

The term video signal as used herein is in analog form, directly digitized numerical representation, CCIR 601/656 standard based digital representation, RGB or YUV computer representation, or standard video direct digitization representation. To any representation of a standard NTSC, PAL, or SECAM signal commonly used for video transmission, including other digital representations that are simply numerically converted from (It is possible to determine how the signal was digitized and encoding and decoding from any digitized form is intended, unless that information is lost after digitization).

[0006]

[Means for Solving the Problems]

Data is transmitted in the form of data bit groups called symbols. Each symbol is associated with one of a predetermined number of longer "chip" sequences, called a PN sequence. The PN sequence transmitted for any symbol is divided into multiple chip lines. Each chip line, along with its inversion, is transmitted in pairs by embedding it in each line scan pair of the video signal. For example, each symbol representing 4 data bits is associated with one of a 16PN sequence of 80 chips each. Any such PN sequence to be superimposed on the video signal is divided into 4 lines of 20 chips each. Each chip line, in its normal form, is transmitted with an inversion, so that each of the eight lines of 20 chips is either added to or subtracted from each line scan of the video signal.

The received line scan pairs are computed and the 20 chips represented by these pairs are extracted. This is done by subtracting one line scan from the other to minimize the effects of the video and integrating the difference signal over the duration of each chip. Original P
Each chip in the N sequence is added to one line scan and subtracted from the other, so that when one line scan is subtracted from the other, not only is the effect of the video minimized, but the magnitude of the chip amplitude is increased. Is doubled. After all 80 chip pairs have been processed in this way and 80 "integral chip values" have been derived, the received code is correlated to each of the 16 possible best fit PN sequences. For the transmitted symbols, the PN sequence is considered to have the highest correlation with the received code.

Further objects, features, and advantages of the present invention will become more apparent in view of the following detailed description in conjunction with the drawings.

[0009]

DETAILED DESCRIPTION OF THE INVENTION

As used herein, a PN (pseudo-noise) code is a series of 1s and 0s with a 50% probability of 1 or 0, and the value of any bit is independent of the value of the preceding bit. Pseudo noise generators, many known in the art, provide a sequence similar to the front / back sequence generated by flipping a coin, but it is optional to simply start the generator in the same state. You can repeat the pattern. As used herein, a PN sequence is a specific series of 1s and 0s from all possible PN codes.

The communication method of the present invention is to generate a “chip” for each 0 or 1 in the PN sequence. A chip is simply a DC level that is added to or subtracted from the video signal, the duration of which corresponds to a 1 or 0 in the PN sequence. A tip is defined as the period between possible transition points.

FIG. 1 shows a 16-chip PN sequence representing a 4-bit symbol to be encoded. It is not advisable to directly code the data bits into the video signal by simply generating four chips and their inversions. It is very difficult to decode the input video signal and extract the chip value without error. Error-free decoding is generally not possible, even with the addition of standard error correction codes to bit groups. For this reason, statistical methods are used. 4 bits of information for 4 chips (
Instead of sending in the form of 8 chips (with inverted), more chips are sent. Different 16-chip PN sequences are associated with each 4-bit symbol. In the television receiver, the received PN code is
Compared to the 16PN sequence associated with the 16 symbols, the one of the 16PN sequences that has the highest correlation with the detected code is considered to represent the transmitted sequence, from which the original 4-bit symbol Can be determined.

FIG. 1 shows a method of representing a 4-bit symbol 0101 by a chip in a video signal. There is a 16-chip PN sequence uniquely associated with this 4-bit symbol. The 16-chip sequence is divided into 4 subgroups. Each subgroup is transmitted twice in two paired lines (although the line and subgroups need not be contiguous), the second line being the reverse of the first. Therefore, for a particular PN sequence, the first four chips shown in FIG.
It is 1. Line 1 of the video used to encode the PN sequence consists of these 4
Represents a chip, where a 1 is represented by adding a small positive voltage to the video signal and a 0 is represented by adding a small negative voltage to the video signal. (Fig. 1
Throughout, for clarity, the video signal is shown at a constant gray level, or constant amplitude). The second line is an inversion of the first line, where a chip with a value of 1 will add a small negative voltage to the video signal, and a chip with a value of 0 will add a small positive voltage to the video signal. Will be done. The next four chips in the PN sequence under consideration, 0100, are similarly represented on lines 3 and 4. Therefore, 8 lines are required to represent 16 chips, and 8 lines are associated with 4 bit symbols (the final information to be transmitted).

Throughout this description, it is assumed that each of the 4-bit symbols is associated with one of 16 unique 16-chip PN sequences. In actual practice, 20 chips per line is preferred. Therefore, an 80 chip PN sequence is used, with 8 lines being 80 chips and its inversion, representing 4 bits. This brings much better accuracy to the detection. For simplicity only,
The example of 4 chips per line is used throughout this description. The principles of the present invention are easily extended to symbols that represent PN sequences of any length and any number of data bits.

The use of a large number, especially as many as 20 chips, of the preferred embodiment of the invention per line results in a signal spectrum that is spread over a wide frequency range. The result is a form of spread spectrum communication. This communication technology was originally invented for military use. The idea is to spread the transmitted signal spectrum over a wide frequency range such that there is only a small amount of signal energy in any narrow range. This allows the signal to be hidden from the scanner looking for a narrow frequency range and also provides adequate protection of the signal from signal frequency jammers. Because the energy at any one frequency is low, the visibility of the data signal is low when the data signal and video are displayed together on a TV monitor, which is why this technique is advantageous for use in the present invention.

FIG. 2 shows the placement of chips within a field of a video signal. Lines 1-21 comprise vertical blanking intervals and any VBI information (closed captions, etc.) located on these lines, as is known in the art. In the preferred embodiment of the invention, the chip synchronization pattern is transmitted. When the sync pattern is detected, it knows where the chip line following the sync pattern is, so that the decoders in any television receiver can operate in sync. The synchronization pattern itself may be one of the 16PN sequences or a different sequence. For every television set, the first PN sequence detected in the field is the sync pattern and is associated with the symbol, even if it is one of the 16 sequences associated with the 16 symbols that may be transmitted. It turns out that it is not a chip sequence. As will be described later, the sync pattern is detected in the same way as the detection of other chip sequences.

In the preferred embodiment of the present invention, the synchronization pattern begins at line 25. However, the received signal may have an earlier start, such as line 23, or a later start, such as line 27. The reason for this is that the processing of the video signal after the encoder has the effect of moving the first line up or down one or two lines by stripping and then reinserting the horizontal and vertical sync pulses. Because there is. For this reason, the decoder must start looking for the sync PN sequence a little earlier and continue until a little later. The sync pattern is
Coded on lines 25-32. The first line that the television set looks for with respect to the beginning of the sync pattern is line 23 and the last is line 34.

The data immediately follows the sync pattern. Eight chip lines are used for each symbol transmitted. Thus, if the data begins on line 35, the last available line is line 258. Therefore, there are 224 chip lines, and 28 groups of 8 lines each are possible. Each of the eight chip lines represents 4 bits (each symbol in the exemplary embodiment of the invention represents 4 bits), so that (28) * (4) data bits are represented per field. . At a 60 field / second rate, the data rate is 7200 bps
Is.

It should be noted that standard error correction techniques can be used, which reduces the bit rate. However, the error correction itself does not form part of the present invention. It is also believed that the data rate can be increased by using standard forms of data compression. In general, it is estimated that typical application bit rates will be slightly lower than 7200 bps.

Before proceeding to a description of the encoding hardware and process, it will be helpful to understand the decoding process of FIG. 7 because the decoding steps are actually done during encoding. The first two graphs in FIG. 7 show two consecutive video lines with chip pattern 1001. In the first line, a small voltage is added for each chip of value 1 and a small voltage is subtracted for each chip of value 0. The addition and subtraction operations are reversed for the second paired line.

The third graph in FIG. 7 shows the result of integrating each line over the duration of each chip. The solid line represents the integral of line 2 over each chip duration,
The dashed line also represents the integral of the tip in line 1. The value represented by the black circle is the final integration result over the course of the chip in line 1 and reflects both the integral of the video signal itself and the superimposed chip value. Each value represented by the symbol x is the integral over the course of the chip in line 2.

The last graph in FIG. 7 represents what is referred to herein as the “integral tip value”. The integral tip value is simply the difference between the integral over the course of the tip in line 1 and the integral over the course of the corresponding tip in line 2. In FIG. 7, the integral of the first chip in line 1 is greater than the integral of the corresponding inverted first chip in line 2, so the integral chip value for this chip pair is positive and is represented by 1 in the last graph. To be done. On the other hand, the integral of the second chip is
It is larger for line 2 than for line 1 and therefore the integral chip value is negative and represented by 0 in the last graph. Similar remarks apply to the third and fourth integration tip values.

Although the video signal in the first two graphs is shown flat across all chips, in practice the video signal is constantly changing. Therefore, the integral taken along the tip is multivalued, like the integral tip value. The integration tip value is
Which chips are positive and which are negative (or, more precisely, which chips are sent positive on one line and negative on the next line, and which is first It should be understood that in some cases it may not really reflect (whether sent negatively and then positively). If the video signal changes significantly from one line to the next, the resulting integrated chip value will be controlled by the video, not by which of the opposite polarity chips was transmitted first. Become.

The correlation process is shown in FIG. In fact, each 16PN chip sequence
Correlated to 16 integrated chip values representing the transmitted PN code. The one with the highest correlation value is the "winner" and the received PN code is assumed to represent the associated 4-bit symbol.

The first assumption in FIG. 8 is that the integrator gain and chip duration are such that each integrated chip value is +0.1 or −0.1 volts. In an actual implementation, the integral chip values are multi-valued, and the example of FIG. 8 corresponds to the simplified binary example of FIG. In the example used throughout this description, the correlation process is 1
Relates to a 6-chip sequence, each corresponding to 4 line pairs of 4 integrated chip values. It is also assumed that the integral chip values 1, 0, 0, and 1 of FIG. 7 are checked against only two possibilities 1001 (correct pattern) and 1110.

The correlation process is as follows. The calculated integral chip value of the received PN code is correlated to all possible PN sequences. Possible PN
Each sequence may be provided with an accumulator (only two such accumulators are needed in the examples of FIGS. 7 and 8). Each integrated chip value is processed according to the value of the chip at the corresponding position of each possible PN sequence. PN that is 1
For any chip in the sequence, the calculated integrated chip value corresponding to that position is added to the correlation accumulator for that PN sequence. If the tip is 0,
The integrated chip value is subtracted from the correlation accumulator. As shown in FIG. 8, in the case of the PN sequence 1001, addition, subtraction, subtraction, and addition are sequentially performed. From FIG.
It turns out that the first and fourth integral chip values are positive, the second and third are negative, and subtraction of negative numbers yields a positive result, so four with absolute amounts of 0.1 volts each. All the integrated chip values are the values in the correlation accumulator, 0 in total.
． 4 will be increased. (In general, each increase / decrease in the value of the correlation accumulator in FIG.
． It is 1 volt, because in the simple example shown, all integrated tip values have the same absolute amount. In an actual implementation, the integration tip value is multivalued).

On the other hand, in the case of the PN sequence 1110, addition, addition, addition, and subtraction operations are performed. The last three operations of adding the negative second and third integral chip values of FIG. 7 and subtracting the fourth positive integral chip value of FIG. 7 add the first integral chip value to the accumulator. After that, the initial +0.1 accumulator value decreases 3 times in a row, and the final result becomes −0.2. Therefore, it is assumed that the first PN sequence 1001 has the highest correlation value and the received PN code is the PN sequence 1001.

In the present invention, consecutive line pairs are encoded using opposite polarity potentials as in the above identified US Pat. No. 4,807,031. As shown in FIG. 7, the basic idea is that if one video line is subtracted from another line scan, then one line is subtracted from the other and the rest are all data signals. That is. Of course, continuous line scans are generally not identical, which is why the integrated chip value often has a value that does not accurately reflect the polarity of the chip. Enabling highly accurate identification of the encoded original symbol is
It is a statistical technique represented by FIG. The present invention and the above-identified Patent Nos. 4 and 8
The main difference from the invention of 07,031 is that it operates on individual chips, thus allowing a much higher data rate instead of a single result per field, or at least a single result for a line scan group. That's right. (In fact, as will be described later, the amplitudes of individual chips on the same line are not always the same). Also, the decoding process, including the correlation technique, is quite different from that used in the prior art.

Since each data symbol has 4 bits, it may be considered that 16PN sequences are needed to represent them. In fact, this is the way the invention has been described thus far. If the PN sequence is different for each symbol,
Sixteen correlations must be calculated for each calculated integral chip value sequence. However, there are ways to reduce the amount of computation required by half, which is done as follows in an exemplary embodiment of the invention.

Only 8PN sequences are used to represent 16 symbols. In the present invention, each chip line value is accompanied by a line having an inverse of the chip value. This technique is central to the invention because it relies on having complementary chip lines that allow for cancellation of the video signal from the integrated chip value. Since each chip is transmitted in both its normal and inverted forms, it is clear that transmitting the inverted form first represents something really different. In fact, each integrated chip value for the two lines of FIG. 7 may have an amount of opposite sign when the second line is transmitted first. (But this is not always the case, as the video on the two lines may not be completely different). This means that the representation of 16 symbols requires only 8PN sequences, but each P
The N sequence can be either normal form or inverted form, depending on whether it is encoded first.
It is possible to represent either of the two symbols. In the correlation process,
The "winner" is one of 16 symbols whose corresponding PN sequence (taking into account whether the normal or inverted form is transmitted first) has the highest absolute correlation value. In this case, -2000 is the "winner" for +150.
In this way, for each received PN code, only 8 correlations need to be calculated instead of 16.

The encoding hardware is shown in FIG. The input video is provided to a 10-bit analog to digital converter 10, the output of which is provided to both a digital integrator 12 and a one field delay memory 14. Although all processing is done in the digital domain in the preferred embodiment of the present invention, it need not be. The horizontal sync signal on line 8 synchronizes the digital integrator with each line scan,
Facilitates the extraction of chip values.

The digital integrator processes the received video signal and provides the integrated chip value at the input of the digital signal processor 16. The horizontal sync pulse is provided to the digital integrator on line 16 and the digital integrator and digital signal processor communicate control information on line 18 so that the digital signal processor begins looking for the sync pattern on line 23. be able to. The method by which the digital signal processor detects the synchronization pattern will be described later. (Although not shown, vertical sync pulses can also be advantageously used to synchronize the digital integrator, as will be apparent to those skilled in the art).

It is assumed that data may already be superimposed on the input video signal.
An encoder can be called to add to the original data. For example, the broadcast may include data related to national chain pizza advertisements. Individual TV stations may need to add "local" data to the video signal, for example data relating to how consumers can order pizza for local deliveries. This is why the encoder actually has to detect the data that may be present in the input video signal. What is done is an efficient stripping of this data from the video signal, which will be described later along with a flow chart showing the processing, combining this with new data, and then combining all this composite data into a "clean" video signal from the beginning. It is to encode. In fact, the chip component in the input video signal is not first physically removed from the video. Rather, these components are stored by the digital signal processor (determined by the integral chip value) and then subtracted from the video signal as new data is added prior to broadcasting the video signal.

The output chip amplitude passes to digital adder 22 via line 20. The digital signal processor determines the chip value required for the entire field. Delay memory 1
Since 4 introduces a delay equal to the whole field, the digital signal processor
A new chip amplitude can be given to the field at the beginning of the field as it enters the digital adder.

As described above with the decoding process, subtracting the integral along one chip from the integral along a pair of chips ideally does not affect the video signal itself, and (Or, more accurately, a negative value is subtracted, which is twice the amplitude of each chip in the pair) to give an integrated chip value result. Used to strip the original chip from the input video simultaneously with the addition of a new chip (by assuming the video subtraction process is perfect and calculating the chip amount from half the integral chip value) , The integrated chip value. As described below, the encoder provides chips of variable amplitude depending on the nature of the video signal. The advantage of knowing the original integration chip values can be assumed to be that these integration chip values are accurately determined for the video field being processed by an encoder that first placed them in the video signal, first encoding the same amplitude from this. It is possible to select the same chip position in the video signal to be played.

The output digital field data is provided to the input of the 10-bit digital / analog converter 26, which forms the analog output video. The output video signal (represented at the output of digital adder 22) across line 30 to the digital integrator is processed by digital integrator 28, with the final check that the data was correctly placed in the video signal. To be done. The horizontal sync pulse at the analog output is provided on line 32 to the input of the digital integrator. The control line 34 is the digital signal processor 16
Control digital integrator 28 in the same manner as it controls digital integrator 12. The digital integrator 28 produces an integrated chip value provided to the input of the digital signal processor. These are called output integration chips rather than input integration chips because they represent chips in the output video signal, unlike chips at the original input. The digital signal processor actually decodes the data represented by the output integration chip and verifies that the data was properly placed in the video signal. (This final check is not shown in the flow chart below,
The decoding process is the same as the decoding process performed by any television set, as described below).

Digital signal processor 16 is under master control of microprocessor 38, which communicates with memory 40 and serial input / output lines 42. The details of the microprocessor operation are not important to an understanding of the invention. The microprocessor determines the text to add to the video signal based on the text (if any) already present in the input video signal, and the digital signal processor 1
There is bidirectional communication between the 6 and the microprocessor 38.

If the data is improperly encoded in the video signal, this is determined in a final check by operation on the output integration chip. It's too late to cancel everything. The video has already been sent. What is done is to encode in the next field a message telling each television that in fact the data in the preceding field should be ignored. The data is then re-encoded in the current field.

There are many other cases where it is advantageous to add text or data to text or data that is already on the input video. For example, a McDonald's local franchise merchant may add a cola to the Big Mac offered by McDonald's or may add verification to the coupon. All this is done at a higher level by the microprocessor and is not relevant to the present invention. The present invention is
It concerns how the data is encoded and decoded, but not what it represents. Similar remarks may be advantageously employed, for example, but also apply to error correction protocols that are not part of the invention.

4A and 4B constitute a flow chart of the encoding process. A sync pattern starting with one of the first viewable horizontal lines is added to the video in a manner similar to how other chip patterns are added, as described in detail below. The insertion of the synchronization pattern is not shown in the flow chart in order not to complicate the drawing. The pattern consists of a special PN sequence covering 8 lines, as described above.

In step 11, the next input video field is decoded. Decoding is the same process as described below along with what is done in the television receiver. As mentioned above, the input video signal must be decoded in case the data is already present in the input video signal. In some cases, when adding data,
The entire field may need to be rebuilt, rather than simply adding a tip at a position that corresponds to the data that was originally "stuffed" in the field, or adding the data to a position where there is no data. Data is written again. The integrated chip value is calculated as shown in FIG. 7 and stored in step 25 by the digital signal processor. In step 13, a check is made to see if there is any data in the input video. In some cases, in step 15, the data is decompressed if it was originally compressed and the error is corrected if the original data was sent with error correction. As mentioned above, error correction and compression takes place at a higher level than the steps involved in the method of the invention and does not form part of the invention itself.

In step 17, a check is made to see if there is room for new data in the video signal (ie, there are lines without chips, or either line simply represents a meaningless “stuffing” pattern. Check).
If not, it returns to step 11 where it operates on the next input video field. The current field is simply transmitted through the 1-field delay memory 14 without modification.

On the other hand, if there is room for new data, as determined in step 17, the new data can be added to the old data, the data can be compressed, and error correction code can be added. This is all done by the microprocessor 38. Since the integrated chip value passed to the digital signal processor 16 represents the original chip amplitude, in step 21 the initial coding level can be determined for each group of 8 lines. In step 23, for each chip in the 8 lines representing the symbol, a table is formed representing the amplitudes to be added to or subtracted from the video.

In step 21, the initial coding level is determined for all chips in each group of 8 lines representing a 4 bit symbol. Individual chips may have different amounts, but it is not feasible to determine what the different amounts are at the time of initial coding. The best that is feasible is to estimate the initial coding level for a group of chips and then use all chips corresponding to a particular symbol to estimate the average coding level for 16 chips corresponding to a symbol. Is.
This is why in step 21, the original coding level is estimated for the 8-line group corresponding to each symbol. Not all integrated chip values are used in this process. In step 11, when the input video field is first decoded, integration chip values that are too large are ignored.
(This will be clear if the decoding process is considered in detail on its own). Therefore, not all integrated chip values are available even for the estimation of the initial coding level in step 21. The same value is placed in the chip amplitude table for all chips representing each symbol. If the video changes significantly from line to line, that value is only an estimate, as the individual integrated chip values themselves may not accurately reflect the difference between the chip amplitudes. Nevertheless, an initial estimation of the original coding level is made. This level is used to strip each of the original chips in the eight lines being processed after the modifications described below. It should be appreciated that the chip amplitude table is set according to the symbols determined in step 11. Since these are the symbols with the highest correlation values during the decoding process, the 16 chips corresponding to each symbol in the field are known. The term "inversion pattern" in step 23 refers to inverting, i.e. eliminating, the chips that are in the video signal, using the stored chip amplitude.

If it is determined in step 13 that the input video has no data, the microprocessor 38 builds the data in the new field. This is shown as done in step 27. Since the input signal has no tip,
There is nothing to strip. Therefore, in step 29, 0 is first stored in every chip in the chip amplitude table.

When the process enters step 31, the chip amplitude table consists of either all zeros or, ideally, "inverted" values that strip the original chip from the video signal. Therefore, in step 31, the system can start adding chip amplitude of new data as if there were no chips to start. The microprocessor determines the data to encode, and thus the PN sequence. The digital signal processor adds the lowest possible chip amplitude of the new data to the chip amplitude table. Any integral chip value is a function of chip length, integrator gain, and chip amplitude. The system knows the chip length and integrator gain of any receiver, and therefore also the lowest chip amplitude of each new chip for use in step 31.

At this point, the chip amplitude table contains the value of the chip to add at each position in the video field. Each value is the sum of the voltage estimate designed to eliminate the original chip in the input video and the voltage adding a new chip, so it can be decoded correctly. Next, tests are carried out in the entire digital domain to see if the output video is properly decoded at the television receiver. Each integrated chip value stored in step 25 is added to the integrated chip value component introduced into the chip amplitude table by any chip pair. The sum calculated in step 33 represents the integrated chip value calculated in any television set. (The input integrated chip value is not actually added to the chip amplitude table, as this table represents the chip amplitude added to the video signal and the value should not be changed during the test. It is also possible to use the table for testing).

In step 35, the simulated video signal is decoded. The signal is simulated because the actual analog signal is not sampled. Instead, the integral tip value derived in step 33 is used. The normal decoding process takes place in step 35, which will be described in more detail below, but reflects the algorithm shown in FIGS. 7 and 8. In step 37, a check is made to see if all symbols have been correctly decoded. (It goes without saying that many chips give rise to integrated chip values that do not correspond to chips in the PN sequence being transmitted. The maximum that can be expected is that the statistical test produces the exact symbol "winner" of the field. is there). The test is
Whether all symbol data bits represented in the field are accurate. If any symbol is incorrectly decoded, the amplitude of the corresponding chip in the associated PN sequence is fixed by a fixed amount (in the chip amplitude table of step 39).
For example 20% of the maximum maximum minimum amplitude). (A technique similar to increasing tip amplitude is not described in the above-identified Broughton et al. Patent, but was actually implemented in a commercial use of the Broughton et al. Invention.)
. If any chip amplitude exceeds the maximum allowed chip amplitude, as determined in step 41, the data is not stored in the field being processed and control returns to step 11. On the other hand, if the chip amplitude does not exceed the maximum, then in step 43 the chip amplitude table is updated and the process repeats to input the input integrated video chip values into the chip amplitude table during the simulated encoding process and then the decoding process. to add.

Finally, if all the bits are decoded correctly, chips are added to the adder 22 as needed when the field leaves the field delay memory 14. The system then returns to step 11 to decode the next input video field.

If it is determined in step 41 that it is not possible to increase the amplitude of the chips in the erroneous PN sequence without exceeding the maximum level, instead of not transmitting the data on the field, the analog / digital It is possible to send the video with the data at the input of the converter 10. (The converter can be 8 bits, 10 bits, 12 bits, or any other suitable value).
Although the shuffling of data fields may not be feasible, there is no reason why fields cannot be broadcast with their original data.

The decoder is shown in FIG. Input video is provided to a 10-bit analog-to-digital converter 50. A video sync separator 56 extracts horizontal sync pulses from the video and provides them to the trigger input of digital integrator 52. In this way, the digital integrator can form an integral over each chip and calculate the integrated chip value as shown in FIG. These values are conveyed to the microprocessor 54, which is also provided with sync information from the video sync separator. The microprocessor determines which symbol corresponds to the received PN sequence. It will be recalled that the decoding process is carried out at the output of the encoder shown in FIG. 3, preferably in hardware during encoding, as described above. The encoder has to perform much more processing and its microprocessor has more power than the microprocessor of each decoder. Therefore, it is possible to perform the decoding in step 11 of the entire encoding process in software rather than hardware. However, regardless of how it is performed, the logic of the decoding process is the same in both cases, and either hardware or software may be employed in either case.

6A and 6B are flowcharts of the decoding process. The generation of the integrated chip value has already been described in conjunction with Figure 7, and Figure 8 shows the correlation process using the results of Figure 7. The flow chart shows exactly how and when the integrated chip value is derived and how to perform the correlation process.

In steps 51 and 53, the system looks for vertical and horizontal syncs. When the first horizontal sync of a new field is detected, it determines whether to check the sync PN sequence. In step 55, the system begins looking for the sync sequence on line 23, even though the sequence is encoded on line 25 in the field. As mentioned above, this is because the post-encoder processing may move the first line up or down one or two lines. For this reason, the decoder must start looking for the sync PN sequence a little earlier and continue to look a little later.

After integrating the chips of 12 lines of data, the synchronous PN sequence is being transmitted on 8 of these lines. The synchronous PN sequence is correlated to 16 integral chip values derived from the first 8 lines. Result is Step 5
A check is made whether the last line (line 34), which is stored at 7, and possibly has sync chips, has been processed at step 59. If not, return to step 53. The synchronous PN sequence starts with the line 23 ...
It is correlated with the integrated chip value derived from 30. On the next lap, line 24
Correlated with the integrated tip value derived from ˜31. This process continues,
The final correlation is that of a synchronous PN sequence with 16 integrated chip values on lines 27-34. (As mentioned above, the synchronous PN sequence may be one of the PN sequences used to represent a 4-bit symbol, or it may be a completely different sequence).

In step 61, the best sync correlation result is determined. This finds the first chip line that represents the data. The first data PN code starts immediately after the synchronization sequence. (The best sync correlation result must be at least 100% greater than the second highest sync correlation, otherwise the entire test is ignored and the system waits for a new field).

In step 63, the 8 lines of the next data PN code are integrated and stored and then the integrated chip value is calculated. The integrated chip value can be derived by integrating the video signal over the course of the chip and then subtracting one value from the other, or the subtraction may be performed before the integration. Next, in step 83, the system selects the first one of the possible 8PN sequences to correlate with the received data code.

A check is made to see if any integration chip value is too large. The threshold used for testing is unique to every system. At step 65, the first integral chip value of the new PN code is accessed and at step 67 the value is checked. For example, if the value is a full video, that is, the highest value integrated using the same video for both paired chips (1.5 (or
In another example, if it is greater than 2.0) times, the integral chip value must have been overly influenced by the video signal. For example, if the maximum amplitude that can be added to the video signal is 30 millivolts, then the integral chip value for the two chips should be (30 millivolts) (2) (chip width in milliseconds) (integrator gain). is there. With full video (meaning the video in process of the two chips is the same)
, Note that the equations do not include video because the videos are offset. Also, there is a factor (2) in the calculation because the tip amplitude of -30 millivolts is subtracted.
(Alternatively, if the first tip is negative, the final result is twice the size, but
Is negative). If the paired horizontal lines are not similar over the duration of the paired chips, then any integral chip value will be too large. If the value is not too large, then in step 69 it is included in the correlation accumulator for the PN sequence under test. Referring to Figure 8, the correlation accumulator for each of the possible 8PN sequences (always 16 if the inverted code is not sent first) is simply an adder. Each integrated chip value is either added to or subtracted from the sum depending on the value of the corresponding chip in the PN sequence. Each accumulator can have a positive or negative value.

At step 71, a test is made to determine if the previous integrated chip value was too large. If not too large, branch to step 85. This purpose will be described later. However, if the preceding integrated chip value is too large, no further processing is performed on the current integrated chip value and the process branches directly to step 73. here,
Determine if all chips in the PN sequence under test have been processed. If not, return to step 65 to get the next integrated chip value. At step 75, performed after all 16 integration chip values have been processed for the PN sequence under test, it is determined whether all 16 PN sequences have been compared to the 16 integration chip values being processed. If not, then in step 79 the next PN sequence is selected and returns to step 65 to process the first integrated chip value, this time using the newly selected PN sequence.

Finally, in step 77, the PN sequence with the highest correlation accumulator size is selected as the “winner”. As mentioned above, positive and negative values are 16
Corresponds to a different one of the PN sequences. In step 81, a check is made as to whether all data has been processed for this field. If yes, return to step 51. If no, step 63
And thus the next data sequence can be processed.

The question is what to do with the integral chip value that is determined to be too large in step 67. Also, it has not yet been described what additional processing is to be performed when the current integration chip value is determined not to be too large in step 67, and the previous integration chip value determined in step 71 is also not described. The same applies. The latter sequencing is described first, the first integration chip value with the preceding integration chip value being the second.

In processing the first integrated chip value in the first iteration for each PN sequence, there is no preceding value and the response to the test in step 71 is set to yes. If it is determined in step 67 that the second integrated chip value is not too large, then again in step 69 the value is included in the correlation accumulator of the PN sequence being operated on. Then, when step 71 is executed, there is a preceding integral chip value. If this was not too large, then in step 85 a test is performed to see if the current and previous chip values match the PN sequence under test. The next chart of step 85 is that if the PN sequence under test has 00 or 11 for the two chip positions under consideration, and 2
If two integrated chip values have the same sign, then branch to step 89 is indicated. Since the PN sequence can be transmitted first in either normal or inverted form and then in inverted or normal form, the integral chip value of either sign is correlated to the particular PN sequence under test. Value can be increased (final "
"Winner" is the correlation value that has the greatest absolute amount, even if it is negative)
I must remember that. Thus, as long as there is a "match" in step 85, it is shown that there are two consecutive integrated chip values that correlate with the PN sequence under test. Since there are two "hits" in succession, the input PN code being processed is more likely to correspond to the PN sequence being tested. For this reason
In step 69, the integrated chip value is not only included (added or subtracted) in the correlator accumulator, but also a second time as a result of the matching decision in step 85.

Moreover, if the previous integrated chip value is different from the current one, it is more likely that the integrated chip value is more accurate than if the previous and current values were of the same sign. This is because the neighboring chips not only match the PN sequence under test,
This is because there is most likely no line-by-line video bias that affects the sign of the integrated chip value when the polarities are different. For this reason, a test is performed in step 89 to see if the sign of the preceding chip is the same as or different from the sign of the current chip. The end result is that if both consecutive integration chip values have polarities that do not match the corresponding chips in the PN sequence under test (determined in step 85), branch to step 73 to determine the current integration chip. The value is added to the correlation accumulator only once in step 69. If both the current and the previous integral chip value match the corresponding chip in the PN sequence under test (determined in step 85), and have the same sign in step 89. If it is determined in step 87 that the current integral chip value is in step 85, then there is a sequence of at least two integral chip value sequences that match the PN sequence under consideration. , Is added to the correlation accumulator again or subtracted from the correlation accumulator. Finally, if at step 89 it is determined that the current integrated chip value has a different sign than the previous integrated chip value, then at step 91 the current integrated chip value is included twice more in the correlation accumulator.

Steps 81, 93, 95, and 97 have not yet been described, and an understanding of these steps requires consideration of FIGS. 9A, 9B, and 10.
The test at step 67 is whether the integrated chip value being processed is too large. If too large, so that the difference between the integrals over the duration of the two chips in each pair exceeds the maximum difference between the two polarities of the opposite chips, and thus the integral chip value is too video dependent. It means that there was a change line by line in the video. For the PN sequence under test for the input data sequence, if the preceding chip is of the same polarity as the current chip, there is nothing that can be done to the integrated chip value and branch to step 73. From any point of view, the integrated chip value being processed is ignored and not added to or subtracted from the correlation accumulator of the PN sequence under test. This simply means that the PN sequence under test is unlikely to be the "winner." However, if the preceding chip of the PN sequence under test has a different polarity than the current chip, then in step 93 the preceding integrated chip value is subtracted from the current integrated chip value. If the difference is too large (this means that
Again, there is no way it is possible to use the current integral chip value and branch to step 73. However, if the difference is not too large, then in step 97 the difference is included in the correlation accumulator before proceeding to step 73. The reason why this technique works will be clear from a consideration of FIGS. 9A, 9B, and 10.

Referring to FIG. 9A, two consecutive video lines are shown in an inverted chip pattern. The most important point to observe is that in the first case the video is shown as having a value of 0.5 Volts and in the second case it is shown as having a value of 0.2 Volts. It is clear that the difference between the two video biases is three times larger than the highest and lowest amplitude of the chip, with a maximum peak chip amplitude of 0.1 volts. The third line in FIG. 9A assumes that the integrator gain is 1, in this case taking into account the video bias, two of the integration chip values are 0.4 and two are 0. It turns out that it is .2. All four values are too large and clearly reflect different video biases.

FIG. 9B shows why video bias between lines causes errors in signal decoding. Looking at the first line in FIG. 9A, the chip sequence being transmitted is 1001.
It is clear that FIG. 9B shows a PN sequence 1 in which the input PN code is correct.
The processing is shown when compared against 001 and the incorrect sequence 1110. Using the usual rules, a 1 in the PN sequence being compared against the input code causes the integrated chip value to be added to the accumulator and a 0 causes the integrated chip value to be subtracted from the accumulator. For the exact PN sequence 1001, four consecutive integration chip values 0
． 4, 0.2, 0.2, and 0.4, respectively, are added, subtracted, subtracted, and added to the correlation accumulator, resulting in a final value of 0.4.

For the incorrect PN sequence 1110, the four integrated chip values are added, added, added, and subtracted to the accumulator. This gives the same final result 0.4 as for the exact PN sequence. As a result, the line-to-line bias clearly causes errors because the effect of the four integrating chip values on the correlator accumulators of both the exact and inaccurate PN sequences is the same.

FIG. 10 identifies two rules that implement steps 93, 95, and 97 if the current integrated chip value being processed has a different polarity than the previous integrated chip value. Rule 1 is that if the current integrated chip value corresponds to an amount of chip amplitude greater than 1.5 times the maximum high / low chip amplitude, it is not used except as described in rule 2. This rule basically represents the subsequent processing in steps 93, 95, and 97, and the chart at the bottom of FIG.
The application to N sequences 1001 (exact) and 1110 is shown.

Normal addition or subtraction rules apply, meaning that a PN chip of 1 should add the integrated chip value to the correlation accumulator, and a PN chip of 0 will add the integrated chip value to the correlation accumulator. Indicates that should be subtracted from. The "differs from last" column indicates whether the chip under consideration is the same as or different from the preceding chip. Symbol NA (
Not applicable) refers to the fact that the first chip in each sequence has no predecessor chip and is therefore not the same or different. The "out of range" column simply means that the test in step 95 indicates that the integrated tip value is too large. Figure 9A
, All four example integration chip values under consideration are 0.2 or 0.
． 4, which exceeds the maximum and minimum chip amplitude of all 0.1 volts by more than 1.5 times. The last column shows how the correlation accumulator is affected by the two rules.

For the first PN sequence 1001, the first chip does not differ from the previous chip in the PN sequence (since there is no previous chip), so the first integrated chip value is ignored. The correlation accumulator remains zero. The next chip is different from the previous chip, so the rule subtracts the previous integrated chip value from the current integrated chip value in step 93 and then the difference is subtracted from the correlation accumulator (in the PN sequence under test). The second chip is 0). From FIG. 9A, the previous integral tip value is 0.4 and the current integral tip value is 0.2, so the difference is −0.2. When this value is subtracted from the correlation accumulator, the correlation accumulator becomes +
A value of 0.2 is shown. The third integrated chip value is ignored because the chips in the PN sequence under consideration have the same value as the previous chip. Finally, the fourth chip is 3
Since it is different from the third, in the last step of the processing of this example, the third integrated chip value is subtracted from the fourth and the difference is added to the correlation accumulator. The last integrated chip value is 0.4 and the third is 0.2, so the difference is 0.2, which is added to the accumulator to give the final result of +0.4.

In the case of an incorrect PN sequence 1110, it is clear that the first three integrated chip values are ignored in any of these cases, since the previous chip is the same as the current one. However, because the fourth chip in the PN sequence is 0 and the third is 1, the third integrated chip value is subtracted from the fourth and the difference is subtracted from the correlation accumulator. This gives a correlation accumulator result of -0.2.

Comparing the two results and recalling that the “winner” is the one with the largest absolute quantity, the process is at least some integrals too large to affect the process and the correlator accumulator. It is clear that we allowed a chip value.

Note that in step 95, a test is done to see if the difference is too large. In all cases considered in the example of FIG. 10, where the previous integration chip value was subtracted from the current integration chip value and the current integration chip value was added to or subtracted from the correlation accumulator. , The difference is +0.2 or −0.
It was either 2. The absolute amount of such a difference is the maximum and minimum chip amplitude of 1.5.
Greater than double the test at step 67. However, the test at step 95 is whether the difference is three times the highest and lowest chip amplitude. The reason for this is that the subtraction operation of step 93 aimed at removing the video bias actually doubles the integrated chip value information. For the PN sequence under test, if the leading and current chips have different signs, then two consecutive integral chip values should have opposite signs. When one is subtracted from the other to remove video bias, this has the effect of doubling the contribution of the chip itself. This is why the test threshold of step 95 is twice the test threshold of step 67. In any case, if the difference determined in step 93 is greater than 3 times the highest and lowest tip amplitude, then branch to step 73 and ignore the integral tip value being processed.

Referring again to FIG. 9A, this additional processing results in too large an integral tip value
We can still see why it is possible to contribute to the correlation accumulator. If there should be a transition in chip polarity (determined in step 81), both the integrated chip value before the transition and the integrated chip value after the transition are such that the video bias in one line is greater than the video bias in the other. Also has a large coefficient due to being much larger. However, when one integrated chip value is subtracted from the other, the video bias difference disappears. Because the chip values are different, the contributions of the chips to the integrated chip value have different signs, and one is subtracted from the other, so what is really left is an absolute quantity equal to the sum of the two absolute quantities. The system actually has no way of knowing that two consecutive input chips have different values, i.e.
There is no guarantee that this technique will work because there is no way to know that there is a transition between two chips. The test in step 81 simply relates to whether the PN sequence under test has two consecutive chips of opposite values. Final test is step 95
Whether the difference in is too large. If it is too large, it means that there is no way possible to use the integral tip value. However, if it is not too large, it is assumed that the difference in the integrated chip values accurately reflects the value of the current chip, so the difference is included in the correlation accumulator of the PN sequence under test.

The reason why it is desirable for the PN sequence used to represent transmittable symbols to have a large number of transitions is that in step 81 the current PN sequence under test transitions between the chip positions being processed. 9 only if it is determined to have
This is because the processing shown in A, FIG. 9B, and FIG. 10 is performed. Preferably, for an 8-chip PN sequence, each PN sequence has at least 5 transitions,
There should only be at most 5 0's or 1's in a row.

For ease of explanation, for the present invention, each PN sequence has 8 lines, each 4 chips, and the lines are paired (normal and inverted), so that each PN sequence actually has 16 lines. It was explained from the perspective of including different information items of. In a practical implementation, each line preferably has 20 chips. This is shown in FIG. In general, the number of lines per PN sequence, the number of chips per line, the chip amplitude, the chip start point, and the number of PN sequences possible for a symbol of any size can all be changed. The error rate is improved by increasing the number of chips per line. However, as chips get smaller, line synchronization becomes more important and for this reason decoding of video signals is more difficult.

The preferred parameters are shown in FIG. The first chip starts about 8 microseconds after the rising edge of the horizontal sync pulse. The chip width is 2.3 microseconds and the maximum and minimum chip amplitude varies from 5 millivolts to 20 millivolts. The starting horizontal line is line 25 and the ending horizontal line is 233. Similar to the above exemplary embodiment of the present invention, there are 8 lines for each data symbol, 8 data patterns (PN sequence) are used for 16 symbols, and 2
Five data patterns are encoded in each video field. In the exemplary embodiment of the invention, the raw data rate is 10 per field because each symbol represents 4 bits and there are 25 data patterns encoded in each video field.
It is 0 bit (6000 pbs for a field rate of 60 fields / sec).

It should be appreciated that there are many other ways in which the present invention may be practiced. For example, instead of synchronizing the decoding with the rising edge of the horizontal sync pulse on each line, the process may be synchronized with the color burst signal or some other feature.
The video signal with the data superimposed can be detected optically as in the above-identified Brownton et al. Patent, or it can be detected electrically by operating directly on the video signal. There is no uniqueness in representing 16 4-bit symbols or 8 lines per symbol using an 8PN sequence. For example, 16 PN sequences may be used instead of 8. If these 16 sequences can be transmitted initially in either normal or inverted form, then 32 symbols can be represented. If 10 lines are used instead of 8 and the PN sequence is lengthened (assuming the chip width remains the same), then 5 bits are represented by 10 lines instead of 4 bits by 8 lines and the data rate Remains the same. However, in general, the greater the number of possible PN sequences, the higher the probability of incorrectly decoding the input sequence and the longer the processing time required to determine the correct sequence.

In an exemplary embodiment of the invention, once the input PN code is determined, the possible P
One is tested for each N sequence. Rather than running each PN sequence test individually, custom hardware can be employed to process all PN sequences in parallel. In the exemplary embodiment, analog /
The digital converter is a 10-bit device. It is possible to use an 8-bit converter, but this increases the probability of error because the coded signal is much smaller.

In the exemplary embodiment of the invention, the consecutive lines of each PN sequence are paired, but it is also possible to interleave the PN sequences differently. Since we expect the rest to reflect only the data signal, in order to remove the video, we have to derive the integral chip value and we have to subtract the two inversely encoded lines from each other, It is necessary to send each PN sequence in its normal and inverted forms. It may be more preferable to separate the paired lines by a few lines, as it may improve the error rate if the "bad" part of the video is unlikely to cover several lines in a row. In other words, if a part of the PN sequence is damaged, it is better that both lines in the pair are not damaged. However, it is desirable not to change the average luminance and the subtraction process works best when the video signals on the two lines in the pair are similar (more likely if the lines are adjacent). Therefore, the paired lines should not be too far apart. As used in the claims, "paired" lines should be within about 5 of each other. However, the continuous line method is preferred because it is the simplest and requires the least computer memory to implement.

Instead of modulating the luminance part of the video signal, it is possible to modulate the chrominance. In practice, especially the chrominance and luminance signals do not interfere too much with each other, so it is possible to modulate both and thus double the data rate. It may also be possible to modulate the chrominance signal at a higher amplitude and thus at a higher data rate with the same error probability as the luminance signal. However, in general, more complex equipment is required for the modulation and demodulation of chrominance signals.

All encodings are preferably on a field-by-field basis, ie the PN sequence does not go over consecutive fields. The reason for this is that when moving from a TV show to a commercial, for example, the video signal may be edited and the data may be interrupted if the PN sequence is not entirely contained in a single field. .

Although the present invention has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the application of the principles of the invention. Many modifications may be made and other configurations may be devised without departing from the spirit and scope of the invention.

[Brief description of drawings]

FIG. 1 is a diagram showing how a typical PN sequence associated with each symbol is superimposed on a line scan of a video signal.

FIG. 2 is a diagram showing a case where data is transmitted in each video field.

FIG. 3 shows an exemplary encoder at a video signal broadcast site.

FIG. 4A is a flowchart showing an encoding process.

FIG. 4B is a flowchart showing an encoding process.

FIG. 5 shows an exemplary decoder in a television receiver.

FIG. 6A is a flowchart showing processing in the television receiver.

FIG. 6B is a flowchart showing processing in the television receiver.

FIG. 7 is a diagram showing how each “integrated chip value” is derived.

FIG. 8 illustrates the correlation process of the present invention.

FIG. 9A is a diagram showing the effect of line-to-line video bias.

FIG. 9B is a diagram showing why such a bias leads to decoding errors.

FIG. 10 provides rules used to eliminate errors introduced by line bias, and typical examples of using such rules.

FIG. 11 is a diagram showing preferable parameter values.

[Explanation of symbols]

10 10-bit A / D, 12 digital integrator, 14 1-field delay memory, 16 digital signal processor, 22 digital adder, 26 10-bit D / A, 28 digital integrator, 38 microprocessor, 40 memory,
50 10-bit A / D, 52 digital integrator, 54 microprocessor,
56 video sync separator.

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE), OA (BF, BJ , CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, K E, LS, MW, SD, SL, SZ, UG, ZW), E A (AM, AZ, BY, KG, KZ, MD, RU, TJ , TM), AL, AM, AT, AU, AZ, BA, BB , BG, BR, BY, CA, CH, CN, CU, CZ, DE, DK, EE, ES, FI, GB, GE, GH, G M, HR, HU, ID, IL, IS, JP, KE, KG , KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MD, MG, MK, MN, MW, MX, N O, NZ, PL, PT, RO, RU, SD, SE, SG , SI, SK, SL, TJ, TM, TR, TT, UA, UG, US, UZ, VN, YU, ZW (71) Applicant One Memorial Drive,             Suite 2000, St. Louise,             MI 63102, United State             s Of America (72) Inventor Siaduro, Daniel Andrew             Ka, Laura, Missouri, United States             Tree Road 5480, 1386 (72) Inventor Cosbar, Kurt Lewis             Laura, Les, Missouri, United States             Ard Avenue 52 (72) Inventor Chap, Christopher Eric             Laura, No, Missouri, United States             Source State Street 801 F-term (reference) 5C063 AB01 AB07 DB09

Claims (38)

[Claims] 1. A method of superimposing data on a visible portion of a video signal, the method comprising: (a) converting an input video signal into a digital representation; and (b) for each of a plurality of data symbols, each of the data symbols. Assigning each chip pattern having more chips than the number of bits represented, each chip pattern having a plurality of chips to be superimposed on the video signal in a line pair having a normal form and an inverted form, respectively. And (c) creating a chip amplitude table having digital values representing the value of each chip to be superimposed on the video signal at corresponding positions, and (d) the input. A representation of the video signal and the chip represented at its corresponding position in the chip amplitude table Deriving a digital representation of the output video signal by digitally adding, and (e) superimposing on the output video signal by digitally computing the digital representation derived in step (d). Simulating the decoding of the selected data, (f) increasing the value in the chip amplitude table if the decoding simulation of step (e) produces erroneous results, and (g) After the values in the chip amplitude table are increased so that the decoding simulation of (e) produces accurate results, the digital representation of the input video signal and its corresponding position in the chip amplitude table are displayed. A visible portion of the video signal, the step of generating an output video signal from the chip value being How to superimpose the data on. 2. The method further comprises: (h) decoding the input video signal to derive a digital representation of any data superimposed thereon, the steps (d), (e), and (g). The method of superimposing data on a visible portion of a video signal according to claim 1, wherein all include additional utilization of the digital representation derived in step (h). 3. In the step (g), the chip amplitude table is used to include chips with opposite polarities in the line pairs in the output video signal to superimpose data on a visible portion of the video signal. how to. 4. The decoding in steps (e) and (h) derives a difference in the integral of the video signal computed over the course of each pair of chips of opposite polarity and determines each of the chip patterns. Statistically correlating to the integral difference and determining the highest correlation. 5. In the step (g), the chip amplitude table is used to include chips of opposite polarities in the line pairs in the output video signal to superimpose data on a visible portion of the video signal. how to. 6. The decoding in step (e) comprises deriving a difference in integral of the output video signal calculated over the course of each pair of chips of opposite polarity.
The method of superimposing data on a visible portion of a video signal according to claim 5, comprising statistically correlating each of the chip patterns with an integral difference and determining the highest correlation. 7. Decoding said input video signal to derive a digital representation of any original data superimposed thereon, removing said original data from said output video signal, said original data The video of claim 1, further comprising: deriving synthetic data in combination with new data; and using the synthetic data in performing steps (d), (e), and (g). A method of overlaying data on the visible portion of a signal. 8. The step (g) includes using the chip amplitude table to include chips of opposite polarities in line pairs in the output video signal to superimpose data on a visible portion of the video signal. how to. 9. Decoding in said step (e) derives a difference in integration of the output video signals calculated over the course of each pair of chips of opposite polarity,
The method of superimposing data on a visible portion of a video signal according to claim 9, comprising statistically correlating each of the chip patterns with an integral difference and determining the highest correlation. 10. A method of superimposing data on the visible portion of a video signal, comprising the steps of: (a) converting the input video signal into a digital representation; and (b) for each of the plurality of data symbols, each of the data symbols. Assigning each chip pattern having more chips than the number of bits represented, each chip pattern having a plurality of chips to be superimposed on the video signal in a line pair having a normal form and an inverted form, respectively. And (c) creating a chip amplitude table having digital values representing the value of each chip to be superimposed on the video signal at corresponding positions, and (d) the input. A digital representation of the video signal and its corresponding position in the chip amplitude table. That from the chip value, a method of superimposing data in the visible portion of the video signal and generating an output video signal. 11. The method further comprises: (e) decoding the input video signal to derive a digital representation of any data superimposed thereon, wherein step (d) is derived in step (e). The method of superimposing data on a visible portion of a video signal as claimed in claim 10 including the additional use of the rendered digital representation. 12. The step (d) uses the chip amplitude table to include chips of opposite polarities in line pairs in the output video signal to superimpose data on a visible portion of the video signal. how to. 13. Decoding the input video signal to derive a digital representation of any original data superimposed thereon, removing the original data from the output video signal, and removing the original data. 13. Superimposing data on the visible portion of the video signal of claim 12, further comprising: deriving synthetic data in combination with new data; and using the synthetic data in performing step (d). Method. 14. In the step (d), the chip amplitude table is used to include chips of opposite polarities in line pairs in the output video signal to superimpose data on a visible portion of the video signal. how to. 15. A method of superimposing data on a visible portion of a video signal, comprising: (a) each of a plurality of data symbols is provided with a chip pattern having more chips than the number of bits represented by each of the data symbols. Allocating, each chip pattern having a plurality of lines, each having a plurality of chips, to be superimposed on the video signal in a line pair having a normal form and an inverted form respectively, and (b) A visible portion of a video signal comprising: creating a composite digital representation of a chip pattern corresponding to the video signal and data symbols to be superimposed on the video signal; and (c) generating a video signal from the composite digital representation. How to superimpose data on. 16. (d) Decoding the video signal to determine any data originally superposed thereon prior to performing step (b); and (e) step (d). 16. The method of superimposing data on a visible portion of a video signal according to claim 15, further comprising the step of partially determining data symbols to be superimposed on the video signal using the decoded data in. 17. The data in the visible portion of the video signal of claim 16, wherein in step (b) chip patterns representing any original data determined in step (d) are removed from the digital representation. How to superimpose. 18. A method of decoding data represented in a visible portion of a video signal, the video signal comprising, for each of a plurality of data symbols, more chips than the number of bits represented by each data symbol. The corresponding chip pattern having a plurality of lines each having a plurality of chips superimposed on the video signal, each chip pattern being arranged in line pairs having a normal form and an inverted form, respectively. (A) deriving an integrated chip value for each position in each line pair in a line representing a chip pattern corresponding to a single data symbol; and (b) an integrated chip value derived for a single data symbol, Correlating to all chip patterns corresponding to each one of the plurality of data symbols; (C) identifying a data symbol represented in the visible portion of the video signal according to a chip pattern having the highest correlation with the data symbol, and decoding the data represented in the visible portion of the video signal. . 19. The step (b) includes: (b1) For each of the chip patterns, integrates the value stored in each correlation accumulator if the corresponding chip in the pattern has a first polarity. And (b2) for each of the chip patterns, when the corresponding chip in the pattern has the second polarity, the substep of reducing the value stored in each correlation accumulator by the integrated chip value. 19. A method for decoding data represented in the visible portion of a video signal according to claim 18, comprising: 20. The difference function does not exceed a second threshold level and the correlated chip pattern is inverse at a position corresponding to any integrated chip value and a preceding integrated chip value above the first threshold level. The arbitrary integral tip value is not directly used for the correlation in step (b), but instead is used as part of a difference function with the previous integral tip value. 20. A method for decoding data represented in the visible part of a video signal according to claim 19. 21. Any integral tip value that does not exceed the first threshold level is:
If the arbitrary integrated chip value and the preceding integrated chip value have polarities that both match the polarities of the two chips in the correlated chip pattern, the extra amount for the correlated chip pattern. 20. A method of decoding data represented in the visible part of a video signal according to claim 19, which increases the correlation. 22. Any integral chip value that increases the correlation by an extra amount for the correlated chip pattern has a different polarity for the correlated chip pattern, where the integrated chip value and the preceding integrated chip value are different. 22. The method of decoding data represented in the visible portion of a video signal according to claim 21, wherein the method comprises increasing the correlation by a greater amount. 23. The difference function does not exceed a second threshold level and the correlated chip pattern is inverse at a position corresponding to any integrated chip value and a preceding integrated chip value above the first threshold level. The arbitrary integral tip value is not directly used for the correlation in step (b), but instead is used as part of a difference function with the previous integral tip value. 19. A method for decoding data represented in the visible part of a video signal according to claim 18. 24. Any integral tip value that does not exceed the first threshold level is:
If the arbitrary integrated chip value and the preceding integrated chip value have polarities that both match the polarities of the two chips in the correlated chip pattern, the extra amount for the correlated chip pattern. The method for decoding data represented in the visible part of a video signal according to claim 18, wherein the correlation is increased. 25. Any integral chip value that increases the correlation by an extra amount for the correlated chip pattern has a different polarity for said correlated chip pattern, said integral chip value and the preceding integral chip value. 25. The method of decoding data represented in the visible part of a video signal according to claim 24, wherein the correlation is increased by a greater amount. 26. A method of decoding data represented in a visible portion of a video signal, the video signal being arranged for each of a plurality of data symbols into line pairs having a normal form and an inverted form, respectively. , A corresponding chip pattern having a plurality of lines each having a plurality of chips superimposed on the video signal, the method comprising: (a) each line pair in a line representing the chip pattern corresponding to a single data symbol. Deriving a value based on the chip at each position in, and (b) the value derived for a single data symbol in step (a) corresponding to each one of the plurality of data symbols. Correlating with a chip pattern, and (c) a chip pattern having the highest correlation with the data symbol. Identifying the data symbols represented in the visible portion of the video signal according to claim 1. 27. In the step (b), (b1) when the corresponding chip in the pattern has the first polarity, the value stored in each correlation accumulator for each of the chip patterns is calculated as an integrated chip value. And (b2) if the corresponding chip in the pattern has the second polarity, for each of the chip patterns, the value stored in each correlation accumulator is reduced by the integrated chip value. 27. A method of decoding data represented in the visible portion of a video signal according to claim 26, including: 28. The difference function does not exceed a second threshold level and the correlated chip pattern is inverse at a position corresponding to any integrated chip value and a preceding integrated chip value above the first threshold level. The arbitrary integral tip value is not directly used for the correlation in step (b), but instead is used as part of a difference function with the previous integral tip value. 26. A method for decoding data represented in the visible part of a video signal according to claim 26. 29. Any integral tip value that does not exceed the first threshold level is:
If the arbitrary integrated chip value and the previous integrated chip value have polarities that both match the polarities of the two chips in the correlated chip pattern, then the extra amount for the correlated chip pattern. 29. A method of decoding data represented in the visible part of a video signal according to claim 28, which increases the correlation. 30. Any integral chip value that increases correlation by an extra amount for a correlated chip pattern has a different polarity for said correlated chip pattern than said integrated chip value and the preceding integrated chip value. 30. A method for decoding data represented in the visible part of a video signal according to claim 29, wherein the correlation is increased by a greater amount. 31. A method of encoding data in the visible portion of a transmitted video signal without degrading the display of the received video signal and decoding the data in the received video signal, the method comprising the steps of: (a) transmitting. Selecting an associated one of a number of longer predetermined chip sequences for a data bit group to be done, (b) dividing the selected chip sequence into a plurality of chip lines, (c) ) Before transmission, pairing each chip line and its inversion into each line scan pair of the video signal, and (d) performing an operation on the received line scan pair and representing the chip Detecting a line, and (e) correlating each of the several chip sequences with the detected chip line and determining a correlation amount thereof. Method comprising the steps of: leaving, and selecting as a chip sequence transmitted chip sequence with the largest correlation amount (f). 32. In step (c), the two possible chip values are:
32. The method of claim 31, wherein the characteristics of the video signal are changed in opposite directions. 33. In step (d), one of each of the line scan pairs operated to reduce the effect of the video signal on the detected chip line and to increase the amplitude of the detected chip line. 33. The method of claim 32, wherein the line scan is subtracted from the other line scan in the same pair. 34. Each line scan is computed in step (d) by deriving an integral function for each chip, each chip function for one line scan corresponding to a pair of line scans. 33. The method of claim 32, wherein the method is subtracted from the chip function for the co-located chips. 35. Prior to transmission, embedding a sync tip pattern in several line scans of the video signal, and performing an operation on the received video signal to confirm the tip position for detection in step (d). 35. Performing and determining the position of the sync tip pattern. 36. In step (d), one of each line scan pair operated on to reduce the effect of the video signal on the detected chip line and to increase the amplitude of the detected chip line. 32. The method of claim 31, wherein the line scan is subtracted from the other line scan in the same pair. 37. Each line scan is computed in step (d) by deriving an integral function for each chip, each chip function for one line scan corresponding to a pair of line scans. 32. The method of claim 31, wherein the method is subtracted from a chip function for co-located chips. 38. Prior to transmission, embedding a sync tip pattern in some line scans of the video signal, and performing an operation on the received video signal to confirm the tip position for detection in step (d). The method of claim 31, further comprising: performing and determining the position of the sync tip pattern.