JP2003500745A5 - - Google Patents
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- Publication number
- JP2003500745A5 JP2003500745A5 JP2000620508A JP2000620508A JP2003500745A5 JP 2003500745 A5 JP2003500745 A5 JP 2003500745A5 JP 2000620508 A JP2000620508 A JP 2000620508A JP 2000620508 A JP2000620508 A JP 2000620508A JP 2003500745 A5 JP2003500745 A5 JP 2003500745A5
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- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Applications Claiming Priority (15)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13590299P | 1999-05-26 | 1999-05-26 | |
| US13612699P | 1999-05-26 | 1999-05-26 | |
| US13612799P | 1999-05-26 | 1999-05-26 | |
| US60/136,127 | 1999-05-26 | ||
| US60/135,902 | 1999-05-26 | ||
| US60/136,126 | 1999-05-26 | ||
| US09/574,693 | 2000-05-17 | ||
| US09/574,693 US6470486B1 (en) | 1999-05-26 | 2000-05-17 | Method for delay-optimizing technology mapping of digital logic |
| US09/574,572 US6516453B1 (en) | 1999-05-26 | 2000-05-17 | Method for timing analysis during automatic scheduling of operations in the high-level synthesis of digital systems |
| US09/574,572 | 2000-05-17 | ||
| US57742600A | 2000-05-22 | 2000-05-22 | |
| US09/577,426 | 2000-05-22 | ||
| US09/579,825 US6782511B1 (en) | 1999-05-26 | 2000-05-25 | Behavioral-synthesis electronic design automation tool business-to-business application service provider |
| US09/579,825 | 2000-05-25 | ||
| PCT/US2000/014617 WO2000072185A2 (en) | 1999-05-26 | 2000-05-26 | Behavioral-synthesis electronic design automation tool and business-to-business application service provider |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2003500745A JP2003500745A (ja) | 2003-01-07 |
| JP2003500745A5 true JP2003500745A5 (ja) | 2007-07-05 |
| JP4495865B2 JP4495865B2 (ja) | 2010-07-07 |
Family
ID=27568902
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000620508A Expired - Fee Related JP4495865B2 (ja) | 1999-05-26 | 2000-05-26 | 業者間アプリケーションサービスプロバイダ |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP1248989A2 (ja) |
| JP (1) | JP4495865B2 (ja) |
| CN (1) | CN1408092A (ja) |
| AU (1) | AU5167100A (ja) |
| WO (1) | WO2000072185A2 (ja) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6961773B2 (en) | 2001-01-19 | 2005-11-01 | Esoft, Inc. | System and method for managing application service providers |
| EP1582960B1 (en) * | 2001-02-16 | 2007-07-18 | United Parcel Service Of America, Inc. | Systems for selectively enabling and disabling access to software applications over a network and method for using same |
| AU2002245463A1 (en) * | 2001-02-16 | 2002-09-04 | United Parcel Service Of America, Inc. | System and method for selectively enabling and disabling access to software applications over a network |
| US7734715B2 (en) * | 2001-03-01 | 2010-06-08 | Ricoh Company, Ltd. | System, computer program product and method for managing documents |
| JP2003067453A (ja) * | 2001-08-27 | 2003-03-07 | Nec Corp | 設計を促進する方法 |
| US20160162625A1 (en) | 2013-09-26 | 2016-06-09 | Synopsys, Inc. | Mapping Intermediate Material Properties To Target Properties To Screen Materials |
| US9836563B2 (en) | 2013-09-26 | 2017-12-05 | Synopsys, Inc. | Iterative simulation with DFT and non-DFT |
| US10516725B2 (en) | 2013-09-26 | 2019-12-24 | Synopsys, Inc. | Characterizing target material properties based on properties of similar materials |
| US10402520B2 (en) | 2013-09-26 | 2019-09-03 | Synopsys, Inc. | First principles design automation tool |
| WO2015048400A1 (en) | 2013-09-26 | 2015-04-02 | Synopsys, Inc. | Estimation of effective channel length for finfets and nano-wires |
| US10489212B2 (en) | 2013-09-26 | 2019-11-26 | Synopsys, Inc. | Adaptive parallelization for multi-scale simulation |
| US10078735B2 (en) | 2015-10-30 | 2018-09-18 | Synopsys, Inc. | Atomic structure optimization |
| US10734097B2 (en) | 2015-10-30 | 2020-08-04 | Synopsys, Inc. | Atomic structure optimization |
| CN112199918B (zh) * | 2020-10-20 | 2021-09-21 | 芯和半导体科技(上海)有限公司 | 一种通用eda模型版图物理连接关系的重建方法 |
| CN113158599B (zh) * | 2021-04-14 | 2023-07-18 | 广州放芯科技有限公司 | 基于量子信息学的芯片和芯片化eda装置 |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62202268A (ja) * | 1986-02-28 | 1987-09-05 | Nec Corp | 回路処理装置 |
| JPS6376065A (ja) * | 1986-09-19 | 1988-04-06 | Nec Corp | グラフ構造デ−タ表示方式 |
| US5557531A (en) * | 1990-04-06 | 1996-09-17 | Lsi Logic Corporation | Method and system for creating and validating low level structural description of electronic design from higher level, behavior-oriented description, including estimating power dissipation of physical implementation |
| US5787010A (en) * | 1992-04-02 | 1998-07-28 | Schaefer; Thomas J. | Enhanced dynamic programming method for technology mapping of combinational logic circuits |
| US5544071A (en) * | 1993-12-29 | 1996-08-06 | Intel Corporation | Critical path prediction for design of circuits |
| JPH08101861A (ja) * | 1994-09-30 | 1996-04-16 | Toshiba Corp | 論理回路合成装置 |
| US5535145A (en) * | 1995-02-03 | 1996-07-09 | International Business Machines Corporation | Delay model abstraction |
| JP2856141B2 (ja) * | 1996-04-01 | 1999-02-10 | 日本電気株式会社 | 遅延情報処理方法及び遅延情報処理装置 |
| GB2325996B (en) * | 1997-06-04 | 2002-06-05 | Lsi Logic Corp | Distributed computer aided design system and method |
| JPH11282884A (ja) * | 1998-03-30 | 1999-10-15 | Mitsubishi Electric Corp | ネットワーク型ｃａｄシステム |
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2000
- 2000-05-26 WO PCT/US2000/014617 patent/WO2000072185A2/en not_active Application Discontinuation
- 2000-05-26 JP JP2000620508A patent/JP4495865B2/ja not_active Expired - Fee Related
- 2000-05-26 CN CN00810690A patent/CN1408092A/zh active Pending
- 2000-05-26 EP EP00936347A patent/EP1248989A2/en not_active Withdrawn
- 2000-05-26 AU AU51671/00A patent/AU5167100A/en not_active Abandoned