JP2003348368A - Image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image display device in which increase of costs is suppressed by eliminating increase in an unwanted current or voltage even when expanding an image to be displayed on a CRT. <P>SOLUTION: The image display device is provided with; a comparator 12 for outputting a signal to be a high level when a voltage generated on one terminal (point B) of a deflection yoke 2 becomes higher than a threshold determined by a reference voltage (e) and the ratio of resistors R1 and R2; and a blanking period control pulse generator 13 for generating a blanking period control pulse in accordance with a signal level outputted from the comparator 12 and a horizontal synchronization signal. The blanking period control pulse generator 13 controls ON/OFF of a transistor Q2 according to the blanking period control pulse and controls the width of the blanking period control pulse to be widened as the signal level outputted from the comparator 12 becomes higher. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cathode ray tube (CR)
The present invention relates to an image display device having T), and more particularly to an improvement in a horizontal deflection circuit of the image display device.

[0002]

2. Description of the Related Art FIG. 6 is a circuit diagram showing a configuration of a conventional general horizontal deflection circuit. The horizontal deflection circuit includes a horizontal drive circuit 101 for generating a horizontal drive signal, a deflection yoke 102, a flyback transformer 103, a variable power supply circuit 104, and a horizontal output transistor Q101.
, Resonance capacitor C101, and S-shaped correction capacitor C
102 and a damper diode D101.
In this horizontal deflection circuit, the image displayed on the CRT is enlarged by increasing the output voltage E of the variable power supply circuit 104.

[0003]

Since the aspect ratio of a CRT has recently increased to 16: 9, an aspect ratio of 16: 9 has been used in a business monitor for checking images.
It is required that the image of the image 9 be side-cut and displayed as an image having an aspect ratio of 4: 3 over the entire screen of the CRT.

Therefore, in order to increase the image size, the output voltage E of the variable power supply circuit 104 is increased, and
The overscan is 0% or more, and the deflection current ID flowing through the deflection yoke 102 increases in proportion to the output voltage E. For this reason, it is necessary to use a deflection yoke having a large rated current value. Further, since the collector voltage of the horizontal output transistor Q101 also increases in proportion to the power supply voltage E, it is necessary to use a transistor Q101 having a large withstand voltage. As a result, there is a problem that component costs increase.

The present invention has been made by paying attention to this point, and an image display apparatus capable of suppressing an unnecessary increase in current or voltage and suppressing a cost increase even when an image displayed on a CRT is enlarged. The purpose is to provide.

[0006]

According to a first aspect of the present invention, there is provided an image display apparatus having a cathode ray tube, wherein the image display device has a cathode ray tube according to a size of an image to be displayed on the cathode ray tube. Control means for controlling a power supply voltage applied to the deflection yoke, comparison means for outputting a comparison signal when a voltage generated at one end of the deflection yoke is higher than a reference voltage, a comparison signal output from the comparison means, A retrace time control pulse generating means for generating a retrace time control pulse in response to the horizontal synchronization signal; a switch means which is on / off controlled by the retrace time control pulse and one end of which is connected to ground; End, and a capacitor connected between one end of the deflection yoke, and the retrace time control pulse generating means, as the level of the comparison signal increases, Characterized by increasing the width of the line time control pulses.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a circuit diagram showing a configuration of a horizontal deflection circuit of an image display device according to a first embodiment of the present invention. The horizontal deflection circuit includes a horizontal drive circuit 1 for generating a horizontal drive signal, a deflection yoke 2 for generating a magnetic field for deflecting an electron beam, and a flyback for outputting a pulse for generating a high voltage to be supplied to an anode of a CRT. A transformer 3, a size control microcomputer (hereinafter referred to as "size control microcomputer") 5 for controlling the size of an image displayed on the screen of the CRT, a variable power supply 4 whose output voltage is controlled by the size control microcomputer 5, and a horizontal output transistor Q1, a resonance capacitance switching transistor Q2, Q3 that is turned on and off by the size control microcomputer 5 and switches the resonance capacitance, a resonance capacitor C1, a damper diode D1, an S-shaped correction capacitor C2, and control resonance capacitors C3, C4. It has.

When the horizontal output transistor Q1 is turned off, a half-sinusoidal pulse is generated at the collector of the transistor Q1. When the transistors Q2 and Q3 are off, the pulse width T is equal to the resonance capacitor C1.
The width is determined by When only the transistor Q2 turns on, the pulse width T increases, and when the transistor Q3 also turns on, the pulse width T further increases.

When the user instructs to enlarge the image size, the size control microcomputer 5 increases the output voltage Vcc of the variable power supply 4 according to the enlargement ratio,
A signal for turning on only the transistor Q2 or the transistors Q2 and Q3 is output. When the output voltage Vcc of the variable power supply 4 is a normal voltage, the relationship between the deflection current ID and the screen size is as shown by a straight line L1 in FIG. Output voltage Vcc of variable power supply 4 to enlarge the image
Is increased, as shown by a straight line L2 in FIG.
An unnecessary current corresponding to a range exceeding the RT size flows.

Therefore, in the present embodiment, in response to the increase in the power supply voltage Vcc, the transistor Q2
Only, or by turning on the transistors Q2 and Q3, the resonance frequency is lowered and the retrace time is lengthened. FIG. 3 shows an example in which the image size is enlarged by 30%, and the capacitances of the capacitors C2 and C3 are set so that the raster is turned over when the raster exceeds the CRT size by extending the retrace time. .

In this embodiment, when an instruction to enlarge the image size is issued, the output voltage Vcc of the variable power supply 4 is increased according to the enlargement ratio, and only the transistor Q2 or the transistors Q2 and Q3 are turned on. ,
Since the flyback time is extended, unnecessary current does not flow. Therefore, it is not necessary to use a component having a large maximum rating, and it is possible to suppress an increase in cost.

(Second Embodiment) FIG. 4 is a circuit diagram showing a configuration of a horizontal deflection circuit according to a second embodiment of the present invention. This circuit includes a horizontal drive circuit 1, a deflection yoke 2, and a flyback transformer 3 as in the first embodiment.
A variable power supply 4, a size control microcomputer 5, a horizontal output transistor Q1, a resonance capacitance switching transistor Q2 for switching resonance capacitance, a resonance capacitor C1, a damper diode D1, an S-shaped correction capacitor C2, and a control resonance. And a capacitor C3.
, A capacitor C5, a reference power supply 11 for outputting a reference voltage e, a comparator 12, and a retrace time control pulse generator 13
And

The voltage Vp-p at the point B to which the collector of the horizontal output transistor Q1 is connected is divided by the resistors R1 and R2 and input to the non-inverting input of the comparator 12. The output of the comparator 12 is high when the input voltage of the non-inverting input is higher than the reference voltage e, and is low when the input voltage of the non-inverting input is lower than the reference voltage e.

The retrace time control pulse generator 13 generates a retrace time control pulse in accordance with the horizontal synchronizing signal and the output signal of the comparator 12, and supplies the pulse to the base of the transistor Q2. FIG. 5A shows a voltage waveform when the horizontal output transistor Q1 is turned off, and FIG. 5B shows a retrace time control pulse waveform. In FIG. 3A, a solid line shows a waveform when the transistor Q2 is turned off, and a broken line shows a waveform when the transistor Q3 is turned on.

The voltage Vp-p at the point B in FIG.
Is represented by Vp-p = (π / 2) × Vcc × (Ts / Tr) (1) Here, Ts is a scanning time, Tr is a retrace time, and Vcc is a power supply voltage. From the expression (1), the following expression (2) is obtained, and it is understood that the flyback time Tr can be controlled by changing the voltage Vp-p at the point B. Tr = (Vcc × Th × π) / (2Vp-p + πVcc) (2) Here, Th is the entire horizontal period (Ts + Tr).

In the present embodiment, attention is paid to the relationship of equation (2), and the retrace time Tr is controlled as described below.
As shown in FIG. 5B, the retrace time control pulse at point A is a pulse that goes high during the period in which the horizontal output transistor Q1 is turned off, and its width TA is determined by the comparator 1
2 is set to be higher when the output is high level than when the output is low level. Therefore, when the voltage Vp-p at the point B increases, the width TA of the retrace time control pulse increases, and the time during which the transistor Q2 is on increases,
It acts to lower the B point voltage Vp-p. As a result, the width TA of the retrace time control pulse is controlled so that the point B voltage Vp-p becomes constant, and the retrace time becomes longer as the pulse width TA increases.

The size control microcomputer 5 increases the power supply voltage Vcc according to the user's instruction in accordance with the magnification of the image, and the transistor Q2 is turned on in response to the B point voltage Vp-p by the retrace time control pulse. Time is controlled. When the power supply voltage Vcc increases, the B point voltage Vp-p also increases, so that the retrace time is controlled to an optimal value according to the power supply voltage Vcc.

As described above, in the present embodiment, a signal which becomes a high level when the voltage generated at one end (point B) of the deflection yoke 2 becomes higher than the threshold which can be determined by the ratio between the reference voltage e and the resistors R1 and R2. A comparator 12 for outputting the signal;
And a retrace time control pulse generator 13 for generating a retrace time control pulse in accordance with the signal level and the horizontal synchronizing signal output from the control circuit. The transistor Q2 is controlled to be turned on and off by the retrace time control pulse. The width of the retrace time control pulse is controlled to increase as the signal level output from the comparator 12 increases. Therefore, when the power supply voltage Vcc increases, the width of the retrace time control pulse increases, and the retrace time is controlled so as to be an optimum value according to the power supply voltage Vcc. As a result, unnecessary current is prevented from flowing, and it is not necessary to use a component having a large maximum rating, thereby suppressing an increase in cost.

[0019]

As described above in detail, according to the present invention, control means for controlling a power supply voltage applied to a deflection yoke of a cathode ray tube according to the size of an image displayed on the cathode ray tube;
Comparing means for outputting a comparison signal when a voltage generated at one end of the deflection yoke is higher than a reference voltage; and a feedback means for generating a retrace time control pulse according to the comparison signal and the horizontal synchronization signal output from the comparison means. Line time control pulse generating means, on / off controlled by the retrace time control pulse,
An image display device is provided, comprising: switch means having one end connected to ground; and a capacitor connected between the other end of the switch means and one end of the deflection yoke. The means is controlled to increase the width of the retrace time control pulse as the level of the comparison signal increases. Therefore, as the power supply voltage increases, the level of the comparison signal output from the comparison means increases, and the retrace time control pulse width increases. as a result,
The time during which the switch means is turned on becomes longer, and acts to reduce the half sinusoidal voltage generated at one end of the deflection yoke. That is, to enlarge the image size,
When the power supply voltage is increased, the width of the retrace time control pulse is increased, and the retrace time is controlled so as to be an optimum value according to the power supply voltage. As a result, unnecessary current is prevented from flowing, and it is not necessary to use a component having a large maximum rating, thereby suppressing an increase in cost.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a horizontal deflection circuit of an image display device according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a relationship between an image size and a deflection current.

FIG. 3 is a diagram illustrating an example in which an image size is enlarged and displayed.

FIG. 4 is a circuit diagram showing a configuration of a horizontal deflection circuit of an image display device according to a second embodiment of the present invention.

FIG. 5 is a diagram for explaining the operation of the circuit shown in FIG. 4;

FIG. 6 is a diagram showing a configuration of a conventional horizontal deflection circuit.

[Explanation of symbols]

Reference Signs List 1 horizontal drive circuit 2 deflection yoke 4 variable power supply 5 size control microcomputer (control means) 12 comparator (comparison means) 13 retrace time control pulse generator (retrace time control pulse generation means) Q1 horizontal output transistor Q2 resonance capacity Switching transistor (switch means) C1 Resonance capacitor C3 Control resonance capacitor

Claims (1)

[Claims] 1. An image display device having a cathode ray tube, comprising: control means for controlling a power supply voltage applied to a deflection yoke of the cathode ray tube according to a size of an image displayed on the cathode ray tube; A comparison means for outputting a comparison signal when a voltage generated at one end is higher than a reference voltage; and a retrace time control pulse for generating a retrace time control pulse according to the comparison signal and the horizontal synchronization signal output from the comparison means. Generating means, switch means which is on / off controlled by the retrace time control pulse, one end of which is connected to ground, and a capacitor which is connected between the other end of the switch means and one end of the deflection yoke. Wherein the retrace time control pulse generating means increases the width of the retrace time control pulse as the level of the comparison signal increases. apparatus.