JP2003348059A - Asynchronous data fetching device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an asynchronous data fetching device dispensing with a local oscillator and effective in performing miniaturization by fetching asynchronous data by using a synchronous system clock to be supplied. <P>SOLUTION: The number of clocks to be counted by a counter 5 and bit width are determined and stored in a frequency table 6 by preliminarily associating the number of clocks with the bit width. Logical value outputs of F/F2 and F/F3 holding received data on the basis of the synchronous system clock are compared with each other by a comparator 4 and an identical logical continuation frequency monitoring part 7 detects the bit width from the counted value outputted by the counter 5 by referring to the frequency table 6 at a timing when the logical outputs are mismatched. The counter 5 is reset when the logical outputs are mismatched and counts the synchronous system clock again. A data fetching part 30 successively fetches pieces of data by fetching logical values to be outputted by F/F3 by the bit width by a bit width detection signal. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous data capturing device, and more particularly to a technology for capturing asynchronous data using only a clock supplied from a synchronous system without a local oscillator.

[0002]

2. Description of the Related Art Data transferred by asynchronous communication may be transferred via a synchronous network. In this case, the data transmitted based on the asynchronous system clock is transferred while being mounted on the synchronous system clock. In the process, an operation of once taking in the data of the asynchronous communication is performed.

FIG. 4 is a diagram showing an example of a system configuration when data by asynchronous communication is transferred via a synchronous network. In this example, the asynchronous / synchronous IF unit 100 accommodates a plurality of asynchronous serial communications, fetches asynchronous data, replaces data with a synchronous clock, and
Pass to 00. The multiplexing section 200 performs data transfer as a multiplexed signal obtained by time division multiplexing. At this time, the synchronous system clock to be replaced by the asynchronous / synchronous IF unit 100 is supplied from the multiplexing unit 200. Here, a case where RS232C is used for asynchronous communication will be described as an example.

The asynchronous / synchronous IF section 100 includes a local oscillator 101 for generating an operation clock, a CPU 102 for performing arithmetic processing based on the operation clock, and dividing the operation clock for each communication speed of asynchronous communication. 1 / n frequency divider 103 for generating a communication speed clock, and ROM 104 and RAM 1 controlled by CPU 102
05 is provided. The asynchronous / synchronous IF unit 100 captures data of asynchronous communication by performing software processing in such a configuration,
Data was transferred to the synchronous clock.

Next, the above-mentioned asynchronous / synchronous IF section 100
Is shown in a functional block diagram, and the processing operation will be described. FIG. 5 is a functional block diagram showing a configuration example of a conventional asynchronous / synchronous IF unit. As shown in FIG.
The configuration of the unit can be broadly divided into an asynchronous data capturing device for capturing the received asynchronous data and a data converter for converting the captured data into synchronous data. Here, the input and output signals are assumed as follows. The communication speed of the received data by the asynchronous communication is 1200 bps. The operation clock generated by the local oscillator is 2 MHz.
It is assumed that a communication speed clock of 1200 Hz is generated by dividing this frequency. The synchronous clock supplied from outside is 64 kHz. The output from the asynchronous data acquisition device is assumed to be data obtained by replacing asynchronous communication data with a synchronous clock of 64 kHz. The asynchronous / synchronous IF unit shown in this example is a start bit detection unit that detects a start bit (ST) in the RS232C format by sampling (extracting information) reception data of asynchronous communication at regular time intervals using an operation clock. 10, a phase conversion unit 20 that adjusts the phase of the communication speed clock based on the detection timing of the start bit detection unit 10 so that the phase is located in the middle of each bit in the received data. The data capturing unit 30 that captures the received data from the start bit detecting unit 10 based on the communication speed clock and the parameter table 50 that previously stores setting parameters related to the asynchronous communication are referred to. Conditions for checking and confirming the parameter conditions set for the captured data A verification unit 40, the verification confirmation of the result collation O
And a synchronous output section 60 for sequentially outputting data fetched based on the synchronous clock when passing by K.

FIG. 6 is a diagram showing an example of setting parameters stored in the parameter table 50. In this example, the communication speed, data bit length, parity, and stop bit have setting items of RS232C. Here, the communication speed is 1200 bps, the data bit length is 8 bits,
It is assumed that the parity is set to an odd number and the stop bit is set to 1 bit. Therefore, the above-described condition matching unit 40
Performs a parity check and the like based on this setting parameter.

Next, the operation of the above asynchronous data acquisition device will be described with reference to a timing chart. FIG. 7 is a timing chart showing the operation of the conventional asynchronous data acquisition device, where FIG. 7A shows received data, and FIG.
Indicates an operation clock, (c) indicates a communication speed clock whose phase has been converted, and (d) indicates data captured by the data capturing unit. That is, the start bit detection unit 10
The received data (a) arriving at a communication speed of 00 bps is
Sampling is performed sequentially at each timing of the operation clock (b) of 2 MHz to confirm the logical value, and the start bit (S
The bit position of T) is detected. When the start bit is detected, the phase converter 20 shifts and shifts the phase of the communication speed clock of 1200 Hz based on the detection timing, and shifts the phase of the bit of the received data (a) by 1/1.
The timing is shifted to the timing at which the phase of two bits is shifted, that is, approximately at the center of each bit. Then, the data fetching unit 30 fetches data as shown in (d) by sequentially fetching each bit of the received data (a) at the timing of the phase-converted communication speed clock (c).

The data fetched by the data fetching unit 30 checks whether or not the next condition checking unit 40 satisfies parameter conditions set in the parameter table 50 in advance. After the condition matching, the data satisfying the parameter conditions is subjected to clock replacement based on the 64 kHz synchronous system clock by the synchronous system output unit 60.
It is output as synchronized serial communication data.

[0009]

However, the above-mentioned conventional asynchronous data capturing apparatus has the following problems. In other words, since multiple clocks such as an operation clock and a communication speed clock are used,
Circuits such as a local oscillator and a frequency divider for generating this are required. Therefore, there has been a problem that the configuration is complicated and miniaturization is difficult.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and it is effective to reduce the size of a local oscillator by eliminating asynchronous data by using a synchronous system clock supplied from the outside. An object is to provide an asynchronous data capture device.

[0011]

According to a first aspect of the present invention, there is provided an asynchronous data capturing apparatus, comprising: a first flip-flop for temporarily storing received data based on a synchronous clock; A second flip-flop that temporarily holds data held by the first flip-flop based on a synchronous clock, and a comparator that compares an output of the first flip-flop with an output of the second flip-flop. A counter that counts the synchronous clock and is reset by a non-coincidence output of the comparator; a count table pre-stored in which a bit width of received data is associated with a count value of the synchronous clock; The same logic continuation number monitoring unit that detects the bit width by comparing the count value of the counter with the number table when the mismatch is output, The logic 2 flip-flops for holding, characterized in that the same logical continuation count monitoring unit and a data acquisition unit for capturing the data assigned to the bit width detected.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on illustrated embodiments. FIG. 1 is a functional block diagram showing an embodiment in which the asynchronous data acquisition device according to the present invention is applied to an asynchronous / synchronous IF unit. Note that the same reference numerals are given to the same functional blocks as those shown in FIG. 5 described above, and description thereof will be omitted. Also, conditions such as setting parameters are the same as in the conventional example.

The asynchronous data capturing apparatus shown in this example has a data receiving section 1 which receives received data and a synchronous clock supplied from the outside, a receiving data output from the data receiving section 1 and a bit width detection signal. And a data capturing unit 30 which receives the data as input. In the subsequent stage, a condition matching unit 40 for checking whether or not the data acquired by the data acquiring unit 30 satisfies the conditions of the setting parameters stored in the parameter table 50 in advance, and the condition matching unit 40 There is provided a data converter having a synchronous output section 60 for sequentially outputting the passed data on a synchronous clock.

The configuration of the data receiving section 1 will be described in more detail. The data receiving unit 1 includes a first flip-flop (hereinafter, referred to as a first F / F) that holds a logical value of received data at a timing based on a synchronous clock supplied from the outside.
F) 2, a second flip-flop (hereinafter abbreviated as a second F / F) 3 for holding a logical value held by the first F / F 2 at a timing based on a synchronous clock, and a first flip-flop 3.
A comparator 4 for comparing the logical value output held by the F / F2 and the second F / F3, a counter 5 for counting the number of synchronous system clocks and resetting when the output from the comparator 4 does not match; The number of clocks (number of times) counted by the counter 5 and the bit width are preliminarily associated with each other on the premise of the known speed of the synchronous clock and the communication speed of the received data. The count value output from the counter 5 at the timing when the output of the counter 5 becomes inconsistent with the same logic continuation count monitoring unit 7 that detects the bit width by referring to the count table 6.

The table stored in the frequency table 6 will be described with reference to an example. FIG. 2 is a diagram showing an example of the number-of-times table.
z, the communication speed of the received data is 1200 bps. Then, the number of times the 64 kHz synchronous clock is input per bit when the communication speed is 1200 bps is determined and stored. That is, 64k / 1200
Since it is $ 53.33, it is set in consideration of ± 1 clock as an error range. Thus, 53 ± 1 times is determined as the number of clocks per bit. Since the bit width is constant, it is determined that the width is 2 bits for 2 × 53 ± 1 times and 3 bits for 3 × 53 ± 1 times. Also, it is considered that the error range is increased as the bit width increases.

FIG. 3 is a timing chart showing an example of each signal of the asynchronous data acquisition device according to the present invention.
5A shows received data, FIG. 5B shows a synchronous clock, FIG. 5C shows an image in which bits are established by the output of the data receiving unit, and FIG. Indicates the acquired data. The operation of the asynchronous data acquisition device according to the present invention will be described with reference to the timing chart. That is, the logical value in the time difference of one clock of the synchronous clock is sequentially shifted to the first F / F2 and the second F / F3, and the comparator 4 compares the outputs of the first F / F2 and the second F / F3. The timing at which the logical value has changed is detected. In the received data (a), the first logical value change occurs at the head of the start bit (ST).
Counter 5 is reset by the mismatch output of
The counting of the synchronous clock is started. Here, assuming that the logical value of the first bit of the eight-bit data is a logical value inverted from the start bit, the output of the comparator 4 becomes inconsistent again at the head of the first bit. At the timing of the disagreement, the same logic continuation number monitoring unit 7 compares the number of clocks counted by the counter 5 with the number table 6. Since the start bit is 1 bit wide, the counter 5
Should be within the range of 53 ± 1. Therefore, the same logic continuation number monitoring unit 7
Outputs a bit width detection signal indicating that the width is one bit.
The data fetching unit 30 fetches the logical value held by the second F / F3 as a 1-bit width based on the bit width detection signal.

Next, for example, when the first bit and the second bit of the data are the same logical value and the logical value is inverted to the third bit, the counter 5 counts from the head of the first bit. The number of system clocks is counted continuously up to the head of the third bit. The same logic continuation number monitoring unit 7
The number of clocks counted by the counter 5 is compared with the number of times table 6, and if the number is within the range of 105 to 107 times, a bit width detection signal indicating that the width is 2 bits is output.

In this manner, the data fetch unit 30 fetches from the start bit (ST) to the stop bit (SP). The acquired data is subjected to collation confirmation based on the setting parameters of the parameter table 50 in the subsequent condition collation unit 40 in the same manner as in the prior art. The output is replaced by the clock.

The asynchronous data capturing apparatus according to the present invention, configured as described above, can capture asynchronous data using only the supplied synchronous clock. Therefore, components (local oscillators and frequency dividers) for generating operation clocks and communication speed clocks that were conventionally required
Can be reduced and the size can be reduced.

[0020]

As described above, the asynchronous data capturing apparatus according to the present invention comprises: a first F / F2 (first flip-flop) for holding a logical value of received data at a timing based on a synchronous clock; The second F that holds the logical value held by the 1F / F2 at a timing based on the synchronous clock
/ F3 (second flip-flop), a comparator 4 for comparing the logical value output held by the first F / F2 and the second F / F3, and counting the number of synchronous system clocks and outputting the same by the comparator 4. Is premised on the counter 5 that is reset when the values do not coincide with each other, and the known speed of the synchronous clock and the communication speed of the received data. The same logic continuation count monitoring that detects the bit width by referring to the count table 6 and the count value output by the counter 5 at the timing when the output from the comparator 4 does not match the determined count table 6 And a data receiving unit 1 having a unit 7 and a function of reading asynchronous data by using a supplied synchronous clock. It can be omitted and the divider, very effective asynchronous data capture device miniaturization can be achieved.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an embodiment of an asynchronous data acquisition device according to the present invention.

FIG. 2 is a diagram showing an example of a count table of the asynchronous data capture device according to the present invention.

FIG. 3 is a timing chart showing each signal example of the asynchronous data acquisition device according to the present invention.

FIG. 4 is a system configuration diagram for explaining a technical background of transferring data by asynchronous communication via a synchronous network.

FIG. 5 is a functional block diagram showing a configuration example of a conventional asynchronous data capturing device.

FIG. 6 is a diagram illustrating an example of asynchronous communication setting parameters stored in a parameter table.

FIG. 7 is a timing chart showing signal examples of a conventional asynchronous data acquisition device.

[Explanation of symbols]

1 ... data receiving unit 2 ... Flip-flop (F / F) 3 ... Flip-flop (F / F) 4 ... Comparator 5 ... Counter 6 ... Count table 7 ... Same logic continuation number monitoring unit 10 Start bit detector 20: phase converter 30 ... data acquisition unit 40 ・ ・ ・ Condition matching unit 50: Parameter table 60 Synchronous output section 100: Asynchronous / synchronous interface (IF) unit 101 ... local oscillator 102: CPU (Central Processing Unit) 103 ... frequency divider (1 / n) 104 ・ ・ ・ ROM (Read Only Memory) 105: RAM (Random Access Memory) 106 ・ ・ ・ Peripheral circuit

Claims (1)

[Claims] A first flip-flop for temporarily holding received data based on a synchronous system clock; a second flip-flop for temporarily holding data held by the first flip-flop based on a synchronous system clock; A comparator for comparing the output of the first flip-flop with the output of the second flip-flop; a counter for counting the synchronous clock and resetting with a mismatch output of the comparator;
A count table in which a bit width of the received data and a count value of the synchronous clock are stored in advance, and a bit count is set by comparing the count value of the counter with the count table when the comparator outputs a mismatch. A detecting unit for detecting the same logic continuation count, and a data fetching unit for fetching data by allocating the logic held by the second flip-flop to the bit width detected by the same logic continuation monitoring unit. Asynchronous data capture device.