JP2003347929A - Data transmission control apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transmission control apparatus for allowing an FPGA (Field Programmable Gate Array) to reliably receive program data in programming the FPGA and reducing the time required for the programming. <P>SOLUTION: The data transmission control apparatus is configured such that the apparatus compares two consecutive data or more, decreases a data transmission interval when they are matched and extends the data transmission interval when mismatched. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a program for a programmable integrated device, and more particularly to a data transmission control device for reducing programming execution time.

[0002]

2. Description of the Related Art In recent years, programmable integrated devices (FPGAs (Field Programmable Devices)) have been developed.
(Gate / Array)), there is a problem that the programming execution time becomes long and the startup time of the device using the FPGA becomes long. That is, in the realization of an FPGA that uses a static random access memory (SRAM) for holding the configuration information (program data) of the FPGA, when the system is started or initialized, the FPGA is programmed from an external source. The data is read into the SRAM, but as the number of programmable elements in the FPGA increases, the FPGA
Has also increased in the amount of programming data required to construct the. Therefore, in the FPGA using the SRAM, a long transfer time of the program data is required every time the FPGA is started and initialized.

As a method for solving the problem that the programming execution time of the FPGA is long, Japanese Patent Application Laid-Open No.
Japanese Patent Application Publication No. 153789 discloses a technique for reducing the transfer time.

FIG. 10 is a block diagram showing a conventional method for shortening a programming execution time.
The PGA 54 includes a programming control circuit 52, a compressed data decompression circuit 53, and a logic cell array 55 including a plurality of programmable logic cells 56 interconnected horizontally and vertically.

[0005] The program data storage ROM 50 includes:
Data in which the program data for programming the FPGA 54 is compressed to reduce the data size is stored. Here, the program data transmission circuit 51 reads the compressed data stored in the program data storage ROM and sends the compressed data to the programming control circuit 52 of the FPGA 54. Subsequently, the programming control circuit 5
2 sends the read compressed data to the compressed data decompression circuit 53. Upon receiving the compressed data, the compressed data decompression circuit 53 decompresses the compressed data to return to the data before compression, and then sends it to the programming control circuit 52. Then, the decompressed program data is sent to each logic cell 56 in the FPGA 54, and the FPG
Each logic cell 56 of the logic cell array 55 constituting A54
Used to program In this manner, the data to be stored in the program data storage ROM is compressed to reduce the data size, thereby shortening the time for sending to the FPGA 54, thereby shortening the programming execution time.

[0006]

However, in order to transfer the compressed data to the FPGA 54 to shorten the programming execution time as in the prior art, it is necessary to provide the FPGA 54 with a compressed data decompression circuit 53. FPG without the compressed data release circuit 53
There was a problem that it could not be applied to A54.

The present invention has been proposed on the basis of the above-mentioned conventional circumstances, and can be applied to an FPGA having no compressed data decompression circuit 53. It is an object to provide a control device.

[0008]

The present invention employs the following means to achieve the above object. That is, as shown in FIG. 1, the present invention is based on a data transmission control device that transmits program data to a programmable integrated device. And comparing means 1 described below.
3. Transmission interval control means 12 and data transmission means 2
0 is provided.

That is, the comparing means 13 compares at least two consecutive program data. The sending interval control means 12 controls the sending interval of the program data based on the comparison result of the comparing means 13, and the data sending means 20 sends the program data according to the sending interval output by the sending interval controlling means 12.

In this way, at least two comparisons are made.
The data transmission interval is controlled depending on whether or not the pieces of data match, and the program data can be reliably written into the FPGA, and the programming time can be reduced.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. It should be noted that the following embodiments are examples embodying the present invention, and do not limit the technical scope of the present invention. (Embodiment 1) FIG. 1 is a schematic functional block diagram of a data transmission control device according to the present embodiment. Hereinafter, only the configuration different from the above-described conventional one will be described.

As shown in FIG. 1, a data transmission control device 1
6 reads the program data from the flash memory 21 in which the program data of the FPGA 22 is stored. That is, the read control circuit 15 constituting the data transmission control device 16 gives the address of the flash memory to the flash memory 21 and outputs the read signal 27 to the flash memory 21 so that the read signal is stored in the flash memory 21. Read the program data stored. The read program data is 8-bit parallel in the present embodiment, but the number of bits is not limited to this number, and may be, for example, 16 bits.

Next, the program data read from the flash memory 21 is loaded into the shift register circuit 20 as data transmission means by a parallel load signal 29 output from the transmission interval control means 12.

The shift register circuit 20 includes flip-flops 1 to 8 and a flip-flop 9. The number of flip-flops 1 to 8 constituting the shift register circuit is determined by the number of bits of program data read at one time. Depends on.

The flip-flop i (i = 1, 2,...)
・, 8) take in the data given to the I0 terminal when the LD terminal is “H” and output it to the Q terminal,
When the SF terminal is at "H", the data supplied to the I1 terminal is taken in and output to the Q terminal. Further, this circuit holds the output of the Q terminal when both the LD terminal and the SF terminal are at “L”.

The flip-flop 9 has an SF terminal of "H".
When the SF terminal is at "L", the circuit takes in the data given to the I terminal and outputs the data to the Q terminal, and holds the output of the Q terminal when the SF terminal is "L". The output Q9 of the flip-flop 9 becomes the serial data 32 which is the input data of the FPGA 22.

Next, the output Q8 of the flip-flop 8 and the output Q9 of the flip-flop 9 are input to the comparing means 13. The comparing means 13 is composed of an exclusive OR circuit, and is a circuit for comparing the output Q8 of the flip-flop 8 and the output Q9 of the flip-flop 9, which are inputs.
That is, when both have the same value, “L” is output,
This circuit outputs "H" when the input values are different.
Therefore, "L" is output when two consecutive bits of the program data have the same value, and "H" is output when two consecutive bits have different values.

The output of the comparison means 13 is input to the transmission interval control means 12. The transmission interval control unit 12 outputs a shift signal 30 to the shift register circuit 20 in accordance with the state of the comparison signal 23 output from the comparison unit 13.
Is input to the SF terminals of the flip-flops 1 to 8, the parallel load signal 29 is input to the LD terminals of the flip-flops 1 to 8, the read request signal 31 is input to the read control circuit 15, and the FPGA 22 outputs the serial data 32. To generate a serial clock 33 for capturing the

FIG. 2 is a schematic functional block diagram of the data transmission interval control means 12. As shown in FIG. 2, the data transmission interval control means 12 includes a transmission interval counter 37 and a counter control means 36. The sending interval counter 37 is a counter that decrements by one at the rising edge of the operation clock 35.
It has three states “0”, “1”, and “2”, and transitions between the states according to the comparison signal 23 output from the comparing means 13. In addition, the counter control means 36 controls the shift signal 30, the parallel load signal 29, the read request signal 31,
Then, a serial clock 33 is generated.

FIGS. 3 and 4 are time charts showing the operation of the data transmission control device 16 in the present embodiment. The operation of the data transmission control device 16 will be described with reference to FIGS.

The operation clock 35 shown in FIG. 3A is always continuously supplied to each element (the flip-flops 1 to 9 and the transmission interval control means 12) constituting the data transmission control device 16, and in this state, Assume that the counter control means 36 of the transmission interval control means 12 sets the read request signal 31 to "H" as shown in FIG. 3B from time T0 to time T1. The read control circuit 15 outputs the read request signal 3 at the rising edge of the operation clock 35 at time T1.
1 is changed to "H", the address signal 26 of the flash memory 21 shown in FIG. 3C is updated (FIG. 3), and the read signal 27 shown in FIG. Is set to “L” (FIG. 3).

The flash memory 21 has a read signal 27
Becomes "L", the data stored at the address indicated by the address signal 26 is output as parallel data 28. In the example shown in FIG. 3E, 6E (hexadecimal notation) is output.

On the other hand, the counter control means 36 of the transmission interval control means 12 operates in the time from time T1 to time T2 as shown in FIG.
The parallel load signal 29 shown in FIG. At this time, the flip-flop i (i = 1, 2,..., 8) constituting the shift register circuit 20 indicates that the parallel load signal 29 has become “H” at time T2.
Of the parallel data 28 (6E) recognized by the rising edge of the
H (hexadecimal)) respectively (pattern).

The counter control means 36 of the transmission interval control means 12 compares the output Q8 of the flip-flop 8 with the output Q9 of the flip-flop 9 at the rising edge of the operation clock 35 at time T2. When the comparison signal 23, which is the result of the check and comparison, is "L", that is, when the comparison results match, FIG.
As shown in (h), the transmission interval counter 37 is loaded with "1". When the counter value (counter state) of the transmission interval counter 37 is "1" or more, the counter control means 36 sets the serial clock 33 shown in FIG.
(Except for the period when the read signal 27 shown in FIG. 3D is “L”).

Thereafter, at the rising edge of the operation clock 35 at time T3, the transmission interval counter 37 is decremented as shown in FIG. 4 (h), and the counter value (counter state) becomes "0". When the counter value (state of the counter) of the transmission interval counter 37 becomes "0", the counter control means 36 performs the operation shown in FIG. 4 (i) from time T3 to time T4.
Is set to "H" (FIG. 4).

Next, when the shift signal 30 becomes "H",
At the rising edge of the operation clock 35 at time T4, the flip-flops i (i = 1, 2,..., 9) constituting the shift register circuit 20 perform the shift operation (pattern). That is, the flip-flop 1 captures “L”, and flip-flop i + 1 (i = 1, i = 1,
, 8) fetch the output signal Qi (i = 1, 2,..., 8) of the preceding flip-flop i, and the shift register circuit 20 performs a shift operation.

Next, the counter control means 37 of the transmission interval control means 12 determines the comparison signal 23 output from the comparison means 13 at the rising edge of the operation clock 35 at the time T4, and sets the comparison signal 23 to "L". ", Ie,
If the comparison results match, "1" is loaded into the transmission interval counter 37 as shown in FIG. Then, from time T4 to T5, the counter control means 36 of the transmission interval control means 12 sets the serial clock 33 to "H" as shown in FIG. 4 (j) (FIG. 4). Also, the next time T
At the rising edge of the operation clock 35 of FIG. 5, the transmission interval counter 37 is decremented, and the counter value (counter state) becomes "0". As shown, the shift signal 30 is set to “H” (FIG. 4),
The serial clock 33 is set to "L" as shown in (j) (FIG. 4). At the time when the serial clock 33 switches from “H” to “L” (rising edge of T5),
For example, the FPGA 22 reads “0” (the lower first bit of the data 6EH) of the serial data 32 shown in FIG.

At the next rising edge of the operation clock 35 at time T6, each flip-flop i (i = 1, 2,...) Constituting the shift register circuit 20 is similar to the rising edge of the operation clock 35 at time T4. , 9) perform a shift operation (pattern).

Next, the counter control means 36 of the transmission interval control means 12 determines the comparison signal 23 output from the comparison means 13 at the rising edge of the operation clock 35 at time T6, and H ”, that is, if the comparison results do not match, the transmission interval counter 3
7 is loaded with "2". This indicates that the next data to be sent to the FPGA 22 changes from “0” to “1” as shown in FIG. 4F, and from time T6 to time T8, the data shown in FIG. As shown in (1), the counter value (counter state) of the transmission interval counter 37 is "1" or more. Therefore, as shown in FIG. 4 (j), the serial clock 33 also becomes "H" during the two operation clocks (FIG.
,). Subsequently, at the rising edge of the operation clock 35 at time T8, the transmission interval counter 37 is decremented, and the counter value (counter state) becomes "0".
From time T8 to time T9, the counter control means 36 sets the shift signal 30 shown in FIG.
) And the serial clock 33 shown in FIG.
Is set to “L” (FIG. 4 (10)). At the time when the serial clock 33 switches from “H” to “L” (rising edge of T8), for example, the FPGA 22 outputs the signal shown in FIG.
Is read (the lower second bit of the data 6EH) of the serial data 32 shown in FIG.

At the next rising edge of the operation clock 35 at time T9, the flip-flops i (i = 1, 2,...) Constituting the shift register circuit 20 are similar to the rising edge of the operation clock 35 at time T6. , 9) perform a shift operation (pattern).

Thereafter, the same operation is sequentially performed in accordance with the comparison result of the comparing means 13.
When the transmission of the 8-bit serial data 32 is completed, the transmission interval control means 12 outputs a new read request signal 31. Then, the next parallel data 28 is read from the flash memory 21, and the same operation as from time T 0 is sequentially performed. This series of operations is repeated until the writing of the program data to the FPGA 22 is completed.

As described above, two consecutive pieces of program data written from the flash memory 21 to the FPGA 22 are compared, and if they match, the transmission interval of the serial data 32 is set to the operation clock 35 for two clocks. If they do not match, the transmission interval of the serial data 32 is set to three operation clocks. By changing the transmission interval in accordance with the coincidence / mismatch of two data in this way, when the FPGA receives the serial data 32 at the falling edge of the serial clock 33, the setup time is determined by the operation clock when the two data coincide. 3
In contrast, only one mismatch of the two data corresponds to two operation clocks 35. Therefore, when the comparison results match, the data transmission interval is shortened, so that the programming time to the FPGA can be shortened.

For example, when writing program data to the FPGA 22, the frequency of the operation clock 35 supplied to the data transmission control device 16 is, for example, 66 MHz.
(Period approximately 15 nanoseconds) in many cases. In this case, even if the setup time of the FPGA is about 13 nanoseconds (a setup time of about 15 nanoseconds is necessary including the delay of the circuit, etc.), if the continuous data match, the operation clock 35 is used. The program data can be written into the FPGA with the setup time of one clock, and the programming time to the FPGA can be reduced.

In the above description, an example has been described in which the program data to be written to the FPGA 22 is transmitted serially. However, the present invention can be similarly implemented by transmitting the program data in parallel. However, in this case, for example, in the case of 8-bit parallel, eight comparing means 13 are required, and the probability that the data before and after consecutive coincide will be smaller than that in the case of serial processing.

The duty ratio of the serial clock 33 is set to 2: 1 when two consecutive data are different.
In the case where the data is the same, the ratio is set to one-to-one.

Also, the example in which the transmission interval of the program data is determined by the set-up time has been described. However, other electrical characteristics, a longer hold time, or suppression of radiation noise on a printed circuit board can be used. It may be decided.

The example in which the transmission interval of the program data is adjusted by changing the number of clocks of the operation clock 35 has been described. By adjusting the frequency of the operation clock 35 by a voltage controlled oscillator such as a VCO, the transmission interval can be adjusted. Adjustment can be similarly performed.

In this embodiment, one comparing means 13 is used. However, two comparing means 13 may be provided to adjust the hold time in the same manner as the setup time. An embodiment in which two comparison means 13 are provided will be described below. (Embodiment 2) FIG. 5 is a schematic functional block diagram of a data transmission control device according to the present embodiment. Hereinafter, only the configuration different from the first embodiment will be described.

As shown in FIG. 5, the flip-flop 10 is added to the shift register circuit 17 and the comparison means 14 is added to the shift register circuit 17 as compared with the configuration of the first embodiment. As shown in FIG. 6, the transmission interval output control means 18 comprises a counter control means 38 and a transmission interval counter 39 as in the first embodiment. That is, R0, R1,
It has seven states, LD, H0, H1, L0, and L1, and the first comparison signal 23 and the second comparison signal shown in FIG. 9 which is the output of the comparison means 14 of FIG.
State transition is performed according to the output of the second comparison signal 24 shown in (i).

FIG. 7 is a state transition diagram of the transmission interval counter 39. The transmission interval counter 39 starts operating when the reset signal 40 shown in FIG. 8B becomes “H”. From state R0 to state R1, from state R1 to state L
D, from state LD to state H0, from state L0 to state L1
From the state L1 to the state H0.
Is input, the state automatically changes in synchronization with the rising edge. In addition, from the state H0 to the state H1
From state H0 to state L1, from state H0 to state L0
, The first comparison signal 23 and the second comparison signal 2 from the state H1 to the state L1 and from the state H1 to the state L0, respectively.
The transition is made according to at least one of the four values.

FIGS. 8 and 9 are time charts showing the operation of the data transmission control device 19 in the present embodiment. The operation of the data transmission control device 19 will be described with reference to FIGS.

T0 of the operation clock 35 shown in FIG.
8B, the reset signal 40 shown in FIG. 8B changes from “L” to “H”, and the data transmission control device 1
Operation 9 is started. At the time of T1 of the operation clock 35 shown in FIG. 8A, the state transition diagram shown in FIG.
0 to the state R1. In the state R1, the counter control means 38 switches the state from the time T1 to the time T2 in FIG.
The read request signal 31 is set to "H" as shown in FIG. Next, the read control circuit 15 outputs the operation clock 35 at time T2.
It recognizes that the read request signal 31 has become “H” at the rising edge of the address signal, and updates the address signal 26 of the flash memory 21 shown in FIG. 8D (FIG. 8).
Until time T4, the read signal 27 shown in FIG. Here, the state transition of the transmission interval counter 39 transits from the state R1 to the state LD.

At time T2 of the next operation clock 35, when the transmission interval counter 39 changes to the state LD, the counter control means 38 sets the parallel load signal 29 shown in FIG. (FIG. 8).

At time T3 of the next operation clock 35, the state transition diagram of the transmission interval counter 39 changes from state LD to state H0.
Transitions to. In the state H0, since the parallel load signal 29 shown in FIG. 8G is "H", the value 4E (hexadecimal) of the parallel data 28 shown in FIG.取 り 込 む Take in the flip-flop 8.

At time T4 of the next operation clock 35, the state transition diagram of the transmission interval counter 39 shows that the first comparison signal 23 shown in FIG. 9H and the second comparison signal 24 shown in FIG. Since the state is “L”, the state transits to the state L1. State L
At 1, the counter control means 38 sets the serial clock 33 shown in FIG. 9 (l) to "L" (FIG. 9), and FIG. 9 (k).
Is set to "H" (FIG. 9).

At the next time T5 of the operation clock 35, the state transition diagram of the transmission interval counter 39 changes from the state L1 to the state H0. In the state H0, the serial clock 33 shown in FIG. 9 (l) is set to “H” (FIG. 9).
Since the shift signal 30 shown in FIG. 9K is “H”,
At the rising edge of the operation clock 35 at the time T5, the flip-flop 1 captures “L”, and the flip-flop i + 1 (i = 1, 2,..., 9) outputs the output signal Qi (i = 1, 2, ..., 9)
And the shift register circuit 17 performs a shift operation.

At the next time T6 of the operation clock 35, the state transition diagram of the transmission interval counter 39 shows that the first comparison signal 23 shown in FIG. 9H is "H" and the first comparison signal 23 shown in FIG. Since the second comparison signal 24 is "L", the state transits to the state L0, and the serial clock 33 is set to "L" as shown in FIG. 9 (l) (FIG. 9). At the time when the serial clock 33 switches from “H” to “L” (rising edge of T6), for example, the FPGA 22 outputs “0” (lower first bit of the data 4EH) of the serial data 32 shown in FIG. Eye) is read.

At time T7 of the next operation clock 35, the transition state diagram of the transmission interval counter 39 transits from state L0 to state L1. In the state L1, the serial clock 33 shown in FIG. 9 (l) is set to “L” (FIG. 9), and FIG.
Is set to "H" (FIG. 9).

At time T8 of the next operation clock 35, the state transition diagram of the transmission interval counter 39 changes from state L1 to state H0. In the state H0, the serial clock 33 shown in FIG. 9 (l) is set to "H" (FIG. 9). Also, FIG.
Since the shift signal 30 shown in (k) is “H”, the flip-flop 1 captures “L” at the rising edge of the operation clock 35 at time T8, and the flip-flop i
+1 (i = 1, 2,..., 9) takes in the output signal Qi (i = 1, 2,..., 9) of the preceding flip-flop i, and the shift register circuit 17 performs a shift operation.

At the next time T9 of the operation clock 35, the state transition diagram of the transmission interval counter 39 shows that the first comparison signal 23 shown in FIG. The serial clock 33 shown in FIG. 9 (l) is set to “H” (FIG. 9 (10)).

At time T10 of the next operation clock 35,
In the state transition diagram of the transmission interval counter 39, since the first comparison signal 23 shown in FIG. 9H is "L", the state transitions from the state H1 to the state L1. In the state L1, the serial clock 33 shown in FIG. 9 (l) is set to “L” (FIG. 9 (11)),
The shift signal 30 shown in FIG. 9K is set to “H” (FIG.
(12)). Time when this serial clock 33 switches from "H" to "L" (rising edge of T10)
Then, for example, “1” of the serial data 32 (the lower second bit of the data 4EH) shown in FIG.

At time T11 of the next operation clock 35,
The state transition diagram of the transmission interval counter 39 transitions from the state L1 to the state H0. In the state L1, the serial clock 33 shown in FIG. FIG. 9 (k)
Is "H", the flip-flop 1 captures "L" at the rising edge of the time T11 of the operation clock 35, and the flip-flop i + 1
(I = 1, 2,..., 9) captures the output signal Qi (i = 1, 2,..., 9) of the preceding flip-flop i, and the shift register circuit 17 performs a shift operation.

At time T12 of the next operation clock 35,
The state transition diagram of the transmission interval counter 39 shows that the first comparison signal 23 shown in FIG. 9H is "L" and the second comparison signal 24 shown in FIG. 9I is "L". The state transits from the state H0 to the state L1. In the state L1, the serial clock shown in FIG. 9 (l) is set to “L”, and the shift signal 30 shown in FIG. 9 (k) is set to “H”. This serial clock 3
At the time when 3 changes from “H” to “L” (rising edge of T12), for example, “1” of serial data 32 (lower third bit of data 4EH) shown in FIG. Is read.

At time T13 of the next operation clock 35,
In the state transition diagram of the transmission interval counter 39, the state transits to the state L1 or the state H0. In this state H0, the serial clock 33 shown in FIG. FIG. 9 (k)
Is "H", the flip-flop 1 captures "L" at the rising edge of the operation clock 35 at time T13, and the flip-flop i + 1
(I = 1, 2,..., 9) captures the output signal Qi (i = 1, 2,..., 9) of the preceding flip-flop i, and the shift register circuit 17 performs a shift operation.

At time T14 of the next operation clock 35,
The state transition diagram of the transmission interval counter 39 is because the first comparison signal 23 shown in FIG. 9H is “H” and the second comparison signal 24 shown in FIG. 9I is “L”. The state transits from the state H0 to the state L0. In this state L0, the serial clock 33 shown in FIG. The time when this serial clock 33 switches from “H” to “L” (T
For example, “1” (the fourth lower bit of the data 4EH) of the serial data 32 shown in FIG.

At time T15 of the next operation clock 35,
The state transition diagram of the transmission counter 39 is as follows.
1, the serial clock 33 shown in FIG. 9 (l) is set to “H”, and the shift signal 30 shown in FIG. 9 (k) is set to “H”.
And

At time T16 of the next operation clock 35,
The state transition diagram of the transmission interval counter 39 changes from the L1 state to the state H0. In this state H0, the serial clock 33 shown in FIG. Also, FIG.
Since the shift signal 30 shown in (k) is “H”, the flip-flop 1 captures “L” at the rising edge of the operation clock 35 at time T16, and the flip-flop i + 1 (i = 1, 2,...) , 9) take in the output signal Qi (i = 1, 2,..., 9) of the preceding flip-flop i, and the shift register circuit 17 performs a shift operation.

At time T17 of the next operation clock 35, the state transition diagram of the transmission interval counter 39 shows that the second comparison signal 24 shown in FIG. 9 (i) is "H", so that the state transitions from state H0 to state H1. I do. In this state H1, the serial clock 33 shown in FIG.

Thereafter, similarly to the above, the transmission interval counter 3
The state transition diagram of FIG. 9 shows the first comparison signal 23 and the second comparison signal 2
4 sequentially.

Focusing on the serial clock 33 shown in FIG. 9 (l) and the serial data 32 shown in FIG. 9 (f), at time T6 of the operation clock 35, the serial clock 33 shown in FIG. From “H” to “L”,
The serial data 32 shown in FIG. 9 (f) is taken into the FPGA 22, but the currently transmitted serial data 32 is "L" and the serial data 32 to be transmitted next (FIG. 9 (e)
(The current data of Q8) is "H". That is, the data to be transmitted next changes. In this case, the period in which the serial clock 33 shown in FIG. 9L is "H" is one cycle of the operation clock, and the period in which the serial clock 33 is "L" is two cycles of the operation clock ( (Period t1 shown in FIG. 9). This means that when the program data is read into the FPGA 22, a data hold time for two cycles of the operation clock is generated.

At time T10 of the operation clock 35, the serial clock 33 shown in FIG. 9 (l) changes from "H" to "L" and the serial data 32 shown in FIG. Is the "L", and the currently transmitted serial data 32 is "H". That is, the serial data 32 transmitted previously changes to the serial data 32 currently transmitted. In this case, the period when the serial clock 33 shown in FIG. 9 (l) is "H" is two cycles of the operation clock (the period t2 shown in FIG. 9), and the period when the serial clock 33 is "L" is One cycle of the operation clock. This means that when the program data is read into the FPGA 22, a setup time for two cycles of the operation clock is generated.

As described above, by providing two comparison means 13 and 14, it is possible to monitor whether or not the serial data 32 changes continuously. If the serial data 32 changes, the serial data 32 changes to the FPGA 22 for writing the program data. Necessary setup time and hold time can be generated. Therefore, when the programming is executed, the operation clock 35
Even if is faster, the program data can be written into the FPGA while keeping the setup time and the hold time defined by the FPGA 22, and the programming of the FPGA can be shortened.

In the above description, an example has been described in which the program data to be written to the FPGA 22 is transmitted serially. However, the present invention can be similarly implemented by transmitting the program data in parallel.

The duty ratio of the serial clock 33 is set to 2: 1 when two consecutive data are different.
(Or 1: 2), when the data is the same, the data is set to 1: 1. However, other duty ratios can be similarly used.

In the above description, the transmission interval of the program data is determined by the setup time and the hold time. However, the transmission interval may be determined by other electrical characteristics, for example, by suppressing radiation noise on a printed circuit board. Good.

The example in which the transmission interval of the program data is adjusted by changing the number of clocks of the operation clock 35 has been described. However, the frequency of the operation clock 35 is adjusted by a voltage controlled oscillator such as a VCO to thereby adjust the transmission interval. Adjustment can be similarly performed.

[0067]

As described above, according to the present invention, if the data before and after successive data is different, the setup becomes longer, so that the program data can be reliably written in the FPGA, and If the data is the same, the interval at which the program data is sent becomes shorter,
There is an effect that the programming time of A is shortened.

Also, by providing two comparing means, when continuous data is different, the setup time,
In addition, since the hold time can be extended, the program data can be more reliably written into the FPGA, and if the data match, the data transmission interval becomes shorter, so that the programming time can be reduced. .

[Brief description of the drawings]

FIG. 1 is a schematic functional block diagram of a data transmission control device according to a first embodiment.

FIG. 2 is a schematic functional block diagram of a transmission interval control unit according to the first embodiment.

FIG. 3 is an operation time chart of the data transmission control device according to the first embodiment.

FIG. 4 is an operation time chart of the data transmission control device according to the first embodiment.

FIG. 5 is a schematic functional block diagram of a data transmission control device according to a second embodiment.

FIG. 6 is a schematic functional block diagram of a transmission interval control unit according to the second embodiment.

FIG. 7 is a state transition diagram of a transmission interval counter according to the second embodiment.

FIG. 8 is an operation time chart of the data transmission control device according to the second embodiment.

FIG. 9 is an operation time chart of the data transmission control device according to the second embodiment.

FIG. 10 is a configuration diagram of a method for reducing programming execution time in a conventional technique.

[Explanation of symbols]

1 flip-flop 1 2 flip-flops 2 3 Flip-flop 3 4 flip-flops 4 5 flip-flops 5 6 flip-flops 6 7 flip-flops 7 8 flip-flops 8 9 flip-flops 9 10 flip-flops 10 12 Transmission interval control means 13 Comparison means 14 Comparison means 15 Read control circuit 16 Data transmission control device 17 Shift register circuit 18 Transmission interval control means 20 shift register circuit 21 Flash Memory 22 FPGA 23 1st comparison signal 24 Second comparison signal 26 address signal 27 Read signal 28 parallel data 29 Parallel load signal 30 shift signal 31 Read request signal 32 serial data 33 serial clock 35 Operation clock 36 Counter control means 37 Transmission interval counter 38 Counter control means 39 Transmission interval counter 40 Reset signal 50 ROM for storing program data 51 Program data transmission circuit 52 Programming control circuit 53 Compressed data release circuit 54 FPGA 55 logic cell array 56 logic cells

Continuation of front page    F term (reference) 5B077 AA14 AA18 FF13 GG04 GG13                       GG16                 5J039 HH07 HH09 KK09 KK11 KK26                       MM00 MM03 NN00                 5J042 BA01 BA09 BA14 CA13 CA15                       CA18 CA20 DA04

Claims (2)

[Claims] 1. A data transmission control device for transmitting program data to a programmable integrated device, comprising: comparing means for comparing at least two consecutive program data; and said program data based on a comparison result of said comparing means. A data transmission control device, comprising: transmission interval control means for controlling the transmission interval of the program; and data transmission means for transmitting the program data in accordance with the transmission interval outputted by the transmission interval control means. 2. At least two comparing means are provided,
2. The data transmission control device according to claim 1, wherein the transmission control unit outputs at least two transmission intervals based on a comparison result of the comparison unit.