JP2003347506A - Semiconductor device having chip-on-chip structure and semiconductor chip used in the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a chip-on-chip structure which is applied with effective anti-noise measures, and also to provide a semiconductor chip to be used in the same. <P>SOLUTION: Around bumps BC for connection to be used for interchip connection, a wall-like shield wiring sections S is so formed as to surround the bumps BC for connection. The shield wiring section S is connected to a bump BCG connected to the ground. In a region where no bumps BC for connection are formed, dummy bumps BD are formed. The dummy bumps BD are connected to the shield wiring section S. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a chip-on-chip structure in which another semiconductor chip is overlapped on the surface of a semiconductor chip, and a semiconductor chip for such a semiconductor device.

[0002]

2. Description of the Related Art A semiconductor device having a chip-on-chip structure in which a pair of semiconductor chips are opposed to each other and electrically connected to each other by bumps has been proposed, but there are still many problems to be solved in realizing the semiconductor device. . For example, by adopting a chip-on-chip structure,
Compared to storing each chip in a separate package,
It is expected that the area of the wiring boards of various electronic devices can be reduced to reduce their size. However, for example, in a device such as a mobile telephone that handles a high-frequency signal, it is important to take measures against noise. Therefore, a shield member for shielding the entire wiring board is separately provided. Therefore, the mere employment of the chip-on-chip structure cannot achieve a significant size reduction of the device.

[0003]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device having a chip-on-chip structure in which the above-mentioned technical problems are solved and effective noise countermeasures are taken, and a semiconductor chip therefor. It is to be.

[0004]

Means for Solving the Problems and Effects of the Invention According to the first aspect of the present invention, there is provided a semiconductor device having a chip-on-chip structure in which another semiconductor chip is superimposed on and joined to a surface of the semiconductor chip. A semiconductor chip for a semiconductor device, formed on a surface of the semiconductor chip, a plurality of inter-chip connecting portions for electrical connection with another semiconductor chip, and the plurality of chips on a surface of the semiconductor chip. A shield wiring portion formed in a wall shape surrounding the plurality of chip-to-chip connection portions that is routed between the inter-connection portions and includes a shield conductor portion connected to the low impedance portion. Semiconductor chip.

[0005] According to the above configuration, the shield conductor is provided so as to be routed between the plurality of inter-chip connection portions on the surface of the semiconductor chip and to surround the plurality of inter-chip connection portions. External noise can be prevented from reaching the inter-chip connection portion. Accordingly, when a semiconductor device having a chip-on-chip structure is formed by overlapping and joining another semiconductor chip to the semiconductor chip, it is not necessary to separately provide a noise shield structure.

In addition, since the gap between the chips can be supported by the shield conductor portion, the stress acting on the semiconductor chip for resin sealing or the like can be dispersed, and the deformation of the semiconductor chip due to mechanical pressure, stress distortion, or the like can be achieved. Can be prevented. As a result, a semiconductor device having a chip-on-chip structure that can exhibit stable element characteristics can be realized. In particular, as described in claim 2, the inter-chip connecting portion is
If the semiconductor chip is arranged so as to be substantially uniform on the connection surface with the other semiconductor chip, deformation of the semiconductor chip due to mechanical pressure, stress distortion, or the like can be more effectively prevented.

[0007] As described in claim 3,
The inter-chip connection portion and the shield conductor portion may be a metal protruding portion formed by protruding on the surface of the semiconductor chip. The metal raised portion may be a so-called bump in which a metal is raised by plating or the like,
The metal deposition film may not be raised as high as the bump. The invention according to claim 4 is the semiconductor chip according to any one of claims 1 to 3, wherein the inter-chip connection portion and the shield conductor portion are formed of the same material.

According to this structure, the inter-chip connection portion and the shield conductor portion can be formed in the same step.
The manufacturing process is simplified. According to a fifth aspect of the present invention, the shield conductor further includes a dummy bump formed on a surface of the semiconductor chip and not contributing to electrical connection with another semiconductor chip, and the shield wiring portion is joined to the dummy bump. The semiconductor chip according to any one of claims 1 to 4, wherein

According to a sixth aspect of the present invention, the inter-chip connecting portion comprises an inter-chip connecting bump, and the dummy bump comprises a plurality of bumps including the inter-chip connecting bump and the dummy bump substantially on the surface of the semiconductor chip. 6. The semiconductor chip according to claim 5, wherein an arrangement is selected so as to be evenly arranged. 7. The semiconductor device according to claim 7, wherein the second semiconductor chip is formed by superimposing and joining a second semiconductor chip on a surface of a first semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip are provided. A plurality of inter-chip connecting portions for electrical connection between the first semiconductor chip and the second semiconductor chip, the first semiconductor chip and the second semiconductor; A shield wiring portion formed in a wall shape surrounding the plurality of inter-chip connection portions by being routed between the plurality of inter-chip connection portions between surfaces facing the chips, and a low impedance portion; And a shield conductor connected to the semiconductor device.

With this configuration, the same effect as the effect described in claim 1 can be obtained. In a preferred embodiment of the present invention, the shield conductor further includes the first conductor.
And a dummy bump formed between the opposing surfaces of the first semiconductor chip and the second semiconductor chip and not contributing to the electrical connection between the first and second semiconductor chips. The shield wiring portion is joined to the dummy bump. 8. The semiconductor device according to claim 7, wherein:

According to a ninth aspect of the present invention, the inter-chip connecting portion is formed by an inter-chip connecting bump, and the dummy bump is formed by connecting the inter-chip connecting bump and a plurality of bumps including the dummy bump to the first semiconductor chip. The second
9. The semiconductor device according to claim 8, wherein the arrangement is selected so as to be arranged substantially evenly between surfaces facing the semiconductor chip.

[0012]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is an exploded perspective view of a semiconductor device according to one embodiment of the present invention. This semiconductor device is a so-called Chip-On-Chip in which a child chip 2 as a second semiconductor chip is superposed and joined to a surface 11 of a parent chip 1 as a first semiconductor chip. It has a structure.

The parent chip 1 is made of, for example, a silicon chip. The surface 11 is a surface on the active surface layer region side on which a functional element such as a transistor is formed on a semiconductor substrate, and the outermost surface is covered with a protective film of an insulator.
On the protective film, a plurality of pads 12 for external connection are arranged at predetermined positions so as to be exposed near the periphery of the surface 11 of the parent chip 1 having a substantially rectangular planar shape. The external connection pad 12 is a pad to be connected to the lead frame 14 by the bonding wire 13. A bonding area 15 of the child chip 2 is set in an area inside the parent chip 1, and the bonding area 15 has an internal connection pad P for connection with the child chip 2.
Are arranged.

The child chip 2 has a front surface 21 opposed to the parent chip 11 and a so-called face-down method.
Joined to. The child chip 2 is made of, for example, a silicon chip. The surface 21 is a surface of the semiconductor substrate on the active surface layer region side where elements such as transistors are formed, and the outermost surface is usually covered with a protective film of an insulator. FIG. 2 is an enlarged perspective view showing the configuration of the child chip 2. A bump B made of an oxidation-resistant metal, for example, gold, lead, platinum, silver, or iridium is formed on the surface 21 of the protective film of the child chip 2 so as to protrude from the surface 21.

The bumps B do not contribute to the electrical connection between the bumps BC (inter-chip connecting portions) for electrical connection with the circuits formed on the parent chip 1 and the circuits of the parent chip 1. And a dummy bump BD. The chip-to-chip connection bumps BC are arranged substantially evenly on the surface 21 that is the connection surface with the parent chip 1, and the dummy bumps BD are formed such that a plurality of bumps B are almost evenly arranged on the surface of the child chip 2. The arrangement is chosen to be arranged. That is, the dummy bump BD is arranged in a region where the connection bump BC is not arranged.

Further, a wall-shaped shield wiring portion S is routed on the surface 21 between the plurality of connection bumps BC so as to surround the connection bumps BC, and is formed to protrude from the surface 21. Have been. This shield wiring portion S is joined to the dummy bump BD,
Of the connection bumps BC, the bumps are connected to bumps BCG (low impedance portions) connected to the ground. Then, the shield wiring portion S, together with the dummy bump BD,
Each of the connection bumps BC is surrounded to form a shield conductor. The shield wiring portion S is made of the same material as the bump B, and can be formed simultaneously with the formation of the bump B in the manufacturing process. Of course, the shield wiring portion S can be formed using a material different from the bump B, but in this case, the shield wiring portion S is formed by a process different from the bump B forming process. .

As shown in FIG. 1, pads P are formed on the surface of the parent chip 1 at positions corresponding to the bumps B, and string-shaped pads PS corresponding to the shield wiring portions S are formed. Have been. Of the pads P, the pads PC formed at positions corresponding to the connection bumps BC are:
It is connected to a circuit inside the parent chip 1. On the other hand, the pad PD formed at a position facing the dummy bump BD is insulated from the internal circuit.
The string-shaped pad PS corresponding to the shield wiring portion S is also electrically insulated from the internal circuit.

FIG. 3 is an illustrative sectional view showing a state where the parent chip 1 and the child chip 2 are joined. The parent chip 1 and the child chip 2 are pressed against each other with the surfaces 11 and 21 facing each other. At this time, ultrasonic vibration is applied to the parent chip 1 and / or the child chip 2 as necessary. Thus, the bump B and the shield wiring portion S
And the pads P and PS are respectively joined. Thereby, the parent chip 1 and the child chip 2 are integrated to form a chip-on-chip structure. In this state, the bonding portion between the connection bump BC and the connection pad PC is connected to the dummy bump BD and the shield wiring portion S and the pads PD and PS.
Are surrounded by a shield conductor portion formed by bonding. Since the shield conductor is connected to the ground, the joint between the connection bump BC and the pad PC is shielded against external noise.

In addition, the bumps B are arranged on the child chip 2 almost uniformly, and the shield wiring portion S surrounds the connection pad PC while the parent chip 1
And the secondary chip 2. As a result, the semiconductor device having a chip-on-chip structure in which the parent chip 1 and the child chip 2 are joined is resin-sealed to form one package 40.
In this case, deformation such as stress distortion of the parent chip 1 or the child chip 2 does not occur, and the element characteristics formed inside these chips do not deteriorate.

As described above, according to the present embodiment, it is possible to realize a semiconductor device having good durability against mechanical pressure and stress caused by resin sealing and the like and including a good noise shield structure. This eliminates the need to provide a large shield mechanism for electronic devices such as mobile telephones, so that these devices can be downsized. Although the embodiments of the present invention have been described above, the present invention can be embodied in other forms. For example, in the above embodiment, the shield wiring portion S
Is connected to the ground, but may be connected to a power supply line (low impedance section).

Further, in the above embodiment, the bump B is provided on the child chip 2, but a similar bump may be provided on the parent chip 1 side, and the bump is provided on both the parent chip 1 and the child chip 2. Thus, chip-on-chip joining of the parent chip 1 and the child chip 2 may be achieved by joining the bumps. The same applies to the shield wiring portion S, and a similar shield wiring portion is provided on the front chip 21 side.
Alternatively, a shield wiring portion may be provided on both the parent chip 1 and the child chip 2 and these may be joined to each other.

Further, instead of a metal raised portion such as a bump, a metal deposited film or the like may be applied. The same applies to the shield wiring portion, and the shield wiring portion can be formed of a metal vapor-deposited film not having the height of a bump. Furthermore, in the above-described embodiment, the case where one child chip 2 is joined to the surface 11 of the parent chip 1 has been described. However, two or more child chips may be joined to the surface 11 of the parent chip 1. Good.

Further, in the above embodiment, the parent chip 1
Each of the sub chip 2 and the sub chip 2 is a chip made of silicon. However, in addition to silicon, a semiconductor chip using any other semiconductor material such as a gallium arsenide semiconductor or a germanium semiconductor can be used as the semiconductor device of the present invention. Can be applied to In this case, the semiconductor materials of the first semiconductor chip and the second semiconductor chip may be the same or different. In addition, various design changes can be made within the scope of the matters described in the claims.

[Brief description of the drawings]

FIG. 1 is an exploded perspective view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an enlarged perspective view showing a configuration of a child chip.

FIG. 3 is an illustrative sectional view showing a state where a parent chip and a child chip are joined.

[Explanation of symbols] 1 Parent chip (first semiconductor chip) 2 child chip (second semiconductor chip) P, PC, PD, PS pad B bump Bump for BC connection (connecting part between chips) BD dummy bump S Shield wiring section

Claims (9)

[Claims] 1. A semiconductor chip for a semiconductor device having a chip-on-chip structure in which another semiconductor chip is superimposed on and joined to a surface of a semiconductor chip. A plurality of inter-chip connection portions for electrical connection with the semiconductor chip; and a wall shape surrounding the plurality of inter-chip connection portions which is routed through the plurality of inter-chip connection portions on the surface of the semiconductor chip. A semiconductor chip, comprising: a formed shield wiring part; and a shield conductor part connected to a low impedance part. 2. The semiconductor chip according to claim 1, wherein said inter-chip connecting portion is arranged so as to be substantially uniform on a connecting surface of said semiconductor chip with said another semiconductor chip. 3. The semiconductor chip according to claim 1, wherein said inter-chip connecting portion and said shield conductor portion are formed of a metal raised portion raised on a surface of said semiconductor chip. 4. The semiconductor chip according to claim 1, wherein said inter-chip connecting portion and said shield conductor portion are made of the same material. 5. The shield conductor section further includes a dummy bump formed on the surface of the semiconductor chip and not contributing to electrical connection with another semiconductor chip, and the shield wiring section is joined to the dummy bump. The semiconductor chip according to claim 1, wherein: 6. The inter-chip connecting portion comprises an inter-chip connecting bump, and the dummy bump is such that the inter-chip connecting bump and a plurality of bumps including the dummy bump are arranged substantially evenly on the surface of the semiconductor chip. 6. The semiconductor chip according to claim 5, wherein an arrangement is selected. 7. A semiconductor device comprising a first semiconductor chip and a second semiconductor chip superposed and joined to a surface of the first semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip face each other. A plurality of inter-chip connecting portions provided between surfaces of the first and second semiconductor chips for electrical connection between the first semiconductor chip and the second semiconductor chip; A shield wiring portion formed in a wall shape surrounding the plurality of inter-chip connection portions and drawn around between the plurality of inter-chip connection portions between opposed surfaces, and connected to the low impedance portion. And a shield conductor. 8. The apparatus according to claim 1, further comprising:
And a dummy bump formed between the opposing surfaces of the first semiconductor chip and the second semiconductor chip and not contributing to the electrical connection between the first and second semiconductor chips. The shield wiring portion is joined to the dummy bump. The semiconductor device according to claim 7, wherein: 9. The inter-chip connecting portion includes an inter-chip connecting bump, and the dummy bump includes a plurality of bumps including the inter-chip connecting bump and the dummy bump, the first semiconductor chip and the second semiconductor chip. 9. The semiconductor device according to claim 8, wherein the arrangement is selected so as to be arranged substantially evenly between the surfaces facing each other.