JP2003347366A - Tape carrier for semiconductor device, semiconductor device and method for manufacturing the semiconductor device - Google Patents
Tape carrier for semiconductor device, semiconductor device and method for manufacturing the semiconductor deviceInfo
- Publication number
- JP2003347366A JP2003347366A JP2002151862A JP2002151862A JP2003347366A JP 2003347366 A JP2003347366 A JP 2003347366A JP 2002151862 A JP2002151862 A JP 2002151862A JP 2002151862 A JP2002151862 A JP 2002151862A JP 2003347366 A JP2003347366 A JP 2003347366A
- Authority
- JP
- Japan
- Prior art keywords
- tape
- semiconductor device
- leads
- carrier
- tape carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、光の透過性又は不
透過性を有する絶縁テープにリードが形成されて成るT
AB(Tape Automated Bonding)テープを、LSIチップ
に接続するフリップチップ接続を良好に行うことを可能
とする半導体装置用テープキャリア、半導体装置および
その半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a T-shaped insulating tape having leads formed on an insulating tape having light transmitting or non-transmitting properties.
The present invention relates to a tape carrier for a semiconductor device, a semiconductor device, and a method of manufacturing the semiconductor device, which enable good flip-chip connection of an AB (Tape Automated Bonding) tape to an LSI chip.
【0002】[0002]
【従来の技術】一般的にTABテープは次のように形成
されている。まず、50〜125μmの厚みで35m
m、48mm、70mm等の幅を有する有機ポリイミド
テープやガラスエポキシテープ等の吸水率1.4%以下
の絶縁フィルムに、パンチング加工によりデバイスホー
ルを形成すると共に、LSIチップの実装時にTABテ
ープ本体を送り出すためのパーフォレーションホール
(送り穴)を形成する。次に、この絶縁フィルムに8〜
24μmの厚さの接着剤によって18〜35μmの圧延
銅箔又は電解銅箔等の銅箔を貼り合わせた後、フォトレ
ジスト・エッチングプロセスによって所定の銅配線パタ
ーンを形成し、更にSnの無電解メッキ等を行ってTA
Bテープを形成する。2. Description of the Related Art Generally, a TAB tape is formed as follows. First, 35m with a thickness of 50 to 125 μm
Device holes are formed by punching on an insulating film with a water absorption of 1.4% or less, such as an organic polyimide tape or a glass epoxy tape having a width of m, 48 mm, 70 mm, etc., and the TAB tape body is mounted when mounting an LSI chip. A perforation hole (feed hole) for feeding is formed. Next, 8 ~
After bonding a copper foil such as a rolled copper foil or an electrolytic copper foil of 18 to 35 μm with an adhesive having a thickness of 24 μm, a predetermined copper wiring pattern is formed by a photoresist etching process, and further, electroless plating of Sn And TA
Form a B tape.
【0003】このTABテープのリードにLSIチップ
をフリップチップ接続した後、ポッティング封止して、
例えば、液晶用パネルに実装する。After connecting the LSI chip to the lead of the TAB tape by flip chip bonding, potting sealing is performed,
For example, it is mounted on a liquid crystal panel.
【0004】フリップチップ接続を行う場合、図5の
(a)に示すように、光の透過性の指標(明度を表す指
数)であるL値(色材第57巻第10号「色の測定」茶
木清著558〜568ページ、昭和59年10月参照)
が35以上の絶縁フィルム10にSnメッキリード12
が形成されたTABテープ14を用い、このTABテー
プ14のSnメッキのリード12に、Auバンプ16が
形成されたLSIチップ18を接続する。In the case of flip-chip connection, as shown in FIG. 5A, an L value (color material, Vol. 57, No. 10, "Color Measurement") which is an index of light transmittance (an index indicating lightness) is used. "See Kiyoshi Chaki, pages 558-568, October 1984)
Of the Sn plating lead 12 on the insulating film 10
Using an TAB tape 14 on which an Au bump 16 is formed, the LSI chip 18 on which an Au bump 16 is formed is connected to the Sn-plated lead 12 of the TAB tape 14.
【0005】即ち、図5(b)に示すように、ステージ
20上にLSIチップ18を載置し、このLSIチップ
18の上方に、Auバンプ16にSnメッキリード12
が対向するようにTABテープ14を配置し、絶縁フィ
ルム10の上方から加熱用ツール22と組み合わされた
CCDカメラ24によって、絶縁フィルム10を透過し
ながらSnメッキリード12とAuバンプ16との位置
合わせを行う。[0005] That is, as shown in FIG. 5 (b), an LSI chip 18 is mounted on a stage 20, and over the LSI chip 18, a Sn plating lead 12 is mounted on an Au bump 16.
The TAB tape 14 is arranged so that the Sn plating leads 12 are opposed to each other, and the position of the Sn plating leads 12 and the Au bumps 16 is adjusted while transmitting through the insulating film 10 by the CCD camera 24 combined with the heating tool 22 from above the insulating film 10. I do.
【0006】次に、図5(c)に示すように、加熱用ツ
ール22を絶縁フィルム10に所定時間当接して加熱す
ることによってSnメッキリード12とAuバンプ16
とのフリップチップ接続を行う。Next, as shown in FIG. 5 (c), a heating tool 22 is brought into contact with the insulating film 10 for a predetermined time and is heated so that the Sn plating lead 12 and the Au bump 16 are heated.
And flip-chip connection.
【0007】[0007]
【発明が解決しようとする課題】しかし、従来の半導体
装置用テープキャリア(TABテープ)を用いた半導体
装置においては、フリップチップ接続時の位置合わせを
CCDカメラ24で絶縁フィルム10を透過しながら行
うため、L値が35以上となる38μm以下で12.5
μm以上の厚さの絶縁フィルム10を用いなければなら
ない。このような薄い絶縁フィルム10を用いた場合、
絶縁フィルム10のこしが弱くなるため、搬送性が悪く
なるという問題がある。However, in a conventional semiconductor device using a tape carrier (TAB tape) for a semiconductor device, alignment at the time of flip chip connection is performed by the CCD camera 24 while passing through the insulating film 10. Therefore, when the L value is 35 or more and 38 μm or less, 12.5
The insulating film 10 having a thickness of not less than μm must be used. When such a thin insulating film 10 is used,
Since the stiffness of the insulating film 10 is weak, there is a problem that the transportability is deteriorated.
【0008】また、搬送性を向上させるために、TAB
テープの絶縁フィルム10に厚さが50μmの保護フィ
ルムを貼り合わせて補強することがあるが、その50μ
m厚の保護フィルムの耐熱性は120℃以下と弱く、フ
リップチップ接続時の加熱温度によっては熱変形が生じ
るという問題がある。Further, in order to improve transportability, TAB
A protective film having a thickness of 50 μm may be bonded to the insulating film 10 of the tape to reinforce the tape.
The heat resistance of the protective film having a thickness of m is as low as 120 ° C. or less, and there is a problem that thermal deformation occurs depending on the heating temperature at the time of flip chip connection.
【0009】また、上記の搬送性の悪化や熱変形によっ
て製品(半導体装置)の歩留まりと生産性が悪くなると
いう問題がある。Further, there is a problem that the yield and the productivity of the product (semiconductor device) are deteriorated due to the deterioration of the transportability and the thermal deformation.
【0010】本発明はかかる点に鑑みてなされたもので
あり、本半導体装置用テープキャリアにおけるフリップ
チップ接続時の搬送性を良くすることができると共に製
造過程での加熱時の熱変形を無くすことができ、これに
よって製品(半導体装置)の歩留まりと生産性を向上さ
せることができる半導体装置用テープキャリア、半導体
装置およびその半導体装置の製造方法を提供することを
目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is possible to improve the transportability of a tape carrier for a semiconductor device at the time of flip chip connection and to eliminate thermal deformation during heating in a manufacturing process. It is an object of the present invention to provide a semiconductor device tape carrier, a semiconductor device, and a method for manufacturing the semiconductor device, which can improve the yield and productivity of products (semiconductor devices).
【0011】[0011]
【課題を解決するための手段】上記課題を解決するため
に、本発明の半導体装置用テープキャリアは、絶縁テー
プ上に所定のパターンのリードを有する半導体装置用テ
ープキャリアにおいて、前記絶縁テープにおける前記リ
ードの形成面と反対面の所定部分に、搬送性の低下を抑
える補強銅層が形成されていることを特徴としている。According to another aspect of the present invention, there is provided a tape carrier for a semiconductor device having a predetermined pattern of leads on an insulating tape. It is characterized in that a reinforcing copper layer for suppressing a decrease in transportability is formed on a predetermined portion opposite to the surface on which the leads are formed.
【0012】また、前記絶縁テープは、光不透過性であ
ることを特徴としている。Further, the insulating tape is light-impermeable.
【0013】また、本発明の光透過性の絶縁テープ上に
所定のパターンのリードを有する半導体装置用テープキ
ャリアにおいて、前記絶縁テープにおける前記リードの
形成面と反対面に、透過性が損なわれないように銅箔が
形成されていることを特徴としている。In the tape carrier for a semiconductor device having leads of a predetermined pattern on a light-transmitting insulating tape according to the present invention, the transparency of the insulating tape is not impaired on a surface opposite to a surface on which the leads are formed. Is characterized in that a copper foil is formed as described above.
【0014】また、本発明の半導体装置は、絶縁テープ
の第1の面に所定のパターンのリードを有し、その第2
の面に搬送性の低下を抑える補強銅層を有するテープキ
ャリアと、前記テープキャリアの前記リードとバンプを
介してフリップチップ接続された半導体チップとを備え
たことを特徴としている。Further, the semiconductor device of the present invention has leads of a predetermined pattern on the first surface of the insulating tape,
And a semiconductor chip that is flip-chip connected via the bumps and the leads of the tape carrier.
【0015】また、本発明の半導体装置は、光透過性の
絶縁テープの第1の面に所定のパターンのリードを有
し、その第2の面に透過性が損なわれないように銅箔を
有するテープキャリアと、前記テープキャリアの前記リ
ードとバンプとを介してフリップチップ接続された半導
体チップとを備えたことを特徴としている。Further, the semiconductor device of the present invention has a predetermined pattern of leads on a first surface of a light-transmitting insulating tape, and a copper foil on a second surface of the insulating tape so that the transmittance is not impaired. And a semiconductor chip which is flip-chip connected via the leads and bumps of the tape carrier.
【0016】また、本発明の半導体装置の製造方法は、
光不透過性の絶縁テープの第1の面に所定のパターンの
リードを有し、その第2の面に搬送性の低下を抑える補
強銅層を有するテープキャリアの前記リードと、半導体
チップのバンプとを対向状態に配置する配置ステップ
と、前記配置ステップで前記対向状態とされた前記リー
ドと前記バンプの双方を撮像手段で撮像しながら双方を
接続するための位置合わせを行う位置合わせステップと
を含むことを特徴としている。Further, a method of manufacturing a semiconductor device according to the present invention
A lead of a tape carrier having a predetermined pattern of leads on a first surface of a light-impermeable insulating tape and a reinforcing copper layer for suppressing a decrease in transportability on a second surface thereof; And an alignment step of performing alignment for connecting both the leads and the bumps that have been set in the opposite state in the arrangement step while imaging both with the imaging unit. It is characterized by including.
【0017】[0017]
【発明の実施の形態】以下、本発明の実施の形態につい
て、図面を参照して詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.
【0018】図1は、本発明の第1の実施の形態に係る
TABテープおよびそれを用いた半導体装置の構成図で
ある。FIG. 1 is a configuration diagram of a TAB tape and a semiconductor device using the same according to a first embodiment of the present invention.
【0019】この図1に示すTABテープ{COF(Chi
p On Film又はChip on Frexible Cuircut)用のTABテ
ープ}を形成する場合、まず(a)に示すように、光不
透過性ポリイミドフィルム(絶縁フィルム)30の片面
に補強銅層31を貼り合わせて光不透過性キャスティン
グテープ32を形成する。このテープ32には、例えば
新日鐵化学製のエスパネックステープを用いる。エスパ
ネックステープとは、幅が35mmで、銅層が9μm、
ポリイミドフィルムが25μmの厚さのテープである。The TAB tape @COF (ChiF shown in FIG.
When forming a TAB tape for p On Film or Chip on Frexible Cuircut), first, as shown in (a), a reinforcing copper layer 31 is attached to one surface of a light-impermeable polyimide film (insulating film) 30. The light-impermeable casting tape 32 is formed. As the tape 32, for example, Espanex tape manufactured by Nippon Steel Chemical is used. ESPANEX tape has a width of 35 mm, a copper layer of 9 μm,
The polyimide film is a tape having a thickness of 25 μm.
【0020】次に(b)に示すように、光不透過性ポリ
イミドフィルム30に吸水率1.2%の接着剤33を8
μmの厚さで塗布し、この接着剤33に(c)に示すよ
うに、圧延銅箔又は電解銅箔等の銅箔34を貼り合わせ
た後、(d)に示すように、フォトレジスト・エッチン
グプロセスによって銅箔34を所定配線パターンに形成
し、更にSnの無電解メッキを行ってSnメッキリード
35を形成すると共に、補強銅層31を所定部分に残し
てTABテープ40を形成する。Next, as shown in FIG. 2B, an adhesive 33 having a water absorption of 1.2% is applied to the light-impermeable polyimide film 30 by 8%.
The adhesive 33 is coated with a copper foil 34 such as a rolled copper foil or an electrolytic copper foil as shown in (c), and then, as shown in FIG. A copper foil 34 is formed in a predetermined wiring pattern by an etching process, and further, electroless plating of Sn is performed to form a Sn plating lead 35, and a TAB tape 40 is formed leaving the reinforcing copper layer 31 in a predetermined portion.
【0021】そして、このTABテープ40に同(d)
に示すAuバンプ36が形成されたLSIチップ37
を、(e)に示すように、Snメッキリード35とAu
バンプ36との位置合わせを行ってフリップチップ接続
し、アンダフィルが阻害されないように封止樹脂38を
ポッティングする。The TAB tape 40 has the same shape (d).
LSI chip 37 formed with Au bump 36 shown in FIG.
As shown in (e), the Sn plating lead 35 and Au
The alignment with the bump 36 is performed to perform flip-chip connection, and the sealing resin 38 is potted so as not to hinder the underfill.
【0022】そのフリップチップ接続を行う場合、図2
の(a)に示すように、ステージ41上に補強銅層31
が当接してSnメッキリード35が上となるようにTA
Bテープ40を載置し、このTABテープ40の上方に
2台の図示しないCCDカメラを介して配置された加熱
用ツール44にLSIチップ37を固定する。この際、
LSIチップ37のAuバンプ36がSnメッキリード
35と対向するように固定する。When the flip-chip connection is performed, FIG.
As shown in (a) of FIG.
Contact so that the Sn-plated lead 35 faces upward.
The B tape 40 is placed, and the LSI chip 37 is fixed to a heating tool 44 disposed above the TAB tape 40 via two CCD cameras (not shown). On this occasion,
The Au bump 36 of the LSI chip 37 is fixed so as to face the Sn plating lead 35.
【0023】そして、上側のCCDカメラでAuバンプ
36を撮像すると共に、下側のCCDカメラでSnメッ
キリード35を撮像しながら、ステージ41のX方向お
よびY方向の移動によってSnメッキリード35とAu
バンプ36との位置合わせを行う。この位置合わせ後、
図2(b)に示すように、CCDカメラ43を水平方向
にシフトしてから、加熱用ツール44をSnメッキリー
ド35とAuバンプ36とが所定圧力で当接する位置ま
で下げ、所定時間加熱することによってSnメッキリー
ド35とAuバンプ36とのフリップチップ接続を行
う。While the upper CCD camera captures an image of the Au bump 36 and the lower CCD camera captures an image of the Sn plating lead 35, the stage 41 moves in the X and Y directions to move the Sn plating lead 35 and the Au plating.
The alignment with the bump 36 is performed. After this alignment,
As shown in FIG. 2B, after the CCD camera 43 is shifted in the horizontal direction, the heating tool 44 is lowered to a position where the Sn plating lead 35 and the Au bump 36 contact with a predetermined pressure, and the heating is performed for a predetermined time. Thus, flip-chip connection between the Sn plating lead 35 and the Au bump 36 is performed.
【0024】このように、第1の実施の形態のTABテ
ープおよびそれを用いた半導体装置によれば、一方の面
にSnメッキリード35が形成された光不透過性ポリイ
ミドフィルム30の反対の面に補強銅層31を所定箇所
に残してTABテープ40を形成したので、補強銅層3
1によってTABテープ40の強度が強くなり、フリッ
プチップ接続時の搬送性を良くすることができ、また、
フリップチップ接続工程の加熱による熱変形を無くすこ
とができる。これによって製品(半導体装置)の歩留ま
りと生産性を向上させることができる。As described above, according to the TAB tape and the semiconductor device using the same according to the first embodiment, the surface opposite to the light-impermeable polyimide film 30 having the Sn plating leads 35 formed on one surface. The TAB tape 40 was formed while leaving the reinforcing copper layer 31 at a predetermined position.
1, the strength of the TAB tape 40 is increased, and the transportability at the time of flip chip connection can be improved.
Thermal deformation due to heating in the flip chip connection step can be eliminated. As a result, the yield and productivity of products (semiconductor devices) can be improved.
【0025】図3は、本発明の第2の実施の形態に係る
TABテープおよびそれを用いた半導体装置の構成図で
ある。FIG. 3 is a configuration diagram of a TAB tape and a semiconductor device using the same according to a second embodiment of the present invention.
【0026】この図3に示すTABテープ(COF用の
TABテープ)を形成する場合、まず(a)に示すよう
に、光透過性ポリイミドフィルム(絶縁フィルム)50
の片面に、光透過性が損なわれないように補強銅層51
を貼り合わせて光透過性キャスティングテープ52を形
成する。このテープ52には、例えば片面に8μmの厚
さで銅メッキしたL値=54で厚さ25μm、幅35m
m、更に吸水率1.7%のカプトンEN(登録商標)テ
ープを用いる。When forming the TAB tape (TAF tape for COF) shown in FIG. 3, first, as shown in FIG.
Reinforced copper layer 51 on one side so that the light transmittance is not impaired.
Are bonded to form a light-transmissive casting tape 52. This tape 52 has a thickness of 25 μm and a width of 35 m, for example, having an L value of 54 plated with copper at a thickness of 8 μm on one side.
m, and a Kapton EN (registered trademark) tape having a water absorption of 1.7% is used.
【0027】次に(b)に示すように、光透過性ポリイ
ミドフィルム50に吸水率1.2%の接着剤53を8μ
mの厚さで塗布した後、(c)に示すように、パーフォ
レーションホール54を打ち抜き、この後、接着剤53
に粗化面の最大粗さ1.5μmで厚さ9μmの電解銅箔
55を貼り合わせキュアする。Next, as shown in (b), an adhesive 53 having a water absorption of 1.2% was applied to the light-transmitting polyimide film 50 for 8 μm.
m, a perforation hole 54 is punched out as shown in FIG.
Then, an electrolytic copper foil 55 having a maximum roughness of 1.5 μm and a thickness of 9 μm is bonded and cured.
【0028】次に(d)に示すように、フォトレジスト
・エッチングプロセスによって銅箔55を所定配線パタ
ーン(リードピッチが34μmと50μmの2種類のも
の)に形成し、更にSnの無電解メッキを行ってSnメ
ッキリード56を形成すると共に、補強銅層51を所定
部分に残してTABテープ60を形成する。Next, as shown in (d), a copper foil 55 is formed in a predetermined wiring pattern (two types having a lead pitch of 34 μm and 50 μm) by a photoresist etching process, and further, electroless plating of Sn is performed. Then, the Sn-plated lead 56 is formed, and the TAB tape 60 is formed while the reinforcing copper layer 51 is left in a predetermined portion.
【0029】そして、このTABテープ60に同(d)
に示すAuバンプ57が形成されたLSIチップ58
を、(e)に示すように、Snメッキリード56とAu
バンプ57との位置合わせを行ってフリップチップ接続
し、アンダフィルが阻害されないように封止樹脂59を
ポッティングする。Then, the same (d) is attached to the TAB tape 60.
LSI chip 58 on which Au bump 57 shown in FIG.
As shown in (e), the Sn plating lead 56 and Au
The alignment with the bump 57 is performed to perform flip-chip connection, and the sealing resin 59 is potted so that underfill is not hindered.
【0030】そのフリップチップ接続を行う場合は、従
来例で図5を参照して説明したと同様である。即ち、ス
テージ上にLSIチップ58を載置し、このLSIチッ
プ58の上方に、Auバンプ57にSnメッキリード5
6が対向するようにTABテープ60を配置し、補強銅
層51の上方から加熱用ツールと組み合わされたCCD
カメラによって、光透過性キャスティングテープ52を
透過しながらSnメッキリード56とAuバンプ57と
の位置合わせを行う。次に、加熱用ツールを補強銅層5
1に加圧して約100℃で約3秒間加熱することによっ
てSnメッキリード56とAuバンプ57とのフリップ
チップ接続を行う。The flip-chip connection is performed in the same manner as described with reference to FIG. That is, the LSI chip 58 is mounted on the stage, and the Au plating 57 is provided on the Au bump 57 with the Sn plating lead 5 above the LSI chip 58.
6 with the TAB tape 60 arranged so that they face each other, and a CCD combined with a heating tool from above the reinforcing copper layer 51.
The positions of the Sn plating leads 56 and the Au bumps 57 are adjusted by the camera while transmitting the light transmitting casting tape 52. Next, the heating tool is connected to the reinforcing copper layer 5.
By applying pressure to 1 and heating at about 100 ° C. for about 3 seconds, flip-chip connection between the Sn plating lead 56 and the Au bump 57 is performed.
【0031】このように、第2の実施の形態のTABテ
ープおよびそれを用いた半導体装置によれば、一方の面
にSnメッキリード56が形成された光透過性ポリイミ
ドフィルム50の反対の面に光透過性が損なわれないよ
うに補強銅層51が形成され、またパーフォレーション
ホール54が形成されて成るTABテープ60を形成し
たので、補強銅層51によってTABテープ50の強度
が強くなり、フリップチップ接続時の搬送性を良くする
ことができ、また、フリップチップ接続工程の加熱によ
る熱変形を無くすことができる。これによって製品(半
導体装置)の歩留まりと生産性を向上させることができ
る。As described above, according to the TAB tape of the second embodiment and the semiconductor device using the same, the surface opposite to the light-transmitting polyimide film 50 in which the Sn plating lead 56 is formed on one surface is formed. The reinforcing copper layer 51 is formed so that the light transmittance is not impaired, and the TAB tape 60 in which the perforation holes 54 are formed is formed. The transportability at the time of connection can be improved, and thermal deformation due to heating in the flip chip connection step can be eliminated. As a result, the yield and productivity of products (semiconductor devices) can be improved.
【0032】また、配線のピール強度を比較するため、
厚さ38μmのカプトンENにスパッタ後、8μmで両
面銅メッキしたものでも、同様にCOF用のTABテー
プを製作した。この組み合わせでは、パターン配線形成
(リードピッチが34μm、50μmの2種類)後、S
nメッキするとSnの染み込み(リード配線の浮き上が
りによる剥離)が認められ、特にリードピッチが34μ
mのものは、全面剥離してTABテープの品質を満足し
なかった。しかし、上記第2の実施の形態のTABテー
プ60は、Snの染み込みが認めらず、特にリードピッ
チが34μmのものは良好であった。In order to compare the peel strength of the wiring,
A TAB tape for COF was produced in the same manner using a Kapton EN having a thickness of 38 μm, which was sputtered and then copper-plated at 8 μm on both sides. In this combination, after forming the pattern wiring (two types of lead pitches of 34 μm and 50 μm), S
When n plating is applied, penetration of Sn (separation due to lifting of lead wiring) is observed, and particularly, the lead pitch is 34 μm.
In the case of m, the entire surface was peeled off and did not satisfy the quality of the TAB tape. However, the TAB tape 60 of the second embodiment did not show Sn penetration, and the one with a lead pitch of 34 μm was particularly good.
【0033】また、このTABテープ60は、絶縁抵抗
性が高く、耐マイグレーション特性に優れた微細配線
(ピッチが50μm以下)のCOF用のTABテープに
最適であることが判明した。Further, it has been found that this TAB tape 60 is suitable for a TAB tape for COF of fine wiring (pitch: 50 μm or less) having high insulation resistance and excellent migration resistance.
【0034】また、上記実施の形態では、デバイスホー
ル無しのフリップチップタイプのTABテープで、配線
上表面にソルダレジストを塗布しない場合であるが、図
4に示すようにソルダレジスト62又はフォトソルダレ
ジストを塗布する場合にも応用可能である。Also, in the above embodiment, the solder resist is not applied to the upper surface of the wiring with a flip chip type TAB tape having no device hole, but as shown in FIG. 4, the solder resist 62 or the photo solder resist is used. It is also applicable when applying.
【0035】更に、上記実施の形態のCOF用のTAB
用テープの構造は、片面のポッティング又はトランスフ
ァーモールド・タイプで、絶縁抵抗性が高く、また、耐
マイグレーション特性に優れた、微細配線(ピッチ80
μm)のCSP(Chip ScalePackage)や、テープBGA
(Ball Gride Array)のフリップチップタイプ及びワイヤ
ボンディングタイプのCSP等にも応用可能である。Further, the TAB for COF of the above embodiment is used.
The structure of the tape is a single-sided potting or transfer mold type, which has high insulation resistance and excellent migration resistance.
μm) CSP (Chip Scale Package) and tape BGA
(Ball Grid Array) flip chip type and wire bonding type CSP.
【0036】[0036]
【発明の効果】以上説明したように、本発明によれば、
光不透過性の絶縁テープ上に所定のパターンのリードを
形成し、このリードの形成面と反対面の所定部分に銅箔
を形成して半導体装置用テープキャリアを形成する。ま
た、この半導体装置用テープキャリアのリードと、半導
体チップのバンプとを対向状態とし、この対向状態にあ
るリードとバンプの双方を撮像手段で撮像しながら双方
を接続するための位置合わせを行うようにした。これに
よって、本半導体装置用テープキャリアにおけるフリッ
プチップ接続時の搬送性を良くすることができると共に
製造過程での加熱時の熱変形を無くすことができ、これ
によって製品(半導体装置)の歩留まりと生産性を向上
させることができる。As described above, according to the present invention,
A lead of a predetermined pattern is formed on a light-impermeable insulating tape, and a copper foil is formed on a predetermined portion of a surface opposite to a surface on which the lead is formed, thereby forming a tape carrier for a semiconductor device. Further, the leads of the semiconductor device tape carrier and the bumps of the semiconductor chip are set to face each other, and both the leads and bumps in the facing state are imaged by the image pickup means, and alignment is performed to connect them. I made it. As a result, it is possible to improve the transportability of the present semiconductor device tape carrier at the time of flip-chip connection and to eliminate thermal deformation during heating in the manufacturing process, thereby increasing the yield and production of products (semiconductor devices). Performance can be improved.
【図1】本発明の第1の実施の形態に係るTABテープ
およびそれを用いた半導体装置の構成図である。FIG. 1 is a configuration diagram of a TAB tape and a semiconductor device using the same according to a first embodiment of the present invention.
【図2】本発明の半導体装置用テープキャリアを用いた
半導体装置の製造方法の説明図である。FIG. 2 is an explanatory diagram of a method of manufacturing a semiconductor device using the semiconductor device tape carrier of the present invention.
【図3】本発明の第2の実施の形態に係るTABテープ
およびそれを用いた半導体装置の構成図である。FIG. 3 is a configuration diagram of a TAB tape and a semiconductor device using the same according to a second embodiment of the present invention.
【図4】他の実施の形態に係るTABテープおよびそれ
を用いた半導体装置の構成図である。FIG. 4 is a configuration diagram of a TAB tape and a semiconductor device using the same according to another embodiment.
【図5】従来の半導体装置用テープキャリアを用いた半
導体装置の製造方法の説明図である。FIG. 5 is an explanatory diagram of a method for manufacturing a semiconductor device using a conventional semiconductor device tape carrier.
10 絶縁フィルム 12,35,56 Snメッキリード 14,40,60 TABテープ 16,36,57 Auバンプ 18,37,58 LSIチップ 20,41 ステージ 22,44 加熱用ツール 24,42,43 CCDカメラ 30 光不透過性ポリイミドフィルム 31,51 補強銅層 32 光不透過性キャスティングテープ 33,53 接着剤 34 銅箔 38,59 アンダフィル 50 光透過性ポリイミドフィルム 52 光透過性キャスティングテープ 54 パーフォレーションホール 55 電解銅箔 62 フォトレジスト 10 Insulating film 12,35,56 Sn plating lead 14,40,60 TAB tape 16,36,57 Au bump 18, 37, 58 LSI chips 20, 41 stages 22,44 Heating tools 24, 42, 43 CCD camera 30 Light-impermeable polyimide film 31, 51 Reinforced copper layer 32 Light-impermeable casting tape 33,53 adhesive 34 Copper foil 38,59 underfill 50 Light transmitting polyimide film 52 Light transmitting casting tape 54 perforation hole 55 Electrolytic copper foil 62 Photoresist
Claims (6)
を有する半導体装置用テープキャリアにおいて、 前記絶縁テープにおける前記リードの形成面と反対面の
所定部分に、搬送性の低下を抑える補強銅層が形成され
ていることを特徴とする半導体装置用テープキャリア。1. A tape carrier for a semiconductor device having leads of a predetermined pattern on an insulating tape, wherein a reinforcing copper layer for suppressing a decrease in transportability is provided on a predetermined portion of the insulating tape opposite to a surface on which the leads are formed. A tape carrier for a semiconductor device, wherein the tape carrier is formed.
とを特徴とする請求項1記載の半導体装置用テープキャ
リア。2. The tape carrier for a semiconductor device according to claim 1, wherein the insulating tape is light-impermeable.
ンのリードを有する半導体装置用テープキャリアにおい
て、 前記絶縁テープにおける前記リードの形成面と反対面
に、透過性が損なわれないように銅箔が形成されている
ことを特徴とする半導体装置用テープキャリア。3. A tape carrier for a semiconductor device having leads of a predetermined pattern on a light-transmitting insulating tape, wherein copper is provided on a surface of the insulating tape opposite to a surface on which the leads are formed so as not to lose transparency. A tape carrier for a semiconductor device, wherein a foil is formed.
のリードを有し、その第2の面に搬送性の低下を抑える
補強銅層を有するテープキャリアと、 前記テープキャリアの前記リードとバンプを介してフリ
ップチップ接続された半導体チップとを備えたことを特
徴とする半導体装置。4. A tape carrier having a predetermined pattern of leads on a first surface of an insulating tape and a reinforcing copper layer for suppressing a decrease in transportability on a second surface thereof; A semiconductor device comprising: a semiconductor chip which is flip-chip connected via a bump.
のパターンのリードを有し、その第2の面に透過性が損
なわれないように銅箔を有するテープキャリアと、 前記テープキャリアの前記リードとバンプとを介してフ
リップチップ接続された半導体チップとを備えたことを
特徴とする半導体装置。5. A tape carrier having a predetermined pattern of leads on a first surface of a light-transmissive insulating tape and a copper foil on a second surface of the tape so as not to impair the transparency. A semiconductor device comprising: a semiconductor chip which is flip-chip connected via the lead of a carrier and a bump.
定のパターンのリードを有し、その第2の面に搬送性の
低下を抑える補強銅層を有するテープキャリアの前記リ
ードと、半導体チップのバンプとを対向状態に配置する
配置ステップと、 前記配置ステップで前記対向状態とされた前記リードと
前記バンプの双方を撮像手段で撮像しながら双方を接続
するための位置合わせを行う位置合わせステップとを含
むことを特徴とする半導体装置の製造方法。6. A tape carrier having a light-impermeable insulating tape having a lead of a predetermined pattern on a first surface and a reinforcing copper layer for suppressing a decrease in transportability on a second surface of the insulating tape. An arrangement step of arranging the bumps of the semiconductor chip in a facing state; and performing an alignment for connecting both the leads and the bumps in the facing state in the arranging step while imaging both of the leads and the bumps with imaging means A method for manufacturing a semiconductor device, comprising: a positioning step.
Priority Applications (1)
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JP2002151862A JP2003347366A (en) | 2002-05-27 | 2002-05-27 | Tape carrier for semiconductor device, semiconductor device and method for manufacturing the semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2002151862A JP2003347366A (en) | 2002-05-27 | 2002-05-27 | Tape carrier for semiconductor device, semiconductor device and method for manufacturing the semiconductor device |
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Publication Number | Publication Date |
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Family
ID=29769324
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JP2002151862A Pending JP2003347366A (en) | 2002-05-27 | 2002-05-27 | Tape carrier for semiconductor device, semiconductor device and method for manufacturing the semiconductor device |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100568496B1 (en) | 2004-10-21 | 2006-04-07 | 삼성전자주식회사 | Film circuit substrate having sn-in alloy layer |
JP2009194354A (en) * | 2008-02-18 | 2009-08-27 | Himax Optelectronics Corp | Cof film package structure, method for fabricating cof package structure, and method for combining driver ic and cof package structure |
JP2012175000A (en) * | 2011-02-23 | 2012-09-10 | Sharp Corp | Semiconductor device and manufacturing method of the same |
-
2002
- 2002-05-27 JP JP2002151862A patent/JP2003347366A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100568496B1 (en) | 2004-10-21 | 2006-04-07 | 삼성전자주식회사 | Film circuit substrate having sn-in alloy layer |
JP2009194354A (en) * | 2008-02-18 | 2009-08-27 | Himax Optelectronics Corp | Cof film package structure, method for fabricating cof package structure, and method for combining driver ic and cof package structure |
JP2012175000A (en) * | 2011-02-23 | 2012-09-10 | Sharp Corp | Semiconductor device and manufacturing method of the same |
US8598692B2 (en) | 2011-02-23 | 2013-12-03 | Sharp Kabushiki Kaisha | Semiconductor device and method for manufacturing same |
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