JP2003346494A - Method for verifying operation of semiconductor device and verification circuit built-in semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that a conventional memory built-in semiconductor device cannot verify operations of the actual product taking into account an operating margin of data read from the memory when the operating temperature and the operating voltage of the semiconductor device are changed. <P>SOLUTION: The semiconductor device includes a delay circuit 110 and an AND circuit 120. The delay circuit 110 delays a read enable signal 101 to set a read enable period in an ordinary state, and a read enable signal 121 outputted from the AND circuit 120 resulting from AND operation of the read enable signal 101 and the delayed read enable signal 111 has a read enable period shorter than that of the ordinary read enable signal 101. Thus, the memory data read operation can be verified under a tighter condition than that of an ordinary memory data read operation by producing the read enable signal 121 with the shorter read enable period and performing data read in this way. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to an operation verification in which data can be reliably read from a memory cell even when an operating condition of the semiconductor device changes in reading data from a built-in memory. The present invention relates to a semiconductor device operation verification method and a semiconductor device with a built-in verification circuit.

[0002]

2. Description of the Related Art A typical conventional method for reading memory data in a semiconductor device will be described below.

In FIG. 4A, reference numeral 430 denotes a memory built in the semiconductor device, and reference numeral 401 denotes a read enable signal for enabling the memory 430 to read data. FIG. 4B shows a read enable signal 401.
Indicates that memory data is read during the enable period.

[0004]

However, when memory data is read with the above-mentioned conventional configuration, the enable time of the memory read is the same as that in the normal operation even at the time of operation verification (at the time of inspection). When the conditions, particularly the operating temperature and the operating voltage change, there is a problem that it is not possible to sufficiently verify whether only data reading in an actual product is possible. In particular, when the semiconductor device does not operate, it is not possible to verify whether the data is due to the inability to read the memory data or the program error, which may reduce the reliability of the semiconductor device.

The present invention solves the above-mentioned conventional problems. When the operating conditions of a semiconductor device change, the data is read from the memory by a strict memory read enable signal corresponding to the operating conditions. It is an object of the present invention to provide a semiconductor device operation verification method and a semiconductor device with a built-in verification circuit that enable reliable operation verification in consideration of an operation margin.

[0006]

According to the method of verifying operation of a semiconductor device of the present invention, the operation of a semiconductor device having a memory in which the period of the pulse width of an input read enable signal is a read enable period during which data can be read is performed. A verifying method is characterized in that a data read operation from a memory is verified by inputting a read enable signal having a shorter pulse width than a read enable signal input to the memory during normal operation to the memory.

According to this method, the read enable period (time) is made shorter than that in the normal operation, so that the memory data is read under more severe conditions than the normal data read. By performing data read from the memory with a strict memory read enable signal corresponding to the operation conditions, reliable operation verification in consideration of the data read operation margin becomes possible.

Further, the semiconductor device with a built-in verification circuit according to the present invention comprises a semiconductor device having a memory in which the pulse width period of the input read enable signal is a read enable period during which data can be read out. A first read enable signal, a delay circuit for delaying by a predetermined time and outputting the first read enable signal, and a first read enable signal and a second read enable signal delayed by the delay circuit; And a logic circuit for outputting to the memory a third read enable signal having a pulse width corresponding to the pulse overlap period of the read enable signal.

According to this configuration, the first pulse having the predetermined pulse width for setting the read enable period in the normal operation is used.
The third read enable signal generated from the read enable signal and the second read enable signal delayed from the read enable signal and input to the memory has a shorter pulse width than the first read enable signal. Therefore, the read enable period (time) is shorter than during normal operation,
Memory data is read out under more severe conditions than normal data readout, and when the operating conditions of the semiconductor device change, the data readout of the memory is performed using a strict memory read enable signal corresponding to the operating conditions, thereby providing a data read operation margin. And reliable operation verification in consideration of the above.

In the normal operation, by setting the delay time of the delay circuit to 0, a third read enable signal having the same pulse width as the first read enable signal having a predetermined pulse width is generated and input to the memory. You.

Further, in the semiconductor device with a built-in verification circuit according to the present invention, the delay circuit determines a delay time according to an operating temperature condition of the semiconductor device. As a result, when the operating temperature condition of the semiconductor device changes, memory data is read with a strict memory read enable signal corresponding to the temperature condition, and reliable operation verification can be performed in consideration of the operating margin of the data reading temperature condition. Become.

In the semiconductor device with a built-in verification circuit according to the present invention, the delay circuit determines a delay time according to an operating voltage condition of the semiconductor device. This allows
When the operating voltage condition of the semiconductor device changes, memory data is read out with a strict memory read enable signal corresponding to the voltage condition, and reliable operation verification can be performed in consideration of a voltage reading operation margin of data reading. .

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1A shows a circuit configuration of a semiconductor device according to a first embodiment of the present invention. Fig. 1 (a)
, 101 is a read enable signal, 110 is a circuit having a delay to the read enable signal 101, 111
Is a read enable signal output from the delay circuit 110, and 120 is the read enable signal 101 and the delay circuit 1
A circuit that takes the logical product of the read enable signal 111 delayed by 10, 121 denotes a read enable signal output from the logical product circuit 120, and 130 denotes a memory. Here, the pulse width of the read enable signal 101 is a read enable period (data readable period) of the memory 130 during a normal operation.

FIG. 1 (b) shows a timing chart of the signal generated by FIG. 1 (a). 1A shows that the read enable signal 121 has a shorter data read enable time than the base read enable signal 101.

The operation of the semiconductor device according to the present embodiment will be described.

The read enable signal 101 is the delay circuit 1
10, the read enable signal 10
Read enable signal 11 delayed by time Dt1 with respect to 1
Create one. By taking the logical product of the read enable signal 101 and the delayed read enable signal 111,
The output read enable signal 121 has a shorter read enable period than the actual read enable signal 101.

When a read operation of memory data is performed with a signal generated by this circuit, the memory data is read under more severe conditions. Read enable signal 12
Reading data at 1 has a read operation margin as compared with the case where data reading is performed by the read enable signal 101 during normal operation of the semiconductor device, and the memory data reading in the actual product is performed. It is possible to reliably verify the operation at the time.

The delay circuit 110 has a plurality of delay times Dt1 classified according to operating conditions. After detecting the operating conditions, the delay circuit 110 detects the delay times Dt1 corresponding to the operating conditions.
1 (the delay circuit 110 can be set so that the delay time Dt1 becomes 0 regardless of the operating conditions). At the time of data read operation verification, a delay time Dt1 (not 0) which is a severe condition is selected by the delay circuit 110, and the data read operation of the memory 130 is performed. Then, as a result of the operation verification, the delay time Dt1 is set to 0 for non-defective semiconductor devices, and then shipped as a product.

As described above, according to the present embodiment, the data read is performed by generating the read enable signal 121 having a shorter read enable period than in the normal operation and reading the data.
Compared with normal memory data reading, memory data reading operation verification is performed under more severe conditions, and high quality of the semiconductor device can be secured.

Although the delay circuit 120 has a delay, it is not necessary to provide a delay when normal memory data reading is performed (ie, the delay time Dt1 is set to 0).
To).

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 2A shows a circuit configuration of a semiconductor device according to a second embodiment of the present invention. Fig. 2 (a)
, 201 is a read enable signal, 210 is a circuit for giving a delay to the read enable signal 201, 21
1 is a read enable signal output from the delay circuit 210, 220 is a read enable signal 201 and the delay circuit 2
A circuit that takes the logical product of the read enable signal 211 delayed by 10, 221 denotes a read enable signal output from the logical product circuit 220, and 230 denotes a memory. Here, the pulse width of the read enable signal 201 is a read enable period (data readable period) of the memory 230 during normal operation. The delay circuit 21
0 determines a delay parameter (delay time) with respect to the operating temperature of the semiconductor device, delays the read enable signal 201 according to the delay parameter, and outputs it as a read enable signal 211.

FIG. 2 (b) shows a timing chart of the signals shown in FIG. 2 (a). Dt2 indicates a delay parameter (delay time) determined by the operating temperature of the semiconductor device. The read enable signal 221 by the circuit shown in FIG.
Data read enable time is shorter than 01.

In the present embodiment, the delay circuit 210 determines the delay parameter Dt2 according to the operating temperature of the semiconductor device.

[0026]

[Table 1]

Table 1 shows a list of the delay parameter Dt2 of FIG. 2B determined by the delay circuit 210 of FIG. 2A.

Dt21 is a delay parameter determined when the temperature for operating the semiconductor device is equal to or higher than T1 and lower than T2;
t22 indicates a delay parameter determined when the temperature at which the semiconductor device operates is T2 or more and less than T3, and Dt23 indicates a delay parameter determined when the temperature at which the semiconductor device operates is T3 or more and less than T4.

Note that any method may be used to determine the delay parameter according to the operating temperature of the semiconductor device.

In Table 1, the condition of the delay parameter is 3
However, the method of the present invention can be realized if there are N (N is plural) cases including the case where the delay time Dt2 is 0 (the case of normal operation).

The operation of the semiconductor device according to the present embodiment will be described.

The read enable signal 201 is supplied to the delay circuit 2
10, the read enable signal 20
Read enable signal 21 delayed by time Dt2 with respect to 1
Create one. The delay time Dt2 at this time is determined by the delay parameters shown in Table 1 depending on the operating temperature of the semiconductor device. By taking the logical product of the read enable signal 201 and the read enable signal 211,
The output read enable signal 221 has a shorter enable time than the actual read enable signal 201 by the delay parameter corresponding to the operating temperature of the semiconductor device shown in Table 1. When a memory data read operation is performed with a signal generated by this circuit, the memory data is read under more severe conditions. Reading data with the read enable signal 221 has an operating temperature margin of the semiconductor device compared to the case where data reading is performed with the read enable signal 201 during normal operation of the semiconductor device. Reliable operation verification at the time of reading memory data in a product type is possible.

The delay circuit 210 detects the operating temperature of the semiconductor device at the time of verifying the data read operation, and selects a delay parameter determined in advance for that temperature. It is also possible to set the delay parameter to 0 without detection.) At the time of data read operation verification, a delay parameter whose delay time Dt2 is not 0 is selected by the delay circuit 210, and the data read operation of the memory 230 is performed. Then, as a result of the operation verification, a non-defective semiconductor device is set as a delay parameter such that the delay time Dt2 becomes 0, and then shipped as a product.

As described above, according to the present embodiment, by generating the read enable signal 221 under conditions that become more severe depending on the operating temperature of the semiconductor device and performing data reading, the operating temperature is lower than that of normal memory data reading. The memory data reading operation with a margin is verified, and high quality of the semiconductor device can be ensured.

Although the delay circuit 210 determines the delay condition according to the temperature condition, the delay parameter Dt2 may be set to 0 when normal memory data reading is performed.

Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 3A shows a circuit configuration of a semiconductor device according to the third embodiment of the present invention. Fig. 3 (a)
, 301 is a read enable signal, 310 is a circuit for giving a delay to the read enable signal 301, 31
1 is a read enable signal output from the delay circuit 310, 320 is a read enable signal 301 and the delay circuit 3
A circuit that takes the logical product of the read enable signal 311 delayed by 10, 321 denotes a read enable signal output from the logical product circuit 320, and 330 denotes a memory. Here, the pulse width of the read enable signal 301 is a read enable period (data readable period) of the memory 330 during normal operation. The delay circuit 31
0 determines the delay parameter (delay time) for the operating voltage of the semiconductor device, delays the read enable signal 301 according to the delay parameter, and outputs the read enable signal 301 as the read enable signal 311.

FIG. 3 (b) shows a timing chart of the signals shown in FIG. 3 (a). Dt3 indicates a delay parameter (delay time) determined by the operating voltage of the semiconductor device. The read enable signal 321 by the circuit shown in FIG.
Data read enable time is shorter than 01.

In this embodiment, the delay circuit 310 determines the delay parameter Dt3 based on the operating voltage of the semiconductor device.

[0040]

[Table 2]

Table 2 shows a list of the delay parameter Dt3 of FIG. 3B determined by the delay circuit 310 of FIG.

Dt31 is a delay parameter determined when the operating voltage of the semiconductor device is equal to or higher than V1 and lower than V2.
Represents a delay parameter for determining the semiconductor device when the operating voltage is V2 or more and less than V3, and Dt33 represents a delay parameter for determining the semiconductor device when the operating voltage is V3 or more and less than V4.

Note that any method may be used to determine the delay parameter based on the operating voltage of the semiconductor device.

In Table 2, the condition of the delay parameter is set to 3
As described above, the method of the present invention holds when there are N (N is plural) cases including the case where the delay time Dt3 is 0 (the case of normal operation).

The operation of the semiconductor device according to the present embodiment will be described.

The read enable signal 301 is supplied to the delay circuit 3
10, the read enable signal 30
Read enable signal 31 delayed by time Dt3 with respect to 1
Create one. The delay time Dt3 at this time is determined by the delay parameters shown in Table 2 depending on the operating voltage of the semiconductor device. By taking the logical product of the read enable signal 301 and the read enable signal 311,
The output read enable signal 321 has a shorter enable time for the read enable signal than the actual read enable signal 301 by the delay parameter for the operating voltage of the semiconductor device shown in Table 2. When a memory data read operation is performed with a signal generated by this circuit, the memory data is read under more severe conditions. Reading data with the read enable signal 321 has an operating voltage margin of the semiconductor device compared to the case where data reading is performed with the read enable signal 301 during normal operation of the semiconductor device. Reliable operation verification at the time of reading memory data in a product type is possible.

The delay circuit 310 detects the operating voltage of the semiconductor device at the time of data read operation verification, and selects a delay parameter determined in advance for the voltage (delay circuit 310 determines the operating voltage. It is also possible to set the delay parameter to 0 without detection.) At the time of data read operation verification, a delay parameter whose delay time Dt3 is not 0 is selected by the delay circuit 310, and the data read operation of the memory 330 is performed. Then, as a result of the operation verification, a non-defective semiconductor device is set as a delay parameter such that the delay time Dt3 becomes 0, and then shipped as a product.

As described above, according to the present embodiment, by generating the read enable signal 321 under conditions that become more severe depending on the operating voltage of the semiconductor device and performing data reading, the operating voltage is lower than that of normal memory data reading. The memory data reading operation with a margin is verified, and high quality of the semiconductor device can be ensured.

Although the delay circuit 310 determines the delay condition according to the voltage condition, the delay parameter Dt3 may be set to 0 when normal memory data reading is performed.

[0050]

According to the present invention, the read enable period for reading data from the memory is set to a time in consideration of the operating margin of the actual product in accordance with the operating environment of the semiconductor device, thereby enabling normal data to be read. It is possible to reliably perform read operation verification, which has an excellent effect that high quality of a semiconductor device can be ensured.

[Brief description of the drawings]

FIG. 1 is a block diagram and a timing chart of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a block diagram and a timing chart of a semiconductor device according to a second embodiment of the present invention;

FIG. 3 is a block diagram and a timing chart of a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a block diagram and a timing chart of a conventional semiconductor device.

[Explanation of symbols]

101 base read enable signal 110 delay circuit 111 read enable signal 120 output from delay circuit 110 logical product circuit 121 read enable signal 130 output from logical product circuit 120 memory 201 read enable signal 210 base and delay circuit 211 Read enable signal 220 output from delay circuit 210 AND circuit 221 Read enable signal 230 output from AND circuit 220 Memory 301 Read enable signal 310 serving as a base Delay circuit 311 Read enable signal 320 output from delay circuit 310 AND circuit 321 Read enable signal 330 output from AND circuit 320 Memory

Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat II (reference) G01R 31/28 VF term (reference) 2G132 AA08 AB01 AG09 AK07 AK21 AL11 4M106 AA08 AC07 5F038 DF01 DF05 DT07 DT15 EZ20 5L106 DD22 EE02 EE03 FF05 GG03

Claims (4)

[Claims] 1. A method of verifying operation of a semiconductor device including a memory in which a period of a pulse width of an input read enable signal is a read enable period in which data can be read, wherein the method is input to the memory during a normal operation. A method for verifying operation of a semiconductor device, wherein a data read operation from the memory is verified by inputting a read enable signal having a pulse width shorter than the read enable signal to the memory. 2. A first read enable signal having a predetermined pulse width is input to a semiconductor device including a memory in which a period of a pulse width of an input read enable signal is a read enable period in which data can be read. A delay circuit for delaying and outputting a predetermined time; and a first read enable signal and a second read enable signal delayed by the delay circuit.
A semiconductor device with a built-in verification circuit, comprising: a logic circuit for outputting to the memory a third read enable signal having a pulse width of an overlapping period of the first and second read enable signals. 3. The delay circuit according to claim 2, wherein the delay time is determined according to an operating temperature condition of the semiconductor device.
The semiconductor device with a built-in verification circuit according to the above. 4. The delay circuit according to claim 2, wherein the delay time is determined by an operating voltage condition of the semiconductor device.
The semiconductor device with a built-in verification circuit according to the above.