JP2003346491A - Nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a sense system for a flash memory with ease of layout and operable stably at a high speed. <P>SOLUTION: Sense amplifiers are switched and used by a plurality of bit lines. The sense amplifiers and latches are provided separately, and also a sense operating means that precharges the bit lines at a voltage lower than a gate voltage of a MOS inserted between the bit lines and the sense amplifiers by a threshold voltage is provided. Thus, the layout pitch is a plurality of the layout pitches of the memory cells to permit the ease of layout. The sense amplifiers mainly for analog operations and the latches mainly for digital operations are independently designed. Since it is not required to discharge the bit lines having a large parasitic capacitance, the memory can be operated stably at a high speed. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to simplification of layout and speeding up of a sense system of a flash memory.

[0002]

2. Description of the Related Art FIG. 30 shows a conventional example. This is 1994
Symposium on VS IE Circuits, Digest of Technical Papers pp. 61-62 (1994 Symposium on VLSI C)
IRCUITS, DIGESTOF TECHNICA
L PAPERS) (Non-Patent Document 1). In this conventional example, a sense latch SL serving both as a sense amplifier and a write latch circuit is arranged for one bit line BL connected to the memory cell MC. Bit line B
L and the IO terminal of the sense amplifier are MO controlled by TR.
The M1 connected to the SM2, the IO terminal of the sense latch is connected in series with the M3 input to the gate, and the M1 controlled by the PG determines whether or not to charge the bit line according to the state of the sense latch. Can be controlled every time As a result, as described in the above document, verification can be performed for each bit, and the threshold voltage distribution of the memory cell after writing can be reduced. MD is a MOS that is controlled by the DDC and discharges the bit line, and is an MO that is controlled by the SET.
S is a MOS for setting SL so that the IO terminal is initially at a high level. VSA is a power supply for a sense latch or the like, and VWEL is a well power supply for a memory cell. As described above, in the conventional example, M1 to M3, S
L was located. Further, in the sensing operation, the bit line BL is charged in advance, this is discharged by the memory cell MC, and the voltage difference after the discharge of the bit line BL due to the difference in information of the memory cell is amplified and read by the sense latch SL.

[0003]

[Non-Patent Document 1] 1994 Symposium on VS IE Circuits, Digest of Technical Papers, pp. 61-62

[0004]

However, as the miniaturization of memory cells progresses, it becomes difficult to match the layout pitch of memory cells with the layout pitch of peripheral circuits. In particular, technological innovations are progressing so that miniaturization of memory cells is easier, and it is difficult to match peripheral circuits that are complicated in terms of circuit with miniaturization of memory cells. In particular, it is difficult to directly drive the memory cells or to lay out peripheral circuits for reading signals from the memory cells as in the above-described conventional example.

In order to reduce the chip area, the number of peripheral circuits for reading signals from the memory cells, that is, the number of sense amplifiers is reduced so that a large number of memory cells are connected to one sense amplifier. Becomes large. Therefore, in the method of precharging the bit line and discharging the electric charge with the current of the memory cell as in the conventional example, the time required for discharging the electric charge until the sense amplifier can amplify increases. In particular, when the power supply voltage is reduced for low power and high reliability, the read current of the memory cell decreases, which is a serious problem.

[0006]

In order to solve this problem,
In the present invention, the sense amplifier and the latch are separately provided, and the sense amplifier is switched between a plurality of bit lines using a switch. Further, a MOS is inserted between the bit line and the sense amplifier, and the potential of the bit line on the memory cell side is precharged to a voltage lower than the gate voltage of the MOS by a threshold voltage.

[0007]

[Function] Since the sense amplifier and the latch are provided separately,
A sense amplifier that mainly performs an analog operation and a latch that mainly performs a digital operation can be independently designed. That is, a MOS having a long gate length is used in the sense amplifier in order to suppress manufacturing variations, and a MOS having a short gate length can be used in the latch because the necessity is small. further,
Since the sense amplifier is switched and used by a plurality of bit lines using a switch, the layout pitch is equivalent to a plurality of layout pitches of the memory cells, and the layout becomes easy.

Further, by precharging the bit line by a threshold voltage lower than the gate of the MOS inserted between the sense amplifier and the sense amplifier, when the memory cell is turned on, the potential of the bit line on the memory cell side becomes this potential. As a result, only the sense amplifier is discharged. Therefore, there is no need to discharge a bit line having a large parasitic capacitance, and only the parasitic capacitance on the sense amplifier side from the inserted MOS needs to be discharged. For this reason, high-speed operation becomes possible.

[0009]

FIG. 1 is a diagram showing a first embodiment of the present invention. D11 to D28 are bit lines, and memory cells M11 to M116 are arranged at intersections with the word lines W1. There are actually a plurality of word lines, and two-dimensionally spread memory cells are selected by a word line and a data line. S
Reference numerals 11 to S22 denote sense amplifiers for amplifying the current of the memory cell, and the switches S111 to S224 share four bit lines. Also, since the memory cells are arranged on the left and right of the memory cell array ARY and the bit lines are distributed on the left and right for each line, the sense amplifiers are arranged at a pitch of eight bit lines. Thus, the layout of the sense amplifier can be facilitated. The bit lines are connected to the latches L111 to L224 by the switches SL111 to SL224.
224 and one-to-one. By storing information necessary for writing to a memory cell in the latch and simultaneously applying a corresponding voltage to the memory cell, the writing time can be reduced. Since this latch only holds a voltage corresponding to 1 or 0, less attention is paid to the symmetry of the parasitic capacitance and resistance on the layout and the manufacturing variation than the sense amplifier. In the present invention, since the latch and the sense amplifier are provided independently, the latch can be laid out for each bit line. The signal amplified by the sense amplifier is Y
The IO lines IO1, IO1,
The signal is sent by IO2 to a main amplifier in a subsequent stage not shown in this drawing.

FIG. 2 is a diagram showing an example of a read sequence according to the present invention. The information of the memory cell selected by one word line W1 is amplified by the sense amplifier, and a signal is sent from the sense amplifier to the IO line. Characteristically, since a sense amplifier is shared by a plurality of bit lines, signal amplification by the sense amplifier and transfer to the IO line are repeated by the number of shared lines. Further, when the left and right sense amplifiers operate, adjacent bit lines are not selected. Thereby, interference between bit lines can be reduced. This is particularly effective in the conventional system in which the entire bit line is discharged by the memory cells in the configuration shown in FIG.

First, the word line W1 is selected and the switch S
S111, SS121, SS212, and SS222 are selected. Thereby, the bit lines D11, D14, D2
1, D24 and the sense amplifier are connected, and the memory cell M1
Information of 1, M14, M19, and M112 appears on the bit lines. Thereafter, the sense amplifiers S11, S12, S21,
S22 is turned on to amplify the signal. At this time, before amplification,
Switches SS111, SS121, SS212, SS2
Alternatively, amplification may be performed after turning off the capacitor 22 and disconnecting the capacitance of the large bit line. When a sufficient signal is obtained in the sense amplifier, the signal is transferred to the IO line by sequentially switching the Y selection switches. The signal on the IO line is sent to the main amplifier at the subsequent stage, where it is amplified and output. When the transfer to the IO line is completed, the process proceeds to reading of the next memory cell. Switch SS11
2, SS122, SS213 and SS223 are selected.
Thereby, the bit lines D13, D16, D23, D2
6 and the sense amplifier are connected. Thereafter, this signal is amplified by a sense amplifier and transferred to the IO line. Similarly, FIG.
As shown in (1), the transfer is repeated after amplifying one after another. With these operations, an operation can be performed with the word line selected, or an operation can be performed to select again each time the sense amplifier operation is performed. Through the above operation, information of the memory cell selected by one word line W1 can be read.

FIG. 3 is a diagram showing an example of a write sequence. Characteristically, the operation of first writing information from the IO line to the sense amplifier and transferring the information in the plurality of sense amplifiers to the latches is repeated by the number of bit lines sharing the sense amplifier, and is repeated for all the latches. After storing the information, a voltage corresponding to the information is simultaneously applied to the memory cells. That is, first, the switches Y11,
Y21 is turned on. Thereby, the information of the IO line is loaded into the sense amplifiers S11 and S21. Next, the switches Y12 and Y22 are turned on, and the information of the IO line is loaded into the sense amplifiers S12 and S22. Although only this is shown in the first embodiment, this operation is actually repeated by the number of sense amplifiers. Next, the data in the sense amplifier is transferred to the latch. That is, the switches SS111, SL111, SS211, SL21
1, SS121, SL121, SS221, SL221
Is turned on to connect the sense amplifier and the latch. At this time, the bit line also has the same voltage as the voltage corresponding to the data in the sense amplifier, which can be directly applied to the memory cell. Next, only the sense amplifier is disconnected while the latch and the bit line remain connected. For this purpose, the switches SS111, SS211, SS121, SS
221 is turned off, and SL111, SL211, SL12
1, keep SL221 ON. This operation is repeated by the number of bit lines sharing the sense amplifier. Here, since the example is shared by four lines, it is repeated four times. By this operation, information is stored in all the latches. Next, a voltage is applied to the memory cell. For this purpose, a voltage is applied to the word line W1, and a switch for connecting a bit line and a memory cell described later is turned on. As a result, a voltage is applied to the memory cell from the word line and the bit line, and information is written to the memory cell according to the voltage of the bit line. At this time, as shown in FIG. 3, the power supply voltage of the latch may be increased on the way to increase the bit line voltage. That is, the applied voltage is changed between the first half and the second half of one write pulse. Thereby, it is possible to reduce an adverse effect due to overshoot and a large write tunnel current at the beginning of a write cycle. When the writing is completed, the latch is disconnected, the bit line is discharged, and the word line is not selected. Thereafter, the operation proceeds to the verify operation described in FIG.

One of the features of the present invention is that a latch and a sense amplifier are provided independently. As mentioned in the above description, FIG. 4 summarizes the effects at this time. First, the latch mainly performs digital operation, and the sense amplifier mainly performs analog operation. Now, it is generally known that when the gate length is reduced, the variation in the threshold voltage due to the manufacturing variation increases. Since the threshold voltage greatly affects the sensing ability of the sense amplifier, the variation of the threshold is not preferable. For this reason, in the sense amplifier, it is necessary to use a large gate length (for example, 2 μm) to reduce the influence of manufacturing variations, and to perform a layout with good symmetry in consideration of resistance and parasitic capacitance. . On the other hand, since the function as a latch is mainly for holding write data, the gate length may be small (for example, 0.4 μm), and there are few points to pay attention to in the layout, which is easy. Therefore, in the conventional latch / sense amplifier integrated type, the gate length is increased to maintain the sense amplifier function. In the present invention, the latch and the sense amplifier are separated to reduce the gate length of the MOS transistor of the latch. As a result, the chip area is made smaller than in the past. If the number of the sense amplifiers is the same as the number of the latches, the area for the sense amplifiers increases. Therefore, in the present invention, the sense amplifiers are shared by a plurality of bit lines. In the present invention, since the memory cell is non-volatile, rewriting like DRAM is not required, and there is no particular problem in sharing the sense amplifier.

In the flash memory, verification is performed for each bit as described in the conventional example. FIG. 5 shows bit-by-bit verification according to a second embodiment of the present invention subsequent to the write operation of FIG. The feature of this method is that the latch is treated as a second memory cell, the state of the latch is read out to a bit line, and then the memory cell is read out. In order to achieve this, the gate voltage of the MOS connecting the latch and the bit line is specified. First, as shown in (A), after the application of the first write pulse is completed, precharge for verification is performed. The case where the output of the latch is 0V and the case where it is 2V are shown. This voltage is an example, and when the output of the latch is 2 V, it indicates the case of performing writing, and the output of the latch is 0 V
At the time of, the case where writing is not performed is shown. In both precharges, MOS connecting the latch and bit line
The gate voltage of the MOS MS connecting the sense amplifier and the bit line is set to VC
And turn it on. For this reason, SL111 is at 0V and SS111 is at VC. In this state, a voltage of 1 V + Vth is applied to the gate of the precharge MOS MN. Here, Vth is the threshold voltage of MN. As a result, the bit line is precharged to approximately 1V.

Next, the state of the latch is detected as (B). For this purpose, 1 V is applied to the gate of the ML connecting the latch and the bit line. When the output of the latch is 0 V, this corresponds to the source voltage of ML, the drain voltage of ML, which is the precharge voltage of the bit line, is 1 V, and the gate voltage of ML is 1 V, so that ML is turned on and the bit line is discharged. For example, it becomes (1-VA) V. On the other hand, when the output of the latch is 2
In the case of V, this corresponds to the drain voltage, the gate voltage of the ML is 1 V, and the source voltage, which is the precharge voltage of the bit line, is 1 V.
V, and the ML is off. Therefore, the voltage of the bit line remains at 1V.

Next, reading of the memory cell is performed. At this time, the ML is off. The word line voltage depends on the threshold voltage of the memory cell to be verified. In FIG. 6, the voltage is set to 1.5 V as an example. Here, the case where the threshold voltage of the memory cell is high is shown in (C-1), and the case where it is low is shown in (C-2). If the threshold voltage is low, it means that the data has been written, and if the memory cell has already been written, or if the write pulse before this verification is performed, the threshold voltage becomes the desired voltage. This is the case when it becomes lower. (C-
In each of 1) and (C-2), the output of the latch may be 0V or 2V. First, when the threshold voltage of the memory cell is high (C-1), no current flows through the memory cell. Therefore, when the voltage of the bit line does not change and the output of the latch is 0 V, (1-VA)
It remains at 1 V when the output of the latch is 2 V. On the other hand, when the threshold voltage of the memory cell is low, the charge of the bit line is discharged, so that the bit line voltage changes. Therefore, when the output of the latch is 0V, the voltage is (1-VA-VB) V, and when the output of the latch is 2V, the voltage is (1-VB) V. In this state, amplification is performed by the sense amplifier.

FIG. 7 shows the result. Only when the output of the latch is 2V and the threshold voltage is high, the voltage is amplified to 2V, and the others are amplified to 0V. The case where the voltage is amplified to 2 V is a case where the threshold voltage of the memory cell is high and writing is necessary. Since the other is the case where writing is completed or writing is not performed, the bit line becomes 0V. In this state, the next write pulse may be applied, but before that, the state of the bit line and the state of the latch must be matched. In particular, when the writing is completed by the writing pulse immediately before the verification, the bit line is at 0 V, but the output of the latch remains at 2 V, and the writing is continued in this state. Therefore, as shown in FIG. 8, the gate voltage of the ML is set to VC. In this case, the output of the latch becomes the same voltage as the voltage of the large capacitance of the bit line. As a result, the contents of the latch can be matched with the result of the verification.
Thereafter, the sense amplifier is disconnected. Since the sense amplifier is shared by the other bit lines and latches, the same operation as described above is performed for the other bit lines and latches shared. When all latches and bit lines have been completed, the sense amplifier is disconnected. In this state, the bit line is already connected to the latch, and a required voltage is applied. At this voltage or after amplifying to a desired voltage, a word line is selected, a switch for selecting a bit line and a memory cell is selected, and a write operation is performed. As shown in FIG. 3, the voltage of the bit line may be changed on the way.

FIG. 9 is a diagram showing a third embodiment of the present invention. Characteristically, when the memory cell is turned on, only a part of the charge is discharged instead of discharging the entire bit line D11. To this end, a MOS MN1 is provided between the MOS transistor M11 and the sense amplifier S11. This gate signal is SS111, and the switch of the same name in the first embodiment and MN1 can serve as the same. Further, assuming that the node connecting MN1 to the sense amplifier is SN1, a MOS MP1 for performing precharge is provided here. This gate signal is PC. Further, a discharging MOS MN2 is provided in front of D11, and the gate signal thereof is DD.
C. SA is a start signal of the sense amplifier.

The operation and features of this configuration will be described with reference to FIG. It is assumed that D11 and SN1 have been discharged in the previous cycle. First, suppose that the PC is switched from the high level to the low level, and SS111 is at the level of VP1.
Here, it is assumed that VP1 is equal to or lower than VC. Then S
N1 is charged to VC. In MN1, the drain is S
N1 and the gate is SS111 and the source is D
It is 11. Therefore, D11 is VP which is lower than the voltage VP1 of SS11 by the threshold voltage Vth of MN1.
It will be precharged to 1-Vth. In this state, PC is set at a high level to turn off MP1, and the word line W1 is turned on.
Select 1. If the threshold voltage of the memory cell is low, a current flows through the memory cell and D
Eleven levels are about to go down. However, since the voltage of SN1 is higher than D11, VP1-Vt is determined by MN1.
D11 is charged to the level of h. Therefore, the level of D11 hardly changes, and only the level of SN1 changes. This operation continues while the level of SN1 is higher than D11. Therefore, if the word line is selected only while this condition is maintained, the bit line D11 having an effective large parasitic capacitance is effectively selected.
Is discharged, only the small parasitic capacitance SN1 needs to be discharged, so that the discharge time is short. After the word line is deselected, SS111 is set to low level and SN1 is set.
And D11 are electrically disconnected. Thereafter, the SA is switched to operate the sense amplifier to amplify the signal. SN1
, It is sufficient to amplify only those nodes, so that the sense amplifier can be operated at high speed and with low power consumption. At this time, the DDC is switched to turn on MN2 and the bit line D
11 is discharged.

FIG. 11 is a diagram showing a second operation example of the third embodiment. The difference from the first operation example is that the voltage of SS111 is changed from VP1 to VP2 after the end of precharge.
It is a point that is lowered to. This is because D11 is VP1-
Although Vth is precharged by MN1, the threshold voltage Vth fluctuates depending on the amount of current or the like. Therefore, even if the precharge is completed once, a minute current flows when the PC is turned off. This is because there are cases. Since the capacitance of SN1 is originally small, a significant voltage change may appear in SN1 with this current. In order to avoid this, after D11 is precharged to VP1-Vth, the voltage of the gate of MN1 is set to V.sub.V lower than VP1.
P2. In this case, MN1 is completely turned off. At the time of operation compared to the first operation example, the potential of D11 is set to VP2
Unless the memory cell is first pulled down to −Vth, SN
1 does not appear, but the difference between VP1 and VP2 is 0.
It may be about 1 to 0.2 V. As a result, the increase in the extraction time is small, and the voltage change of D11 is stably reduced to reduce
The voltage change of N1 can be increased. Other operations are the same as in the first embodiment.

FIG. 12 is a diagram showing a fourth embodiment of the present invention. This is an improved system of the system of the third embodiment. In the second operation example of the third embodiment, the gate voltage is changed. However, in this embodiment, MN3 is provided, and D11 is set to VP1-Vth.
Precharge higher than That is, as shown in FIG. 13, the level of the gate signal RPC of MN3 is set to VP3, and D11 is precharged to VP3-Vth. This Vth is the threshold voltage of MN3. This VP3-V
th may be set to be 0.1 to 0.2 V higher than VP1−Vth. In this case, MN1 is completely turned off. D
No signal appears at SN1 unless the potential of 11 is first extracted by the memory cell to VP1-Vth, but the increase of the extraction time is small. Other operations are the same as in the first embodiment.

The above third and fourth embodiments can be used in combination with the readout operation example of the first embodiment and the second embodiment. MP1 may be connected to the node connecting the sense amplifier of the second embodiment and MS, and the bit line may be precharged so as to be lower than the gate voltage of MS by Vth. The MN is necessary when combining the operation of the fourth embodiment with the second embodiment. If the gate voltage of the ML at the time of detecting the latch state is lower than the precharged bit line voltage, the operation of the second embodiment can be performed.

FIG. 14 is a diagram showing a fifth embodiment of the present invention. The difference from the first embodiment is that the switches ST111 to ST111
ST224 is provided. Thereby, the circuit portion of the sense amplifier and the latch can be separated from the large parasitic capacitance of the bit line. As a result, data can be exchanged only between the sense amplifier and the latch, so that power consumption can be reduced. An example of performing such an operation is shown in FIG.

FIG. 15 shows an example of multi-value storage for storing a plurality of pieces of information per cell. FIG. 15 shows a memory cell
It is assumed that the threshold voltage distribution as shown in FIG. Therefore, if the voltage of the word line is VW1, the memory cell having the lowest threshold voltage distribution is turned on. Hereinafter, in the case of VW2, the memory cell having one of the lower two distributions is turned on, and in the case of VW3, one of the lower three memory cells is turned on. In order to return to binary data, it is necessary to store these data once, and then perform a simple logical operation using this data. In this data storage, for example, when reading the memory cell M11 in FIG. 15 in the present invention, each data may be stored in the latch sharing the sense amplifier while changing the word line voltage by the sense amplifier. Therefore, it is necessary to exchange data between the sense amplifier and the latch. At this time, if the capacitance of the bit line remains connected, power consumption increases. By using the fifth embodiment, the bit line can be cut off in such a case, resulting in low power consumption. Specifically, as shown in FIG. 15C, first, the voltage of the word line W1 is set to VW1. The data of M11 at this time is amplified by the sense amplifier S11.
Next, ST111 to ST114 are closed, and SS1
11 and SL111 are turned on and the data of S11 is changed to L11
Transfer to 1. SS111 and SL111 are turned off once. Next, the voltage of the word line W1 is set to VW2, and the data of M11 is read in S11. Thereafter, ST111 to ST1
In the closed state, SS112 and SL112 are turned on to transfer the data of S11 to L112. Similarly, when the voltage of the word line W1 is VW3, the data is L
Transfer to 113. Here, although M11 has been described, similarly, data obtained by changing the word line voltage of one memory cell to VW1 to VW3 for every other four memory cells connected to W1 is stored in the latch. Next, the data of each latch is transferred. At this time, with ST111 to ST114 always closed, the contents of the latch are transferred to the IO line to the IO1 via the sense amplifier as shown in (d). As in this example, according to the fifth embodiment, data transfer between the sense amplifier and the latch can be performed with the bit line capacitance disconnected.

FIG. 16 shows an example of a memory cell array to which the present invention is applied. In this memory cell array,
As shown in the figure, the memory cells to which the word lines W11 to W1m are connected have the sources of the cells and the drains of the cells connected to each other, and are connected to BS11, BD11, BS12, and BD1.
It is 2. This connection is made by a buried diffusion layer wiring. These connected drains BD11 and BD12 are S
D is a switch MOS controlled by bit lines D11 and D11.
12 is connected. Also, the connected source BSs 11, B
S12 is a switch MOS controlled by SS, which is connected to the common source line CS. Switch MOS controlled by SD
Is turned on, the voltage of the bit line can be applied to the memory cell at the time of writing. By turning on both switch MOSs controlled by SD and SS, the common bit line is selected from the bit line when the word line is selected. A path through which the current of the memory cell flows to the source line can be formed. These elements are
A terminal formed in the well and applying a voltage to the well is VWE.

FIG. 17 shows an example of an applied voltage when the memory cell array of FIG. 16 is selected. In erasing, 12 V is applied to the word line.
And -4 V is applied to the well voltage VWE. As a result, charge transfer between the floating gate and the well occurs due to the voltage difference between the word line and the well voltage,
The threshold voltage of the memory cell increases. Since -4 V is also applied to the common source line, the applied voltage is as shown in the figure. At the time of the erasing operation, since -4 V is applied to SD, the voltage of the bit line set to 0 V in the drawing has no relation. Therefore, description of erasure has been omitted in the description of the operation of the present invention. In writing, 4 V / 0 V is applied to the bit line and -9 V is applied to the word line depending on whether or not to write. In the write operation, charge transfer occurs with a voltage difference of 4 V to the drain of the memory cell connected to the bit line and -9 V to the word line, but when the drain is 0 V, the voltage difference is small and the transfer of charge is very small. In this operation, in order to apply the voltage of the bit line to the memory cell, the voltage of SD is set to 7 V so that the switch MOS is completely turned on. At this time, the source BS11 of the memory cell becomes floating F.

Since a flash memory uses a voltage having a large absolute value, such as -9 V or 12 V shown in FIG.
The withstand voltage design of the OS is important. Here, FIG. 18 shows a usage example of the MOS oxide film thickness. If the oxide film thickness of the MOS is adjusted to a high voltage such as 12 V, for example, when the external power supply voltage is reduced to about 2 V in the future, the clock system and the main amplifier operated at this voltage will be slow. In addition, it is difficult to reduce a high voltage in accordance with the power supply voltage based on the current characteristics of the tunnel oxide film. Therefore, it is desirable to prepare two types of oxide films for peripheral circuits in addition to those for memory cells, and to use these in appropriate places.
However, in the flash memory chip, even in the example described in this embodiment, there are voltages such as 4 V and 7 V. Therefore, even if the thicker oxide film is adjusted to the highest voltage in the chip, the thinner one should be placed anywhere. It remains as an issue to match. FIG.
In No. 8, the sense amplifier is a thin film type. In the present embodiment, the sense amplifier generates 4 V, and TR must be set to about 7 V to transmit this voltage to the bit line. The oxide film thickness possible at 7 V is defined as a thin film system.
This 7 V is the voltage at the boundary between the thin film system and the thick film system. other,
4V operation sense amplifier can also be a thick film type,
At this time, since the thin film system is only a portion operated under an external power supply voltage, it can be made thinner than the case where the voltage is adjusted to 7V. Although not shown in FIG. 18, the internal voltage generating circuit also uses the thin film system and the thick film system while paying attention to the voltage at the selected boundary.

FIG. 19 shows a sixth embodiment of the present invention.
It shows a specific circuit configuration. On both sides of the memory cell array ARY, LC1L-LC8L, LC1R-
An LC8R and mainly a sense amplifier and SC1L and SC1R which are Y-system decode circuits are arranged. RPC0
The MOS controlled by the RPC 3 is a MOS for precharging the bit line, and the gate length of the MOS is set to be long to accurately precharge the bit line. DDC
MOSs controlled by 0 to DDC3 are MOSs for discharging bit lines. MOS controlled by DTR
Is a MOS for separating the bit line from the latch and the sense amplifier unit, the MOS controlled by TR0 to TR3 is a sense amplifier shared switch MOS, and
In the case of using the method of precharging the bit lines described in the embodiment, the gate length is set long. STR0-S
TR3 is a MOS connecting the latch and the bit line,
VLN0, VLP0 to VLN3, VLP3 are latch power supply terminals. The gate length of the latch may be short. In addition,
Bit lines D11, D13, D15, D1 are provided by sense amplifier shared switch MOS controlled by TR0 to TR3.
7 are grouped into N1.
Since one wiring crosses the latch, it is desirable to use a high-level metal wiring. For example, when three metal layers are used, the first layer is used in the circuit of the latch, the second layer is used for the power source of the latch, and the third layer is laid out on the third layer. The above are the components of LC1L, and other LC2L ~
The same applies to LC8L, LC1R to LC8R. Next, SC
In 1L, the MOS controlled by the PSA is the MOS for bit line precharge in the method described in the third and fourth embodiments, and the power supply is VSA. S1
1 to S18 are circuits including a sense amplifier and an equalizing MOS, and EQ is an equalizing start signal. Signals are exchanged between the IO lines IO0 to IO3, / IO0 to / IO3 and the sense amplifiers by the MOS controlled by YS1 and YS2. VR is a reference voltage of the sense amplifier, and is applied to the sense amplifier by a MOS controlled by SVR. When all the outputs of the sense amplifier become 1 or 0, either side of the MOS connected to the drain of EALL and WALL is turned off. This makes it possible to determine whether or not all the memory cells have reached the desired threshold voltage at the time of writing or erasing. For example, the second
As described in the embodiment, when the memory cell reaches a desired threshold voltage after the verification, the bit line side of the sense amplifier becomes 0 V, so that no current flows through WALL.
If this is detected, it can be known at a time that the writing has been completed. YS1 and YS2 are the predecode signals A
Yij, Y0, and Y1 are decoded and generated by a logic circuit in SC1L. The above is the parts in SC1L.
1R is also composed of similar components.

An operation example of the sixth embodiment will be described with reference to FIGS. In the following description, lowercase i and j are TR
The numbers 0, 1 and the like such as 0 to TR3 are collectively shown.

FIG. 20 is a diagram showing a first operation example of the sixth embodiment, and is a read operation example. In this example, the entire precharged bit line is discharged by a selected memory cell, and the result is amplified. The operation is divided into bit line discharge, bit line precharge, word line selection, amplification, and transfer phases. First, the address Ai is switched and a desired word line is selected. Here, DDCi is set to a high level while DTR is set to a high level, and the bit line is discharged. Next, TRi and SVR are set to the high level, the bit line side and the bit line of the sense amplifier are precharged to Vth from the signal level of RPCi, and the other of the sense amplifier is set to the voltage of VR. After that, a word line is selected. Thus, the amount by which the bit line is discharged differs according to the information of the memory cell. After the word line falls, TRi is set to low level to disconnect the bit line from the sense amplifier. In this state, the sense amplifier activation signals PP and PN are switched to change the bit line voltage and VR.
Amplify the voltage difference between After that, YS1 and YS2 are switched to output the information of the sense amplifier to the IO line. This operation is repeated as many times as necessary, although only two YSis are described in the drawing of the sixth embodiment. Thereafter, the sense amplifier is turned off, and equalization is performed by EQ. Thus, the read operation can be performed using FIG.

FIG. 21 is a diagram showing a second operation example of the sixth embodiment, showing a data latch for writing and a writing operation. In the data latch operation, the operation of storing information from the IO lines in all the sense amplifiers while changing the address and transferring the information collectively to the latches is repeated by the number of bit lines sharing the sense amplifier. . As a result, the write information is stored in all the latches.
Thereafter, a voltage corresponding to this information is applied to the memory cell, and writing is performed by a voltage difference from the word line. Specifically, first, necessary data is sent to the IO line, and this data is written to the sense amplifier by selecting YSi. This YSi
And send the next data to the IO line, change the address and
This data is written to the corresponding sense amplifier by selecting Si. This operation is repeated by the number of sense amplifiers.
When data can be stored in all sense amplifiers, TR0 and ST
R0 is selected, VLP0 and VLN0 are switched, and the data of the sense amplifier is transferred to the latch. At this time, a voltage also appears on the corresponding bit line. This can be used as it is as a voltage for writing. When the transfer is completed, only TR0 is set to the non-selected state, and the sense amplifier is disconnected. Thereafter, data is written into the sense amplifier again while switching the address via the IO line. After writing to all the sense amplifiers, the data of the sense amplifier is transferred to the latch as in the previous case. This time, TR1 and STR1 are selected, and VLP1 and VLN1 are switched to transfer the data of the sense amplifier to the latch. When this is repeated four times in the example of the sixth embodiment, data can be stored in all the latches. Next, the process proceeds to writing. Already, S
Since TRi is selected, the voltage from the latch appears. This voltage may be used as it is, or may be amplified as needed. For amplification, VLN0, VLP0-VL
What is necessary is just to increase the voltage difference between N3 and VLP3. In this state, if, for example, -9 V is applied to the word line and a switch connecting the memory cell and the bit line is selected, writing starts. When the writing is completed, the word line and STRi are set to a non-selected state.

FIG. 22 is a diagram showing a third operation example of the sixth embodiment, and shows a verify operation performed subsequently to the second operation example. First, DDC is selected and the data line is discharged. After that, TRi and SVR are set to high level, the bit line side and the bit line of the sense amplifier are precharged to fall from the signal level of RPCi by Vth, and the other of the sense amplifier is discharged. The voltage is VR. When the precharge is completed, SVR and RPCi are deselected. In this state, STRi is selected and set to about 1V. Thereby, as described in the second embodiment, the bit line is discharged depending on the state of the latch. Thereafter, the word line is selected, and the state of the memory cell is read out to the bit line. After a word line is selected for a certain time, the signal on the bit line is amplified by switching between PP and PN. Thereafter, the data of the sense amplifier is written into the latch. This operation is performed for all the bit lines sharing the sense amplifier. As a result, different signals appear depending on whether or not writing is performed on the bit line as described in the second embodiment. Thereafter, the writing shown in the latter half of FIG. 21 is performed, and the verification and the writing are repeated until all the memory cells have a desired threshold voltage.

FIG. 23 is a diagram showing a seventh embodiment of the present invention, in which the contents of the sense amplifiers on both sides of the memory cell array are interleaved and transferred to the main amplifier for high-speed reading. That is, switches SWL and SWR are provided for the main amplifier MA and the output buffer DBF, and the connection between the left and right IO lines IOL and IOR (there are T and B, respectively, and differential signals are transferred) is alternately switched. And read it out. According to this method, the frequency of the output Do of the output buffer is twice the frequency of each IO line. Therefore, high-speed reading can be performed. From the main amplifier to Do, it is possible to collectively lay out in a certain place on the chip and high-speed operation is possible.
The lines are slow because they run the size of the memory cell array.
Therefore, high speed operation can be realized by such operation. Although LTR and LTL may be omitted, they are circuits for latching the contents of the IO lines, and can be used to perform a pipeline operation. That is,
After taking in the contents of the sense amplifier on the IO line, the contents of the next sense amplifier can be taken in to the IO line while transferring the contents to the main amplifier circuit and thereafter.

This operation will be described with reference to FIG. A word line is selected, and the operation starts from a state where the read information of the memory cell is amplified by the sense amplifier. In this state, first, Y11 is selected. Thereby, the sense amplifier S
11 data is transferred to the IOL. Next, Y21 is selected, and the data of the sense amplifier S21 is transferred to the IOR. In parallel with this operation, the data of IOL is selected as SWL and sent to the main amplifier MA. As a result, data is output to the output Do. While performing this operation, IOR
Since SWR is completely transferred from the sense amplifier, SWR is selected. By this, IOR
Is sent to the main amplifier MA and output to the output Do. YS12 is selected in parallel with the output of this IOR. As a result, the data of the sense amplifier S12 becomes IO
L. YS22 is selected while selecting this data and sending it to the main amplifier. In this case, high-speed reading can be performed at twice the period of the operation of the IO line. Note that this method can also be used for an operation of sending data to a sense amplifier in a write operation.

FIG. 25 is a diagram showing an example of a main amplifier used in the present invention. The MOS in which the SWL and SWR signals are input to the gates corresponds to the switch in FIG. MN1L to MN3L and MN1R to MN3R are MOSs for equalizing the IO line, and equalize the IO line to the VIP voltage by the signal of EQ1. WI
Is a signal of write data, which is a signal generated from data at a data input terminal of a chip (not shown), and indicates whether the data is 1 or 0 at a high level or a low level.
WE is a signal indicating whether or not to transfer the WI signal to the IO line. MN6 and MN7 controlled by the MA are switch MOSs for connecting the bit lines to the main amplifier. This switch is a MOS controlled by SWL and SWR
It is good also as composition which also serves as. KT and KB are input terminals of the differential amplifier. The differential amplifier is an nMOS differential amplifier having a flip-flop type load. MN14 and MN1
5, and a differential signal is input to the gates of MN18 and MN19. MP3 and MP4 serve as current sources for the differential amplifier, and are controlled by the MEQ. MN8 to MN11 are MOSs for equalizing the input of the differential amplifier, and are controlled by the MEQ. This differential amplifier is excellent in low-voltage operation because the load is constituted by a flip-flop type CMOS. JT and JB are the outputs of the differential amplifier, and this signal is shaped by NA1 and NA2 forming the latch. After that, the drive capacity is increased by the inverter to increase the MOT, M
OB. These MOT and MOB are connected to a subsequent output buffer not shown.

FIG. 26 shows a first operation example of the main amplifier. Corresponds to the read operation. First, the EQ1 is switched from the low level to the high level, and the equalization of the IO line is released. As a result, the signal of the sense amplifier in the memory cell array appears on the IO line. This signal is the ME
When the Q is switched, the equalization of the main amplifier is released, and when the MA is switched to turn on the current source of the main amplifier, the signal is amplified. This gives 0
A signal appears on KT / KB equalized to V,
This is input to the main amplifier. The main amplifier operates, and a signal having almost full amplitude is obtained at JT / JB as its output. LT / LB is the latch NA1, NA2
Is the output of In response to this, a signal is obtained in MOT / MOB and input to the next stage output buffer. EQ1, MA,
When the MEQ is switched, the main amplifier becomes inactive, and the output MOT / MOB becomes high level.

FIG. 27 shows a second operation example of the main amplifier, which shows a write operation. In this case, the differential amplifier does not operate. First, a signal corresponding to the input data of the chip appears on WI. This data is transferred by switching WE to the IO line whose equalization has been canceled by switching EQ1. In this state, when the WI switches, the data on the IO line also switches. By decoding the YS signal, data can be stored in the sense amplifier via the IO line. If the WE is switched after a series of operations is completed, the IO line is disconnected again from the WI signal.

In the present invention, a signal having a voltage higher than the external power supply voltage is used. For example, in a write operation, a voltage of 3 to 4 V is applied to the drain of the memory cell. To transfer this voltage from the latch to the bit line, a MOS having a voltage of about 7 V applied to the gate is required. When a signal such as 7 V is generated, the control circuit itself operates under an external power supply, so that level conversion is required. FIG. 28 shows an example of a level conversion circuit. In this figure, VC is an external power supply voltage, and VH is a high voltage. NA1 using logical operation as an example
Indicated by. After this passes through the inverter, MP1, MP1
2, MN1, MN2 and an inverter I3. In this circuit, an inverted signal of the VC operation is input to the gates NB and NC of MN1 and MN2. Therefore, one of MN1 and MN2 is completely turned off, and the other is turned on. MP on the VH side
1 and MP2 are connected by crossing each other's gate and drain. MP3 and MN3 are output drivers. The operation of this circuit will be described with reference to FIG. Here, I
It is assumed that the output NA of NA1 goes low when N goes high. When NA goes low, NB goes low and NC goes high, which is its inverted signal. Therefore, MN1 turns off and MN2 turns on. NE tries to go low because MN2 turns on, which causes MP
1 turns on. Then, since MN1 is off, N
D is at the level of VH. Thereby, MP2 is turned off, and NE is completely lowered by MN2. As a result, VH appears on ND and 0V appears on NE,
This means that the system can be converted from the C drive system to the VH drive system.
In response to the output result, the output OUT is driven by the inverter composed of MP3 and MN3. Since NE is 0 V, OUT goes to VH. When IN changes from a high level to a low level, these relations are only reversed. Similarly, the system is converted from the VC drive system to the VH drive system, and NE becomes V
H, and OUT becomes 0V. By using this level conversion circuit, a signal required for the present invention can be generated.

[0039]

Since the sense amplifier is switched between a plurality of bit lines using a switch, the layout pitch is equal to a plurality of layout pitches of the memory cells, and the layout becomes easy. Further, since the sense amplifier and the latch are separately provided, the sense amplifier that mainly performs the analog operation and the latch that mainly performs the digital operation can be independently designed. Further, the sense operation in which the bit line is precharged lower by the threshold voltage from the gate of the MOS inserted between the sense amplifier and the sense amplifier eliminates the need to discharge the bit line having a large parasitic capacitance, thereby achieving a high-speed and stable operation. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a read sequence according to the first embodiment;

FIG. 3 is a diagram illustrating an example of a write sequence according to the first embodiment;

FIG. 4 is a diagram showing a comparison between the latch and the sense amplifier of the first embodiment.

FIG. 5 is a diagram showing a second embodiment of the present invention.

FIG. 6 is a diagram (continued) showing a second embodiment of the present invention.

FIG. 7 is a diagram (continued) showing a second embodiment of the present invention.

FIG. 8 is a diagram (continued) showing the second embodiment of the present invention.

FIG. 9 is a diagram showing a third embodiment of the present invention.

FIG. 10 is a diagram showing a first operation example of the third embodiment.

FIG. 11 is a diagram illustrating a second operation example of the third embodiment.

FIG. 12 is a diagram showing a fourth embodiment of the present invention.

FIG. 13 is a diagram illustrating an operation example of the fourth embodiment.

FIG. 14 is a diagram showing a fifth embodiment of the present invention.

FIG. 15 is a diagram illustrating an operation example of the fifth embodiment.

FIG. 16 is an example of a memory cell array.

FIG. 17 is an example of a voltage applied to a selected memory cell array;

FIG. 18 is a usage example of a peripheral circuit two-level oxide film.

FIG. 19 is a diagram showing a sixth embodiment of the present invention.

FIG. 20 is a diagram illustrating a first operation example of the sixth embodiment;

FIG. 21 is a diagram illustrating a second operation example of the sixth embodiment;

FIG. 22 is a diagram illustrating a third operation example of the sixth embodiment;

FIG. 23 is a diagram showing a seventh embodiment of the present invention.

FIG. 24 is a diagram illustrating an operation example of the seventh embodiment;

FIG. 25 is a diagram illustrating an example of a main amplifier according to the present invention.

FIG. 26 is a diagram illustrating a first operation example of the main amplifier example.

FIG. 27 is a diagram illustrating a second operation example of the main amplifier example.

FIG. 28 is a diagram showing an example of a level conversion circuit used in the present invention.

FIG. 29 is a diagram illustrating an operation example of a level conversion circuit example.

FIG. 30 is a diagram showing a conventional example.

[Explanation of symbols]

D11 to S28, BL ... bit lines, M11 to M116,
MC: memory cell, S11 to S22: sense amplifier, L
111 to L224: write latch, W1, WL: word line, PC, RPC: precharge signal, DDC: discharge signal, TR: bit line sense amplifier connection signal,
SD, SC: memory cell selection signal, VWEL, VWE ...
Memory cell well power and voltage, BS11, BS12 ...
Embedded source lines, BD11, BD12: embedded drain lines, CS: common source line, ABF: address buffer, CLK: control signal generation circuit, DBF: output buffer, MA: main amplifier.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Yusuke Shirono             5-20-1, Josuihoncho, Kodaira-shi, Tokyo             Hitachi, Ltd., Semiconductor Division (72) Inventor Shunichi Saeki             3681 Hayano Mobara-shi, Chiba Hitachi Device             Engineering Co., Ltd. (72) Inventor Naoki Miyamoto             3681 Hayano Mobara-shi, Chiba Hitachi Device             Engineering Co., Ltd. (72) Inventor Katsutaka Kimura             1-280 Higashi-Koigakubo, Kokubunji-shi, Tokyo             Central Research Laboratory, Hitachi, Ltd. F term (reference) 5B025 AA02 AC01 AD04 AD05 AD06                       AD11 AE05

Claims (11)

[Claims] A word line, a plurality of bit lines intersecting the word line, a control gate connected to the word line, a drain connected to each bit line of the plurality of bit lines, and a floating gate. MOS with
In a nonvolatile semiconductor memory device having a plurality of memory cells including transistors, a latch circuit connected to each bit line of the plurality of bit lines, and a latch circuit between each bit line of the plurality of bit lines and the latch circuit Each having its source / drain path
A first switch including an OS transistor; a sense amplifier provided commonly to the plurality of bit lines; and a second switch provided between each bit line of the plurality of bit lines and the sense amplifier. And when the data is read from the selected memory cell, the first switch is turned off, and the second switch between the selected memory cell and the sense amplifier is turned on. A nonvolatile semiconductor memory device. 2. The nonvolatile semiconductor memory device according to claim 1, wherein when data in said latch circuit is written to said plurality of memory cells, said second switch is turned off and said first switch is turned off. A nonvolatile semiconductor memory device wherein a switch is turned on. 3. The nonvolatile semiconductor memory device according to claim 1, wherein a gate length of a MOS transistor in said latch circuit is shorter than a gate length of a MOS transistor in said sense amplifier. Nonvolatile semiconductor memory device. And a floating gate having a word line, a plurality of bit lines intersecting the word line, a control gate connected to the word line, and a drain connected to each bit line of the plurality of bit lines. A plurality of memory cells each including a MOS transistor having a floating gate, and a first latch circuit connected to each odd-numbered bit line of the plurality of bit lines; A first sense amplifier provided in common to the odd-numbered bit lines of the plurality of bit lines; an odd-numbered bit line of the plurality of bit lines;
A first switch provided between each of the plurality of bit lines, a second latch circuit connected to each even-numbered bit line of the plurality of bit lines, and an even-numbered bit of the plurality of bit lines. A second sense amplifier commonly provided to the plurality of bit lines; an even-numbered bit line of the plurality of bit lines;
And a second switch provided between the first and second sense amplifiers. 5. The nonvolatile semiconductor memory device according to claim 4, wherein a third switch is provided between each of odd-numbered bit lines of said plurality of bit lines and said first latch circuit. The even-numbered bit lines of the plurality of bit lines and the second
And a fourth switch respectively provided between the third and fourth latch circuits. When data is read from a selected memory cell of the plurality of memory cells, the third and fourth switches are non-conductive. And the selected memory cell and the first and second memory cells
Wherein the first and second switches between the first and second sense amplifiers are turned on. 6. The nonvolatile semiconductor memory device according to claim 4, wherein said word line is provided between said first latch circuit and said second latch circuit. Nonvolatile semiconductor memory device. 7. The nonvolatile semiconductor memory device according to claim 4, wherein said word line is provided between said first sense amplifier and said second sense amplifier. Nonvolatile semiconductor memory device. 8. A word line, a plurality of bit lines intersecting the word line, a floating gate, a control gate connected to the word line, and a drain connected to each bit line of the plurality of bit lines. MOS connected to
In a nonvolatile semiconductor memory device having a plurality of memory cells including a transistor, a latch circuit connected to each of the plurality of bit lines, a sense amplifier provided commonly to the plurality of bit lines, A first switch provided between each bit line of the plurality of bit lines and the sense amplifier, wherein a gate length of the MOS transistor in the latch circuit is equal to a gate length of the MOS transistor in the sense amplifier. A nonvolatile semiconductor memory device characterized by being shorter than a length. 9. The nonvolatile semiconductor memory device according to claim 8, further comprising a second switch provided between each bit line of said plurality of bit lines and said latch circuit. When data is read from the selected memory cell, the second switch is turned off, and the first switch between the selected memory cell and the sense amplifier is turned on. Non-volatile semiconductor storage device. 10. The nonvolatile semiconductor memory device according to claim 9, wherein when data in said latch circuit is written to said plurality of memory cells, said first switch is turned off and said second switch is turned off. A nonvolatile semiconductor memory device wherein a switch is turned on. 11. A nonvolatile semiconductor memory device having a plurality of bit lines, a latch circuit provided for each of the plurality of bit lines, and one sense amplifier provided for a predetermined number of the plurality of bit lines.