JP2003346486A - Semiconductor memory element and data write method to semiconductor memory element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory element the reliability of which can be improved by preventing deterioration and destruction of a gate oxide film of a memory transistor for a long period of time. <P>SOLUTION: A protection circuit 5 comprising a resistor R, a diode D, and a switch SW is connected to the word line of the memory transistor 1. When data are written in the memory transistor 1, the switch SW is switched off to apply a voltage at write to a write terminal 2. After data write, the switch SW is switched on. Since the voltage applied to the write terminal 2 is clamped by the diode D in this state, a high voltage by static electricity or the like is prevented from being applied to the gate oxide film of the memory transistor 1 even under an environment wherein the high voltage is applied to the write terminal 2 many times so as to maintain the reliability of the semiconductor memory element for a long period of time. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating gate type semiconductor memory device and, more particularly, to a semiconductor memory device and a semiconductor device capable of protecting data from breakdown of an oxide film due to a high voltage such as static electricity and capable of writing data without any trouble. The present invention relates to a method for writing data to a memory element.

[0002]

2. Description of the Related Art Nonvolatile memories such as EPROM and E
In a floating gate type semiconductor memory element such as an EPROM, data is written by injecting electrons into a floating gate through a thin gate oxide film formed on a semiconductor substrate. For electron injection, channel hot electrons or FN (Fo)
(Wler-Nordheim) Tunneling phenomenon or the like. On the other hand, when erasing data, the EPROM is irradiated with ultraviolet light to extract electrons,
In the ROM, the above-described FN tunneling phenomenon via the gate oxide film is used.

[0003] The gate oxide film is destroyed when the amount of charge passing through the gate oxide film exceeds a certain value, resulting in the life of the semiconductor memory device. Therefore, in these floating gate type semiconductor memory devices, the gate oxide film
It is necessary to prevent destruction or deterioration of characteristics due to static electricity during manufacturing and use. On the contrary, a structure that can apply a necessary electric field to the gate oxide film for data writing or erasing is required.

FIG. 4 is a diagram showing a conventional general protection circuit for protecting a gate oxide film from electrostatic breakdown. In the figure,
Floating gate of the memory transistor 1 - capacitor the capacitance between the control gate C _C, are the capacity of the gate oxide film is described as a capacitor C _T. Write terminal (word line) 2 of this memory transistor 1
Is connected to a protection circuit 3 including a diode D. Accordingly, the write terminal 2 can be configured as a voltage higher than the breakdown voltage V _D of the diode D is not applied, and preventing the flow of current to the gate oxide film.

[0005]

Figure 5 [0007] is the I-V characteristic view of the capacitor C _T of the gate oxide film shown in FIG. This characteristic diagram shows a case where electrons are injected into the floating gate by the FN tunneling phenomenon. V _B is the dielectric breakdown voltage of the gate oxide film. V _FN is a voltage at which the current due to the FN tunneling phenomenon starts to increase significantly when the voltage applied to the gate oxide film is increased.

At this time, the breakdown voltage of the diode D is V _D , and the voltage at the time of writing to the write terminal 2 is V
_Assuming that _w is the voltage applied to the gate oxide film (capacitor C _T ) when the voltages V _D and V _W are applied to the writing terminal 2,

The voltage V ₁ at the time of clamping = (C _C / (C _C + C _T )) · V _D (1) The voltage V ₂ at the time of writing = (C _C / (C _C + C _T )) · V _W. (2)

[0008] When an abnormal high voltage is applied to the writing terminal 2 due to static electricity during manufacturing or use, the high voltage is clamped by the diode D, but the gate oxide film momentarily so that the voltage of V ₁ is applied. This voltage V ₁ is
_In order to protect the gate oxide film of _T, the breakdown voltage V _B of the gate oxide film is made lower (V ₁ <V _B ...).
(3)) It is necessary.

On the other hand, when writing data, electrons are injected into the floating gate. At this time, it is necessary to apply a necessary electric field to the gate oxide film. The voltage V _{W at} this time is
A voltage (V ₂ > V _FN ... (4)) equal to or higher than the voltage (V _FN ) at which the current due to FN tunneling shown in FIG.
Must be applied to the gate oxide film.

Further, as the value of the voltage V _W , since a voltage higher than the voltage V _D cannot be applied, V ₂ <V ₁ (5). To summarize the above conditions (3) to (5),

V _FN <V ₂ <V ₁ <V _B (6)

## EQU1 ## These respective voltage values are shown in FIG.
Capacitor C_TIn order to protect the gate oxide film of
Pressure V₁Is better as the value of
And V ₁Is V_FNThe above values will be taken. like this
Under certain conditions, high voltage due to static electricity may
Is applied to the write terminal 2 repeatedly, as shown in FIG.
So capacitor C_TFN tons in the gate oxide film
Current flows due to the tunneling phenomenon, indicating the reliability of the oxide film
Q is an index_bd(Charge to Breakdo
wn) The value of the floating gate
It is possible that electrons are injected into the port and data is written.
There is a potential. Q_bdMeans that the gate oxide film
Is the amount of charge passing through the oxide film. In extreme cases,
In some cases, the gate oxide film may cause dielectric breakdown.

In the above description, an example is described in which the FN tunneling phenomenon is used to inject electrons into the floating gate, but the same applies to the case where the channel hot electron phenomenon is used. That is, when a voltage electron injection floating gate F by channel hot electron begins to occur and V _HOT, since V _FN in the formula (6) corresponds to the V _HOT, the gate oxide film current due to channel hot electron flows Cause similar problems.

FIG. 6 is a diagram showing another conventional protection circuit (disclosed in Japanese Patent Application Laid-Open No. 7-244991) for protecting a gate oxide film from electrostatic breakdown. As shown, the protective circuit 4, a diode D, to connect the MOS capacitor C _P directly, those formed by connected to the write terminal 2, before the current flows through the gate oxide film of the capacitor C _T by flowing a tunnel current to the MOS capacitor C _P of the protection circuit 4 to a configuration for clamping the voltage of the write terminal 2. In this circuit configuration, when a voltage is applied to the write terminal 2 and the voltage applied to the capacitor C _P is V _P and the diode breakdown voltage is V _D as in FIG. 4, V _P + V _D becomes Since it corresponds to V _D in FIG. 4,
The same operation as in FIG. 4 can be obtained.

However, even when the protection circuit 4 shown in FIG. 6 is used, a high voltage due to static electricity is applied to the write terminal 2 for a long time or many times as in the configuration of FIG. In the environment, the memory transistor 1
Could not be sufficiently protected.
The above-described conventional protection circuits 3 and 4 cannot prevent a current from flowing through the gate oxide film due to static electricity or the like during manufacturing or use, reduce the _Qbd value of the gate oxide film, 1 life improvement, and
The number of times of writing and erasing could not be improved.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has been developed for a semiconductor memory device and a semiconductor memory device capable of preventing deterioration and destruction of a gate oxide film of a memory transistor for a long time and improving reliability. It is an object of the present invention to provide a data writing method.

[0017]

In order to achieve the above object, a semiconductor memory device according to the present invention has a protection circuit in which a switch and constant voltage means are connected in series to a word line for a memory transistor such as a nonvolatile memory. It is characterized by having done. The switch is configured using a MOS transistor or the like, and is turned off when data is written to the memory transistor, and is turned on when data is not written. This switch switching can be performed based on the input of the write enable signal, and can be realized by, for example, switching a MOS transistor via a logic circuit.

According to the present invention, at the time of writing data to the memory transistor, the switch is turned off so that a voltage required for writing can be applied to the writing terminal. Also, except during writing, the switch is switched on and held, and the voltage applied to the writing terminal is clamped by using a constant voltage means to prevent a high voltage from being applied to the gate oxide film of the memory transistor. Thus, even in an environment where an abnormal high voltage due to static electricity or the like is applied to the writing terminal several times, the reliability of the semiconductor memory element can be maintained for a long time.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Preferred embodiments of a semiconductor memory device according to the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention. Memory transistor 1, the conventional same floating gate - indicates the capacitance between the control gate capacitors C _C, the capacitance of the gate oxide film as the capacitor C _T. The write terminal (word line) 2 is connected to a protection circuit 5 composed of a resistor R, a diode D as a constant voltage means, and a switch SW connected in series. One end of the resistor R is connected to the write terminal 2 and the other end is connected to the cathode of the diode D. The anode of the diode D is connected to a reference terminal (ground) via a switch SW. A semiconductor switch can be used as the switch SW.

At the time of writing data to the memory transistor 1, the switch SW of the protection circuit 5 is switched to an off state in which the switch SW is opened, and a write voltage V _W is applied to the write terminal 2. Thus, the capacitor C _T of the memory transistor 1,

V _T = (C _C / (C _C + C _T )) · V _W (7)

Voltage is applied. The application of the voltage V _T, through the gate oxide film, a channel hot electrons or FN (Fowler-Nordh
eim) Electrons are injected into the floating gate due to a tunneling phenomenon or the like.

On the other hand, except when data is written to the memory transistor 1, the switch SW of the protection circuit 5 is switched to the closed ON state. Diode D has breakdown voltage V _D
By configuring the protection circuit 5 by connecting the switch SW and the diode D in series as described above, the constraint of the equation (6) can be eliminated. Therefore, based on only the above-described equations (3) and (4), the voltages V ₁ ,
It becomes possible to determine the voltage V ₂ at the time of writing. That is,
Since the breakdown voltage V _D of the diode D can be set low, it is possible to prevent a current from flowing to the gate oxide film of the memory transistor 1 due to static electricity or the like during operation of the protection circuit 5, prevent the gate oxide film from being broken, and prevent the gate oxide film This makes it possible to prevent the _Qbd value, which is reliability, from decreasing.

The protection circuit 5 writes data,
And the operation state is clearly changed in accordance with the non-writing time. In an environment where the protection circuit 5 is activated at the time of non-writing, an abnormally high voltage due to static electricity or the like is applied to the writing terminal 2 several times. However, it has made it possible to maintain the reliability of semiconductor memory devices for a long time.
For data writing, it is possible to apply regardless of the voltage V _W necessary for data write to the breakdown voltage V _D. As described above, according to the present invention, both the protection of the semiconductor memory element and the restriction on the voltage value required for data writing can be eased and easily performed.

Embodiment 2 FIG. 2 is a circuit diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention. This protection circuit 6 includes a resistor R and a diode D as in the first embodiment, and the function of the switch SW is
This is configured using the transistor 7. The MOS transistor 7 is an N-channel MOS in the illustrated example.
Using a FET, connecting the source-drain in series between the diode D and ground, and controlling and switching the gate voltage. In such a configuration, the same operation and effect as in the first embodiment can be obtained.

Embodiment 3 FIG. 3 is a circuit diagram showing a configuration of a semiconductor memory device according to a third embodiment of the present invention. The protection circuit 8 is configured to switch the MOS transistor 7 described in the second embodiment based on a write enable signal. As shown, MO
The gate of the S transistor 7 is connected to a write enable terminal 10 via a logic circuit 9.

The logic circuit 9 can be incorporated in a package constituting a semiconductor memory device. The logic circuit 9 switches the MOS transistor 7 to an off state when a write enable signal is input to the write enable terminal 10 when writing data to the memory transistor 1, and switches the protection circuit 8 to an off state corresponding to FIG. . On the other hand, except when data is written to the memory transistor 1, the protection circuit 8 is turned on. As described above, the logic circuit 9 may have a simple configuration in which the off signal is sent to the MOS transistor 7 at the time of writing and the on signal is sent at times other than at the time of writing. Even when the logic circuit 9 is added, There is no increase in the circuit scale of the entire device.

According to the above configuration, the same operation and effect as those of the first and second embodiments can be obtained, and the protection circuit 8 can be switched on and off in accordance with data writing.

The resistors R, the diodes D, the MOS transistors 7 and the logic circuit 9 constituting the protection circuits 5, 6 and 8 described in the above embodiments constitute a semiconductor memory element together with the memory transistor 1. Formed on the same semiconductor substrate. Also,
No special process is required for adding these circuit elements, and they can be obtained by the same manufacturing steps as in the prior art.

[0030]

According to the present invention, a protection circuit in which a switch and a constant voltage means are connected in series to a memory transistor word line is connected, and the protection circuit is turned off when data is written to the memory transistor by switching the switch. At other times, the protection circuit is turned on, preventing the gate oxide film from being damaged and deteriorated for a long time even in an environment where abnormal high voltage due to static electricity or the like is applied several times to the write terminal. And the reliability can be improved.

The switches constituting the protection circuit include M
By using an OS transistor or the like and utilizing a write enable signal, the operation of the protection circuit can be easily switched according to the data write timing.
In addition, diodes and MOS transistors that constitute a protection circuit can be formed on the same semiconductor substrate that constitutes a semiconductor memory element with almost no increase in circuit scale, and can be manufactured by existing manufacturing processes. Manufacturing can be facilitated, and high reliability can be obtained at low cost.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a general protection circuit for protecting a gate oxide film from electrostatic breakdown.

[5] I of the capacitor C _T of the gate oxide film shown in FIG. 4
It is a -V characteristic view.

FIG. 6 is a diagram showing another protection circuit for protecting a gate oxide film from electrostatic breakdown.

[Explanation of symbols]

1 memory transistor 2 writing terminal (word line) 5, 6, 8 protection circuit 7 MOS transistor 9 logic circuit 10 capacitor D diode (constant voltage unit) of the write enable terminal C _T gate oxide film R resistor SW switch

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/10 481 G11C 17/00 633Z 27/115 29/788 29/792 F term (Reference) 5B025 AA01 AB01 AD03 AD14 AE08 5F038 BH02 BH05 BH07 BH13 EZ20 5F083 EP02 ER02 ER03 ER14 ER21 ER25 GA14 GA21 LA10 PR42 PR52 5F101 BA01 BB02 BC02 BC11 BE07 BE08 BE17

Claims (9)

[Claims] 1. A semiconductor memory device comprising: a protection circuit in which a switch and a constant voltage means are connected in series between a data writing terminal for a memory transistor and a reference terminal. 2. The semiconductor memory device according to claim 1, wherein the memory transistor is a nonvolatile memory. 3. The semiconductor memory device according to claim 1, wherein the switch is turned off when data is written to the memory transistor, and is turned on except when the data is written. . 4. The semiconductor memory device according to claim 1, wherein said switch comprises a semiconductor switch. 5. The semiconductor memory device according to claim 1, wherein said switch is configured using a MOS transistor. 6. A write enable terminal to which a write enable signal is input when data is written to the memory transistor, and a control to switch the switch to an off state when a write enable signal is input to the write enable terminal. The semiconductor memory device according to claim 1, further comprising: a logic circuit. 7. A method for writing data to a semiconductor memory device comprising a protection circuit in which a switch and a constant voltage means are connected in series between a data writing terminal for a memory transistor and a reference terminal, the data writing terminal comprising: A semiconductor memory, comprising: a switch switching step of switching the switch to an off state when writing data from the memory; and a data writing step of writing data from the data writing terminal after the switch switching step. A method of writing data to the element. 8. A protection circuit comprising a switch and a constant voltage means connected in series between a data writing terminal for a memory transistor and a reference terminal, and a write enable signal inputted when writing data to the memory transistor. A method for writing data to a semiconductor memory device, comprising: an enable terminal; and a switch switching step of switching the switch to an off state when the write enable signal is input to the enable terminal. A data writing step of writing data from the data writing terminal later. 9. The method for writing data to a semiconductor memory device according to claim 7, further comprising: a switch holding step of maintaining the switch in an on state after writing data in the data writing step. .