JP2003346340A - Light source drive unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the occurrence of problems, such as increase in cost or deterioration of performance for the requests, such as speed up of recording information, and recording information at high density in recording medium by suppressing a deviation from a desired value of an optical modulation waveform caused by distortion, skew or the like of the optical modulation control signal wave form. <P>SOLUTION: A irradiation level of a light source LD is controlled, by splitting a LD modulation signal WSP indicating transition timing of an irradiation level of a light source LD into an LD modulation signal WSP1, which is the first half of the multi-pulse string and an LD modulation signal WSP2, which is the latter half of the multi-pulse string, as shown in (e-1) and (e-2) respectively (the boundary line of the LD modulation signal WSP1 and the LD modulation signal WSP2 indicates the changing point of time for the irradiation level of the light source LD) and supplying them to a sequencer 301. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information recording / reproducing apparatus such as a CD-R drive, a CD-RW drive, a DVD-R drive, a DVD-RW drive, a DVD + RW drive, and a DVD-RAM drive. The present invention relates to a light source driving device that is mounted on a light source and that drives and controls an optical modulation waveform that has been converted into a multi-level level and a multi-pulse.

[0002]

2. Description of the Related Art Conventionally, in an optical disc apparatus for recording information on a recordable optical disc (information recording medium) by light modulation of a laser beam emitted from a light source, one type of optical disc apparatus is known.
Multi-pulse and multi-level light modulation waveforms (for example, see the light modulation waveform in FIG. 4 (c)) for control of beam overwrite technology and recording mark shape control for higher density. In order to use this technology, it is necessary to switch a plurality of currents in a light source driving unit (hereinafter also referred to as an “LD driver”), and as a result, the number of input signal lines increases. . In addition, in order to realize high-speed recording and high-density recording on an optical disk, it is necessary to further increase the data transfer rate in the future, further refine the pulse division width, and further increase the number of power levels. Has been requested.

Further, since the pickup on which the light source is mounted is movable in the radial direction of the optical disk (this operation is called "seek operation"), the pickup and the circuit board on which the signal processing unit and the like are mounted are flexible. Sex circuit (Flex
In general, the connection is made with a bendable substrate called an IPrint Print Circuit (FPC) substrate. An LD driver is arranged near a light source (LD) mounted on a pickup, and the LD driver is provided from the signal control unit. L
The wiring up to the D driver is made using the FPC board. However, it is inevitable that the length of the FPC board for supplying the optical modulation control signal is inevitable to some extent. A shift in the switch timing of the drive current occurs, and when the switches are simultaneously switched, the waveform is disturbed, so that the light source cannot emit laser light with a desired light waveform (see FIG. 13).

[0004] As a result, the accuracy of the mark shape and mark position formed on the optical disc is impaired, and as a result, a data error is caused. In addition, especially when two switches are turned on at the same time, a temporary over-emission state occurs,
There is even a risk of breaking the light source LD. Furthermore, FP
The problem of unnecessary radiation from the C substrate occurs, which causes noise. In order to solve such a problem, a current of a plurality of current sources is supplied to a light source (LD) via a switch.
Driving means for restoring a driving waveform (optical modulation waveform) for driving the LD in accordance with a binary recording signal to be recorded on an optical disc (information recording medium) and controlling the switching means And a light source driving device provided in the same laser driving integrated circuit (for example, Japanese Patent Application Laid-Open No. 11-28).
No. 3249) has been proposed.

[0005]

However, in the conventional light source driving apparatus as described above, if further high-speed information recording and high-density recording on an optical disk are required in the future, the driving waveform restoring means (optical modulation) is required. Control signal generator)
Since a higher speed operation and higher integration of a laser driving integrated circuit are required, a fine CMOS process is suitable.
On the other hand, since an LD having an operating voltage of about 1 to several V is connected to the LD driving section, a high withstand voltage process (for example, 5
V or 3.3 V). However, it is usually difficult to increase the breakdown voltage in a fine CMOS process (for example, 1.8 in a 0.18 μm CMOS process).
(There is only a withstand voltage of about V), so that it is difficult to realize high-speed operation, or there are problems such as a large increase in cost, an increase in power consumption, and an increase in the size of an integrated circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and suppresses a deviation of an optical modulation waveform from a desired value due to a distortion or skew of an optical modulation control signal waveform, thereby increasing the speed of information recording. It is an object of the present invention to realize a high-density recording on an information recording medium without causing problems such as an increase in cost and a decrease in performance.

[0007]

In order to achieve the above object, the present invention provides the following light source driving devices (1) to (11). (1) In a light source driving device for causing a light source to emit light at a multi-level irradiation level, a state corresponding to the irradiation level is controlled, and a first modulation indicating a part of a change timing of the irradiation level of the light source. The transition of the state is controlled based on the signal and the second modulation signal indicating the remaining part of the change timing of the irradiation level of the light source and a preset transition rule, and corresponds to the state selected by the control. State control means for generating modulated data, and modulation means for modulating the drive current of the light source based on the modulated data generated by the state control means, the first modulation signal and the second modulation signal. Light source driving device provided.

(2) In a light source driving device which emits light at a multi-level irradiation level and transmits one information by a plurality of pulse trains, a state corresponding to the irradiation level is controlled. The first modulation signal indicating the change timing of the first half pulse and the second modulation signal indicating the change timing of the second half pulse of the pulse train, and controlling the transition of the state based on a preset transition rule, State control means for generating modulation data corresponding to the state selected by the control; and the light source based on the modulation data generated by the state control means, the first modulation signal, and the second modulation signal. A light source driving device provided with a modulating means for modulating the driving current of the light source.

(3) In a light source driving device which emits light at a multi-level irradiation level and transmits one information by a plurality of pulse trains, a state corresponding to the irradiation level is controlled. The first modulation signal indicating the change timing of the first half pulse and the second half pulse, the second modulation signal indicating the change timing of the middle pulse of the pulse train, and the transition of the state based on a preset transition rule. State control means for controlling the control, and generates modulation data corresponding to the state selected by the control,
A light source driving device provided with a modulation means for modulating a driving current of the light source based on the modulation data generated by the state control means and the first modulation signal and the second modulation signal.

(4) In the light source driving device according to any one of (1) to (3), the state control means controls the three state groups respectively including a part of the states. A state control unit for generating first to third modulation data, wherein the modulation unit performs the first to third modulation data in accordance with a combination of the first modulation signal and the second modulation signal. A light source driving device which is means for selecting third modulation data and modulating the driving current of the light source. (5) In the light source driving device according to any one of (1) to (3), a pulse instructing a transition of the state is inserted into at least one of the first modulation signal and the second modulation signal. Light source driving device.

(6) In the light source driving device according to any one of (1) to (3), light source control means for sampling a predetermined irradiation level of the light source and controlling the light amount of the light source is provided, A light source driving device configured to insert a pulse indicating a timing for sampling the predetermined irradiation level into at least one of the modulation signal and the second modulation signal. (7) In the light source driving device according to any one of (1) to (3), light source control means for sampling a predetermined irradiation level of the light source and controlling the light amount of the light source is provided, and the first modulation signal or A light source driving device which instructs at least one of the second modulation signals to change the state and inserts a pulse indicating a timing for sampling the predetermined irradiation level.

(8) In the light source driving device according to any one of (1) to (3), a plurality of pulses are inserted into at least one of the first modulation signal and the second modulation signal. A light source driving device configured to transfer information based on the presence or absence of a pulse or the number of pulses. (9) In the light source driving device according to any one of (1) to (3), a plurality of pulses are inserted into at least one of the first modulation signal and the second modulation signal, and the pulses are inserted. A light source driving device provided with command demodulation means for demodulating a command signal transmitted in synchronization with a modulation signal.

(10) In the light source driving device according to any one of (1) to (3), a delay adjusting means for adjusting a delay amount of at least one of the first modulation signal and the second modulation signal is provided. Light source driving device provided. (11) In the light source driving device according to any one of (1) to (3), a modulation signal generation unit that adjusts and outputs a delay amount of at least one of the first modulation signal and the second modulation signal. Light source drive device provided with.

[0014]

Embodiments of the present invention will be specifically described below with reference to the drawings. First, an overall configuration and an operation outline of an information recording / reproducing device including a light source driving device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an overall configuration of an information recording / reproducing apparatus including a light source driving device according to one embodiment of the present invention. In FIG. 1, an information recording medium 100 includes an optical disc such as a CD-ROM or a DVD-ROM in which information to be reproduced is recorded in advance,
Alternatively, a CD-R, a CD-RW, a DVD-R, or a DV in which no information is recorded and a user can arbitrarily record new information.
It is an optical disk such as a D-RAM, MD, or MO.

The pickup 101 irradiates the information recording medium 100 with light emitted from a light source (for example, a semiconductor laser (LD)) 102 to record information, or receives reflected light from the information recording medium 100 and receives light. A light source 102, a light source driving unit (known in the art, not shown) for driving the light source 102, and a light receiving unit 103 for receiving reflected light and converting it into a light receiving signal are arranged. .
The pickup 101 is also provided with a monitor light receiving unit (also well-known, not shown) for monitoring a part of the light emitted from the light source 102, and based on a monitor signal output from the monitor light receiving unit. Control fluctuations.

Further, a tilt detection light-receiving unit (also well-known and not shown) for detecting the inclination of the information recording medium 100 with respect to the irradiation light (referred to as “tilt”) may be provided. Furthermore, in the case of an information recording / reproducing device corresponding to a plurality of types of information recording media in which different media formats are defined (for example, a device compatible with both DVD and CD), a light source having a wavelength suitable for each information recording medium is provided. In some cases, a light receiving unit or a monitor light receiving unit that receives the reflected light from the information recording medium when each light source emits light may be separately provided.

The signal processing unit 104 includes a pickup 101
Light-receiving signals from various light-receiving units arranged in the memory are input, and various signal processes are performed. For example, control is performed such that information is reproduced from the received light signal, and light is always irradiated within a predetermined error with respect to fluctuations such as surface deflection and track radial deflection due to rotation of the information recording medium 100 (focus servo). A servo error signal is generated from the received light signal to perform the control and track servo control, and the pickup 101 is controlled according to the servo error signal. Further, the information to be recorded is modulated according to a predetermined rule, and is output as a recording signal to the light source 102 (or the light source driving unit).
Output light quantity control is performed.

The rotation drive unit 105 is used for the information recording medium 100.
The signal processing unit 104 controls the rotation speed (spindle servo control). CLV
When performing the rotation control, a rotation control signal embedded in the information recording medium 100 is detected via the pickup 101 in order to perform the rotation control more accurately, and the rotation control is performed based on the rotation control signal. As the rotation control signal, for example, in a reproduction information recording medium or the like, a synchronization signal arranged at a predetermined interval in recorded information, or in a recordable information recording medium, a wobble in which a recording track meanders at a predetermined frequency is used.

The controller 106 controls the entire apparatus by transferring recording / reproducing information to / from the host computer and performing command communication. The pickup 101 is movable in the radial direction of the information recording medium (this operation is referred to as “seek operation”).
), A circuit board on which the pickup 101 and the signal processing unit 104 are mounted is a flexible printed circuit (Flexible Print Circuit).
It is generally connected by a board (or cable) called a uit (FPC) board (or cable), and components mounted on the pickup 101 such as the light source 102 and the light receiving unit 103 are mounted on the FPC board. There are many.

Next, the internal configuration and operation of the signal processing section 104 of the information recording / reproducing apparatus will be described. FIG.
FIG. 2 is a block diagram showing an internal configuration of the signal processing unit 104 shown in FIG. The signal processing unit 104 according to the present embodiment includes two light sources LD1 and LD2 as the light sources (LD) 102 in order to support information recording media of different formats.
And the light receiving units PD1 to PD1 as the light receiving unit 103.
A PD 5 is provided, and a part of the irradiation light from the light sources LD1 and LD2 is monitored by the light receiving units PD2 and PD5, respectively.

The light receiving unit PD1 receives the reflected light from the information recording medium when the light source LD1 is irradiated, and the light receiving unit PD4 receives the reflected light from the information recording medium when the light source LD2 is irradiated. The light receiving unit PD3 is a light receiving unit for detecting a tilt amount. The light receiving units PD1, PD3, and PD4 receive light with the divided light receiving elements divided into a plurality. Note that, depending on the pickup, the light emitted from the light sources LD1 and LD2 may be monitored by the same light receiving unit. Similarly, the light receiving unit that receives the reflected light from the information recording medium may be the same.

The light receiving signal processing unit 2 includes light receiving units PD1 and PD
3 and the respective light receiving signals output from the PD 4 are input, and processing such as offset adjustment and gain adjustment of each light receiving signal is performed. The servo signal calculation processing unit 13 generates a servo error signal from each light reception signal supplied from the light reception signal processing unit 2.
At the same time, a servo error signal generated by performing offset adjustment and gain adjustment is supplied to the servo processor 14.
The RF selection unit 4 receives the light receiving signals output from the light receiving units PD1 and PD4, and supplies necessary signals to a subsequent circuit by performing calculations such as selection or partial addition and subtraction.

The wobble signal generator 6 detects a wobble preformatted on a recordable information recording medium. The wobble signal processing unit 15 extracts a binarized wobble signal from the signal output from the wobble signal generation unit 6 and supplies it to the WCK generation unit 17 and the rotation control unit 18.
Also, it demodulates address information modulated into wobbles according to a predetermined rule for each information recording medium and supplies the demodulated address information to the controller 19.

The RF signal processing section / PLL section 16 receives the reproduced RF signal input from the RF selecting section 4 by the RF signal processing section.
A binary RF signal is generated from the signal, and demodulation is performed in accordance with the modulation scheme rules of the information recording medium being reproduced. Also PLL
A reproduction clock is extracted from the binary RF signal by a unit (PLL circuit). The demodulated data is supplied to the controller 19. Further, a rotation control signal is extracted by a synchronization signal inserted at a predetermined interval into the binary RF signal, and the rotation control unit 1
8 The rotation control unit 18 generates a spindle error signal for performing rotation control from a signal input from the wobble signal processing unit 15 or the RF signal processing unit / PLL unit 16 and supplies the spindle error signal to the servo processor 14. When the information recording medium is rotated at a constant angular velocity (CAV), a signal indicating the disk rotation (also known and not shown) output from a rotation control drive unit (known and not shown) is output. To generate a spindle error signal.

The servo processor 14 includes the controller 1
Based on the command from the controller 9, a servo control signal is generated from various input servo error signals and output to the servo driver 20. The servo driver 20 generates a servo drive signal based on the input servo control signal. Each drive unit performs a servo control operation according to the supplied servo drive signal. Here, focus control, track control, seek control, spindle control, and tilt control are performed.

The WCK generation unit 17 generates a recording clock signal WCK based on the binarized wobble signal supplied from the wobble signal processing unit 15, and
Is supplied to each part of the controller 19. During recording, recording data is generated based on the recording clock signal WCK. The LD modulation signal generation unit 10 or the like functions as a modulation signal generation unit that adjusts and outputs a delay amount of at least one of the first modulation signal and the second modulation signal. During recording, the recording data signal Wda is synchronized with the recording clock signal WCK from the controller 19.
ta is supplied to the LD modulation signal generation unit 10. In the recording data signal Wdata, information to be recorded is modulated according to a predetermined rule.

The LD modulation signal generator 10 is an LD for modulating the light source LD1 or LD2 from the recording clock signal WCK input from the WCK generator 17 and the recording data signal Wdata input from the controller 19.
A modulation signal is generated and supplied to the LD drive unit 12. The LD control unit 9 receives a monitor light receiving signal from the light receiving unit PD2 or the light receiving unit PD5, and sends the received light signal to the LD driving unit 12 based on the monitor light receiving signal so that the amount of light emitted from the light sources LD1 and LD2 becomes a desired value. Supply an LD control signal (so-called APC (Automatic Power)
Control). LD drive unit 12
Based on the LD control signal input from the D control unit 9 and the LD modulation signal input from the LD modulation signal generation unit 10, the light source LD1 or LD2 is driven by current to emit light. In addition, the controller 19 outputs control signals of each unit.

Next, the LD controller 9 and the LD driver 1
Two detailed embodiments will be described. FIG. 3 is a configuration diagram of the LD drive integrated circuit 1 in which the LD control unit 9 and the LD drive unit 12 shown in FIG. 2 are integrated. FIG. 4 shows the LD shown in FIG.
FIG. 3 is a waveform chart showing an example of an output signal of each section of the drive integrated circuit 1. The LD drive integrated circuit 1 shown in FIG. 3 is arranged near the light sources LD1 and LD2 to be driven, and is mounted on the pickup 101. On the other hand, LD drive integrated circuit 1
Modulation signal generation unit 1 that supplies an LD modulation signal WSP to the
0 is mounted on a circuit board together with other signal processing units, and a signal line connecting them is transmitted on the FPC board.

Further, the LD modulation signal generator 10 generates the recording data signal Wdat based on the recording clock signal WCK.
a, the LD modulation signal WSP as shown in FIG.
And a state signal STE as shown in (e-1) of FIG.
Generate N. In FIG. 4, the signal W is shown for simplicity of illustration.
The illustration of the SP and STEN with respect to the recording data Wdata is neglected (usually, a predetermined clock delay occurs due to the generation circuit). At this time, the LD modulation signal WSP
It is assumed that pulse width control optimal for a required information recording medium has been performed. Further, a command signal STCMD is also generated.

The LD drive integrated circuit 1 converts a state signal STEN and a command signal STCMD supplied from the LD modulation signal generation unit 10 into a mode control signal SeqMode indicating an LD irradiation level and an irradiation mode, and a command decoder (CMDDecoder) 22. And LD
LD modulation signal WSP supplied from modulation signal generator 10
And the state signal STEN and the mode control signal SeqMo
A sequencer (Sequencer) 21 that controls the LD irradiation level based on de, and a modulator (Data-Modulation) that generates an LD modulation current Imod based on the modulation data DmodL and DmodH supplied from the sequencer 21 and the modulation signal MOD. 23.

Further, a PD amplifier (PD-AM) that performs offset adjustment and gain adjustment by inputting a monitor light receiving signal from a monitor light receiving unit that monitors a part of the light emitted from the light source.
P) 26 and a reference signal Itarg generated from a target level signal Dtarget supplied from the sequencer 21 by a monitor signal Imon supplied from the PD amplifier 26.
bias current control unit (Bias-Control) 27 that controls bias current Iapc so as to match with et.
And the bias current I output from the bias current controller 27.
a bias current selector (MUX) 29 for selecting a bias and an externally supplied bias current Iext to output a current Ibias; A differential quantum efficiency control unit (η-Control) 28 that detects the efficiency η and controls the scale Scale of the LD modulation current according to the detection result is also provided. The bias current control unit 27 functions as the light source control unit.

Further, the high-frequency superimposed signal and the offset current Ihfmofs applied to the bias current during the high-frequency superimposition
High-frequency modulator (HF-Modulatio
n) 30, bias current Ibias and modulation current Imo
d to add the high frequency superimposed offset current Ihfmofs
And a light source LD1 or a light source LD amplifying the current supplied from the current adder 24.
And a control unit 33 that receives a control command supplied from the controller 19 (or via the LD modulation signal generation unit 10) and supplies a control signal to each unit. I have.

The signal waveform of each part shown in FIG. 4 is an example, and the information recording medium assumed here is a phase-change recording medium (for example, an optical disk such as a CD-RW or DVD-RW). The recording clock signal WCK shown in FIG.
Also, based on the recording data signal Wdata shown in FIG. 4B, the light source LD has an optical modulation waveform as shown in FIG.
Is emitted to form a recording mark shown in FIG. In the phase change type information recording medium, a recording mark is generally formed by a ternary multi-pulse of a write power Pw, an erase power Pe, and a bottom power Pb. At this time, accurate recording is performed by precisely controlling the recording power level and the pulse width and pulse interval of each pulse. Further, in the present embodiment, as shown by broken lines (i), (ii), and (iii) in (c) of FIG. The power can be set.

Generally, when a mark is formed depending on the information recording medium or its recording linear velocity, the edge of the mark may be variously affected by the adjacent space length due to thermal influence on the medium by the adjacent space length. is there. In order to avoid this, conventionally, each pulse width of the optical modulation waveform is changed in consideration of the adjacent space length. If the power can be changed in consideration of the adjacent space length as in this embodiment, the amount of heat applied to the medium is equivalent to performing pulse width correction according to the adjacent space length. This is substantially equivalent to subdivision of the pulse width control resolution, which is suitable for high-speed recording.

Here, the light source LD to be driven / controlled will be described before the detailed description of each part. FIG. 8 is a diagram illustrating an example of the drive current-light output characteristics. Usually, light source L
The optical output Po with respect to the drive current ILD of D can be approximated based on the following equation (1). Here, η: differential quantum efficiency, Ith: threshold current.

[0036]

## EQU1 ## Po = η. (ILD-Ith)

In order to obtain a desired optical modulation waveform P (FIG. 8B), when the LD drive current ILD is the sum of the bias current Ib and the modulation current Im (Ib + Im), the bias current Ib is equal to the threshold current. Approximately equal to Ith and the modulation current Im
Can be obtained by driving a current such that P = η · Im as shown in FIG. However, in general, the threshold current Ith and
Since the differential quantum efficiency η fluctuates not only due to variations among individuals, but also due to temperature changes, in order to constantly obtain a desired optical modulation waveform P, the bias current Ib along with fluctuations in the threshold current Ith and the differential quantum efficiency η And the modulation current Im. For example, when the threshold current changes to Ith 'and the differential quantum efficiency changes to η' as shown in (ii) of FIG. 8, in order to obtain a desired optical modulation waveform P, the bias current Ib 'is changed to Ith'. The modulation current Im 'may be controlled so that P = [eta]'. Im 'as shown in FIG.

In the LD drive integrated circuit 1 shown in FIG. 3, the bias current control section 27 mainly performs a bias current control function, and the differential quantum efficiency control section 28 mainly performs a modulation current control function.

The operation and detailed configuration of each section of the LD drive integrated circuit 1 shown in FIG. 3 will be described below. [Sequencer] The sequencer 21 outputs the LD modulation signal WSP
And the state signal STEN to control the irradiation level of the light source LD. FIG. 5 is a state transition diagram of the sequencer 21 shown in FIG. Each state corresponds to the irradiation level of the light source LD, and each of the state machines SMa and SMb operates independently. Then, the current states state0 and stat of each of the SMa and SMb state machines, respectively.
The modulation data DmodL and DmodH are output according to e1.

That is, modulation data corresponding to each state is set in advance, and modulation data corresponding to the current state of each state machine is selectively output. In addition, an LD modulation signal WSP is output as a modulation signal MOD during recording, and a low signal is output as a modulation signal MOD during reproduction.
In FIG. 3, the modulation signal MOD is supplied to the modulation unit 23 via the multiplexer MUX65.
Here, it is assumed that the MUX 65 is selectively outputting the modulation signal MOD.

In the modulation section 23 at the next stage, the modulation signal MO
When D is low, the modulation data DmodL is selected, and when D is high, the modulation data DmodH is selected. Therefore, each state in SMa is the LD modulation signal WSP.
Corresponds to the irradiation level when low, and each state in SMb corresponds to the irradiation level when WSP is high. For example, when state0 = Pb, the modulation signal MO
When D = Low, the irradiation level of the light source LD becomes the bottom power Pb, and when state1 = Pmp and the modulation signal MOD = High, the irradiation level of the light source LD becomes the write power Pw.

The state transition of the state machine SMa is performed at the rising edge of the LD modulation signal WSP, and the state transition of the state machine SMb is performed at the falling edge of the LD modulation signal WSP. That is,
Since the state transition (modulation data change) is performed when the output of the modulation data is not selected, the irradiation level of the light source LD does not change even when the modulation data changes.

The first pulse Ptp and the last pulse Pl
Each modulation data corresponding to p or the final bottom pulse power Pcl can be dynamically changed according to a recording data pattern or the like. That is, a plurality of preset modulation data (for example, Ptp is quaternary, Ptp0 to Pt
p3) is selected by the power selection signal PwrSel supplied from the command decoder 22. The power level to be selected is specified by the command signal STCMD, and the command decoder 22 controls the power selection signal Pw.
Converted to rSel.

Next, transition conditions of each state machine will be described. (G-1) and (g-2) in FIG. 4 show an example of the state transition, and the change time of the LD modulation signal WSP ((f) in FIG. 4) is set to t0 to t27 as shown in the figure. The state signal STEN2 is obtained by re-taking the state signal STEN at the falling edge of the LD modulation signal WSP, and the state machine SMa performs a state transition in accordance with this. As a result, W serving as a reference for state transition in the state machine SMa
Since the data determination time of the state signal STEN2 can be sufficiently secured with respect to the rise of the SP, a stable operation can be performed.

* State machine SMa Hereinafter, unless otherwise specified, transition is made in synchronization with the rise of the LD modulation signal WSP. {State Pr} Initial state. During playback (write signal R / W = 0
(At the time of (Read)) stays here. Start recording (R /
The state transitions to state Pe at (W rise). This transition may not be synchronized with the LD modulation signal WSP. {State Pe} State signal STEN2 = high (High)
In h), the state transits to the next state. Normally, the state transitions to the state Pb (for example, time t3), but sometimes transitions to the state Pcl due to the special condition (A) described later (for example, time t2).
5). At the end of recording (R / W falling), the state transits to the state Pr.

{State Pb} STEN2 = Low (Low)
To transition to the next state. In the waveform example of FIG. 4, the state transits to the state Pcl (for example, time t7). Further, the state transits to the state Pe depending on the mode control signal SeqMode. Transits to {state Pcl} state Pe (for example, at time t
9). The return to the state Pr (reproduction mode) is performed by R /
After W = Raed, the transition may be made after first returning to the state Pe, or the transition may be forcibly made by R / W = Read.

* State machine SMb Unless otherwise specified, transition is made in synchronization with the falling edge of LD modulation signal WSP. {State Pe} Initial state. When the state signal STEN is high (High), the state transits to the state Ptp (for example, at time t).
2). {State Ptp} State signal STEN = high (High
At the time of h), the state transits to the state Pmp (time t4). Also,
When the state signal STEN is low, the state Pl
The state transits to p (time t18). Special condition (A) described later
May transition to the state Pe.

{State Pmp} When the state signal STEN is low, the state transits to the state Plp (at time t).
6). If the state signal STEN is high, the signal stays here. The state transits to {state Plp} state Pe (time t8). In the present embodiment, the transition mode of the state machine can be dynamically changed via the command decoder 22.
For example, in the case of generating a waveform (Ptp → Pcl) surrounded by a dashed-dotted line frame (A) in FIG. What is necessary is just to make a transition. The initialization of each state machine may be performed by issuing a command via the control unit 33. This is effective, for example, when it is desired to forcibly return to the initial state.

[Command Decoder] Command Decoder 2
2 is a state signal STEN and a command signal STCMD.
Is converted into a mode control signal SeqMode for designating the irradiation level and the irradiation mode of the light source LD. The mode control signal SeqMode includes the power selection signal P described above.
wrSel and a transition mode signal of a state machine. The command decoder 22 captures data at both edges of the state signal STEN using the state signal STEN as a clock and the command signal STCMD as data.

In this embodiment, the command signal STCMD
Is 3 bits (Bit), and the final pulse power selection signal PEP (2bi
t) and the CL pulse transition mode signal CLMode (1bi)
t), the leading pulse power selection signal PTP (2 bits) is taken in at the falling edge of the state signal STEN, and supplied to the sequencer 21 respectively. The final pulse power selection signal PEP selects the final pulse power Plp and the cooling pulse power Pcl, and the CL pulse transition mode signal CLMode specifies the mode of the above-mentioned special transition condition (A). Also, the first pulse power selection signal PT
P selects the leading pulse power Ptp. These mode control signals SeqMode may be determined not only for the distribution of the present embodiment but also for a desired optical waveform.

[Modulation Unit] The modulation unit 23 includes a sequencer 21
Generates the LD modulation current Imod on the basis of the modulation data DmodL and DmodH supplied from and the modulation signal MOD. The PbDAC 40 is a current output DAC (D / A converter) that supplies a current based on the modulation data DmodL.
The Ptp DAC 41 is a current output DAC that supplies a current based on the modulation data DmodH. The switch 42 receives the Pb DAC 40 or the Ptp DAC 4 according to a selection signal supplied from the MUX 65 (a modulation signal MOD, that is, an LD modulation signal WSP is supplied at the time of recording).
1 and outputs the LD modulation current Imod. Here, the selection signal, that is, the modulation signal MOD is high (H
If it is high, the output of the Ptp DAC 41 is set to low (Lo).
If w), the output of the PbDAC 40 is selected.

Further, PbDAC40 and PtpDAC41
Full scale Iscl is a scale DAC (Scale
DAC) 43, which is set according to the scale signal Scale supplied from the differential quantum efficiency controller 28. Further, the full scale Iful of the scale DAC 43 is supplied from ηREF, and the light source LD used is
May be determined from the differential quantum efficiency of. Full scale Isc
The method of calculating and setting 1 will be described later. Therefore,
The output currents I0 and I1 of the PbDAC 40 and the PtpDAC 41 are obtained by calculations based on the following equations (2) and (3). Here, PbDAC40, PtpD
AC41 and scale DAC43 are 8 bits (bit)
DAC.

[0053]

## EQU2 ## I0 = (DmodL / 255) * (Scale
/ 255) * Ifull

[0054]

## EQU3 ## I1 = (DmodH / 255) * (Scale
/ 255) * Ifull

As described above, the modulation data Dmod
Since the change timing of L and DmodH is not selected by the switch 42, if the response speed of the PbDAC 40 and the PtpDAC 41 is sufficiently high, PbDA
Changes in the output currents I0 and I1 of the C40 and Ptp DAC 41 are also made while the switch 42 is not selected, and the change in the modulation current Imod is determined only by the change timing of the modulation signal MOD.

FIG. 6 is a block diagram showing another example of the configuration of the modulator 23 shown in FIG. Modulation data (PrData to PlpData) corresponding to each state of the state machines SMa and SMb is supplied from the sequencer 21, and PrDAC80a, PeDAC80b, PbDAC
80c, PclDAC80d and PeDAC81a, PDAC
tpDAC81b, PmpDAC81c, PlpDAC
81d outputs currents I0a to I0d and I1a to I1d based on the modulation data, respectively. The switch 82 outputs the currents I0a to I0d according to the signal state0 indicating the current state of the state machine SMa.
And outputs one of them. Similarly, the switch 83 outputs a signal sta indicating the current state of the state machine SMb.
One of the currents I1a to I1d is selectively output according to te1.

The switch 82 is connected to the modulator 23 shown in FIG.
Similarly, the current I0 or the current I1 supplied from the switches 82 and 83 is selected according to the selection signal supplied from the MUX 65, and the LD modulation current Imo is selected.
Output d. Also, the scale DAC 43 is the same as the modulator 23 shown in FIG.
80b, Pb DAC 80c, Pcl DAC 80d, and P
eDAC81a, PtpDAC81b, PmpDAC8
1c, Determine full scale of Plp DAC 81d. According to this embodiment, when the switch is not selected by the switch 84, the switch is performed to the switch 82 or the switch 83.
The modulation is performed during the time when the modulation unit 2 is not selected in FIG.
3, the modulation current Imod changes according to the modulation signal MOD.
Is determined only by the change timing.

The changing speed of the output currents I0 and I1 is determined by the switching speed of the switches 82 and 83.
DAC80a, PeDAC80b, PbDAC80c,
PclDAC80d, PeDAC81a, PtpDA
The response speed of C81b, PmpDAC81c, and PlpDAC81d may not be high. Therefore, high speed DA
This is effective when it is difficult to realize C. Since the output currents I0b and I1a output the same current,
AC may be shared. Further, when reproducing, the PrDAC 80a outputs the PeDAC 80b, PbDAC 80c, Pc
Since the lDAC 80d is used for recording,
rDAC80a is replaced by PeDAC80b and PbDAC80
c, Pcl DAC 80d.

FIG. 11 is a block diagram showing still another example of the configuration of the modulator 23 shown in FIG. FIG. 12 shows FIG.
FIG. 4 is a waveform chart showing output signals of respective parts of FIG. As shown in FIG. 11, the sequencer 21 outputs modulation data DmodL and DmodL.
In addition to modH, addition data exDataL and exDa
taH is supplied. These addition data are also output according to the state machines SMa and SMb. Pb + DAC
90, PbDAC91, Pt + DAC92, PtDAC
93 outputs a current based on the data. Adders 94 and 95 are Pb + DAC 90 and PbDA, respectively.
Addition of output current of C91, Pt + DAC92 and PtDA
The output currents of C93 are added, and currents I0 and I
Outputs 1.

The switch 96 selects the output currents I0 and I1 according to the modulation signal MOD and outputs the LD modulation current Imod. The scale DAC 43 is composed of Pb + DAC 90 and Pb DAC 9 in the same manner as the modulation section 23 shown in FIG.
1, the full scale of Pt + DAC92 and PtDAC93 is determined. Since the Pb + DAC 90 and the Pt + DAC 92 only output the addition, there is no need to widen the dynamic range.
It may be smaller than the full scale of the tDAC 93 to reduce the number of added data bits. By doing so, the number of bits of the register for holding data can be reduced.

[Current Driver] The current driver 25 amplifies the current supplied from the current adder 24 and supplies a drive current ILD for the light source LD1 or LD2. The switch 44 supplies an input current to the current amplifier 45 or 46 according to the selection signal IoutSel. Current amplifier 45
And 46 amplify the current supplied from the switch 44 at a predetermined amplification factor Ai, and
Is supplied with a drive current ILD. Therefore, at this time, L
The D drive current ILD is obtained by an operation based on the following equation (4).

[0062]

## EQU4 ## ILD = Ai * (Ibias + Imod-Ih)
fmofs)

However, Ihfmofs becomes “0” when high-frequency superposition is not performed. Also, the offset current Ihfm
Ofs may be turned off during high-frequency superimposition and added when high-frequency superposition is not performed. Also, Ib = Ai * (I
bias−Ihfmofs), Im = Ai * Imod, and as shown in FIG. 8, if Ib is controlled to be equal to the threshold current Ith, Im, that is, the modulation current Im
od becomes a waveform proportional to the optical waveform. In this embodiment, it is not assumed that the light sources LD1 and LD2 are irradiated simultaneously.

As can be seen from the above, the pulse width of the light modulation waveform of the light source LD is determined only by the modulation signal WSP.
Between two signals of the output of the LD modulation signal generation unit 10 (WS
Even if there is a skew in (P, STEN), the optical waveform is not affected, and an accurate recording mark can be formed. Therefore, the LD modulation signal generation unit 10 may be constituted by an integrated circuit different from the LD drive unit 12, and a semiconductor process suitable for each desired circuit characteristic can be selected.
An apparatus suitable for cost and performance can be configured.
That is, since a high-speed operation and high integration are required in the LD modulation signal generation unit, a fine CMOS process is suitable.

On the other hand, since a light source LD having an operating voltage of about 1 to several V is connected to the LD driver, a high breakdown voltage process (for example, 5 V or 3.3 V) is required. Usually, it is difficult to increase the breakdown voltage in a fine CMOS process (for example, in a 0.18 μm CMOS process, there is only a breakdown voltage of about 1.8 V). Become like

[PD Amplifier Unit] The PD amplifier unit 26 receives a monitor light receiving signal from a monitor light receiving unit that monitors a part of the light emitted from the light source, and performs offset adjustment and gain adjustment. In the monitor light receiving section, a single light receiving element (PD: Pho
and a type in which a monitor light-receiving signal is output as a current in accordance with "To Detector" or a type in which a current-voltage converter is built in and the monitor light-receiving signal is output as a voltage. In the present embodiment, both types can be supported, and the selection is made by the MUX 48. That is, in the case of the current output type, a signal obtained by converting the input monitor light receiving signal into a voltage by the current / voltage converter (I / V) 47 is selected, and in the case of the voltage output type, a signal not passing through the current / voltage converter 47 is selected. I do.

The adder 50 adjusts the offset of the monitor light receiving signal, and the offset DAC (Offse
(tDAC) 49 is added or subtracted. Gain switching amplifier (X1 / X4 / X8 / X16
The AMP 51 switches the gain of the monitor light-receiving signal subjected to the offset adjustment in accordance with the gain switching signal PDGain (for example, four-stage switching of 1/4/8/16 times) to adjust the gain. In general, the reproduction light amount and the recording light amount are greatly different, so that it is preferable to switch the gain at the time of recording / reproduction. The light receiving current Ipd of the PD is obtained by an operation based on the following equation (5), where α is the light use efficiency of the light source LD with respect to the emitted light Po, and S is the light receiving sensitivity of the light receiving unit PD.

[0068]

## EQU5 ## Ipd = α · S · Po

Assuming that the conversion gain of the current-voltage converter (47 or one having a built-in monitor light receiving unit) is Giv and the gain of the gain switching amplifier 51 is Gpd, the monitor signal Imon is based on the following equation (6). Obtained by calculation.

[0070]

## EQU6 ## Imon = Gpd.Giv.Ipd = Gpd.
Kpd ・ Po

Here, Kpd = Giv · α · S.
Note that the offset voltage supplied from the offset DAC 49 is omitted for convenience. Further, when a monitor light receiving unit for monitoring the light emitted from the light sources LD1 and LD2 is provided separately,
It suffices that two inputs of the PD amplifier unit 26 are provided, a monitor light receiving signal supplied from the monitor light receiving unit is input to each of the inputs, and a monitor light receiving signal corresponding to the illuminating light source LD is selected.

[Bias Current Control Unit] The bias current control unit 27 generates a reference signal Itarget in which the monitor signal Imon supplied from the PD amplifier unit 26 is generated from the target level signal Dtarget supplied from the sequencer 21.
The bias current Iapc is controlled so as to coincide with t.
In the present embodiment, the following three control methods can be selected.

(1) Average value control method The modulation data D is included in the two target level signals Dtarget.
Supplying the same data as modL and DmodH, P-BD
The AC 52, the P-PDAC 53, and the switch 54 generate a reference signal Itarget proportional to the amount of light emission. P-B
The operations of the DAC 52, the P-PDAC 53 and the switch 54 are the same as the operations of the Pb DAC 40, the Ptp DAC 41 and the switch 42, respectively. Here, the output light amount Po
And the proportional coefficient between the reference signal Itarget and K is
The following relationship shown in Expression 7 is obtained.

[0074]

[Equation 7] Target = K · Po

Further, this proportionality coefficient K is calculated by the bias scale DAC (BscaleDAC) 70 as P-BDA.
It is determined by setting the scales of C52 and P-PDAC 53, and is set in advance so that K = Kpd. Kpd is the emission light P of the light source LD of the light receiving unit PD to be used.
Since this varies depending on the variation of the light use efficiency α and the light receiving sensitivity S with respect to o, this setting may be made at the time of initial adjustment. Further, the bias scale setting value BiasScale is changed in accordance with the gain Gpd of the gain switching amplifier 51. Since this reference signal Itarget indicates the target emission light amount, the LD can be irradiated with the target irradiation light amount if the monitor signal Imon for monitoring the emission light amount matches the reference signal Itarget.

The error amplifier 55 receives the reference signal Itage
The difference signal between t and the monitor signal Imon is amplified and supplied to the next stage. S / H integrator (S / HIntegra.) 56
Integrates the amplified difference signal supplied from the error amplifier 55 and outputs a bias current Iapc. The S / H integrator 56 always performs an integrating operation in this control method. Further, the control speed can be changed by the SRSel signal. This is the charge / discharge current to the integrator (eg,
This is performed by changing the output current of the error amplifier 55). This makes it possible to set the control speed to an optimum value during recording / reproduction. Also, R-Cont
Sets the settable range of the charge / discharge current.

FIG. 14 is a diagram showing an example of each signal waveform used for explaining the operation of the bias current control section 27. FIG. 7A shows an optical waveform which is a light emission waveform, and FIG. 7B shows a monitor signal Imon. Light receiving part P to be used
It is assumed that the band is limited by D. The broken line in the figure indicates the average level. As shown in the figure, when the irradiation power or duty is changed, the average level changes. In this case, accurate control cannot be performed by a conventional method of performing error control with a predetermined average value calculated in advance. Also, (c) in the figure is a reference signal Itartet, which has a waveform proportional to the irradiation waveform as described above. The broken line indicates the signal in the bias control band. As described above, by generating a reference signal proportional to the irradiation waveform and using the reference signal for error control, accurate bias control can be performed even when the average level fluctuates due to a change in irradiation power or duty.

(2) Sampling / Holding Control Method The S / H integrator 56 performs an integration operation at the time of sampling (for example, ApcSmp = High) based on the ApcSmp signal to perform bias current control. A certain bias current Iapc is held.
Therefore, since the output of the error amplifier 55 is not integrated during the hold, the drift of the control value due to the circuit offset of the error amplifier 55 can be reduced. Also, the reference signal It
The generation of the target may be performed in the same manner as described above, except that a constant reference signal Ita corresponding to the target irradiation power at the time of sampling is used.
rget may be used. In the present embodiment, the ApcSmp signal is generated by the sequencer 21 and is generated by an LD modulation signal and a state signal (controlled by a state machine).

This waveform example is shown in FIG. Apc
The Smp signal indicates a sample period when it is high and a hold period when it is low. ApcSm
The rise of the p signal is when the state state0 = Pe,
When the state signal STEN2 is low, the signal is synchronized with the rising edge of the LD modulation signal WSP. The falling is the next LD
Performed at the rise of the modulation signal WSP (state state0
= Pe, state signal STEN2 = High). With this configuration, it is not necessary to newly add a signal line. Otherwise, the same operation as the control method (1) is performed.

(3) ACC (Automatic Cu
(Rent Control) Control Method In this embodiment, ACC control can be performed without performing APC control. ACC bypasses the error amplifier 55
The output of the P-BDAC 52 according to the data is output as the bias current Iapc. At this time, if the output of the P-BDAC 52 is held in the S / H integrator 56, the initial value of the integrator is changed when shifting from this mode to another control mode ((1) or (2) above). ACC on hold
Since the data becomes data, the bias current does not become discontinuous, and it is possible to prevent the light source LD from emitting excessive light or being turned off at the time of switching.

Conversely, when switching from the APC control mode to the ACC mode, the value of the bias current Iapc may be monitored and obtained, and set as ACC data. Switching to the control mode is AC
Instructed by the CSel signal. In the present embodiment, the bias current Iext can be externally applied without using the bias current control unit 27. Although illustration is omitted, at this time, the external bias current I
If ext is held in the S / H integrator 56, the transition can be performed reliably and promptly when switching to the internal bias current control unit 27.

FIG. 7 is a block diagram showing another configuration example of the bias current control unit 27 shown in FIG. The target level signal Dtarget2 is data generated by switching the above-mentioned modulation data DmodL and DmodH with the modulation signal MOD, and includes a bias DAC (BiasDAC) 7.
The reference signal Itage, which is the average value of the light emission amount, is set to 1
Generate t. Since the purpose of the bias DAC 71 is to generate an average value of the light emission amount, the PbDAC
40, the high-speed operation of the Ptp DAC 41 is not required. According to this embodiment, since the configuration of the reference signal target generation unit can be simplified and the response speed of the DAC can be reduced, the chip size and current consumption can be reduced. The other blocks operate in the same manner as those shown in FIG. 3, and the control methods (1) to (3) can be applied in the same manner.

[Differential Quantum Efficiency Control Unit] The differential quantum efficiency control unit 28 detects the differential quantum efficiency η of the driving light source LD (light source LD1 or light source LD2), and outputs the LD modulation current in accordance with the detection result. The scale Scale is controlled.
This is performed by detecting a difference in the irradiation light amount between two predetermined points, comparing the difference with a reference value ηtarget, and increasing or decreasing the scale Sacule value based on the comparison result. The sample hold circuit (S / H) 57 converts the monitor signal Imon at the time of the reference irradiation light amount (P1) into EtaSmp
Sample / hold according to the signal. The differentiator 58 is
Output of sample and hold circuit 57 and monitor signal Imon
And generates a difference signal.

The etaref DAC 59 has a reference value ηta
Output rget. The comparator (Comp) 61 compares the output of the differentiator 58 with the reference value ηtarget.
out) 62. The comparison timing of the comparator 61 is performed according to the CompCK signal.
The comparison starts at the rise of the K signal. The counter 62 increases or decreases the counter value according to the comparison result Up / Down signal output from the comparator 61. Update of the counter value is Com
This is performed at the falling edge of the pCK signal. This count value is calculated as Scal
The signal is supplied to the modulation unit 23 as an e signal, and the light emission amount increases and decreases in accordance with the increase and decrease of the Scale signal. The initial value of the counter 62 may be PSscale (initial value at the time of recording) or RSc.
ale (initial value at the time of reproduction) is set.

Although not shown, means for averaging the count values may be provided, and the moving average value of the count values may be used as the Scale signal. By averaging in this manner, oscillation of the control value (Scale) can be prevented. Further, a dead zone is provided in the comparator 61, and when the two substantially match, U
The same effect can be obtained even when neither the p / Down signal is output. The full scale of the etaref DAC 59 is set by the bias scale DAC 70. The emitted light amount Po of the light source LD and the monitor signal Im
The relational expression with “on” is expressed by the above equation (6), and the coefficient Kpd changes depending on variations in the light use efficiency α and the light receiving sensitivity S of the light receiving unit PD used with respect to the emitted light Po of the light source LD.

That is, although the reference value ηtarget also varies from device to device, the bias scale DAC 70 sets the reference value ηtarget.
Variation can be absorbed by adjusting the full scale of the arefDAC59. Therefore, the reference value ηtarget is naturally calculated according to the coefficient Kpd.
May be set. Note that the bias scale DAC 70 supplies the reference signal Ita of the bias current control unit 27 as described above.
Since rget is also adjusted, common adjustment can be performed and the adjustment process can be simplified.

Next, an example of the differential quantum efficiency control method will be described. The control method during the recording operation on the phase change recording medium,
A description will be given based on the waveform diagram of FIG. In this control method, light is emitted at a power P2 for detecting η for a predetermined period in a long space as indicated by an optical waveform shown in FIG. 4C (broken line portion (B)). Sample (the sample signal is EtaSm shown in FIG.
p). Further, during the subsequent irradiation of the erase power P1, the comparator 61 compares with the reference value (CompCK shown in (k) of the figure). That is, the differential quantum efficiency η is detected from the difference between P1 and P2.

Normally, a phase-change type recording medium such as a CD-RW hardly deteriorates the recording characteristics with a slight change in erase power. Also, since the variation of the differential quantum efficiency is mainly caused by the temperature change, this control band may be slow and the frequency of light emission with this special power P2 may be small, so that this control method does not adversely affect the recording performance. .
Further, only when there is a possibility that the initial value PSScale of Scale may be shifted, such as immediately after the start of recording, the control speed may be increased by increasing the sampling frequency. In this way, the variation of the differential quantum efficiency can be automatically controlled without affecting the recording performance, and the light source LD can emit light with a desired light amount.

The control signals EtaSmp signal and CompCK signal are output to the sequencer 21 by L
It can be generated from the D modulation signal and the state signal. less than,
A method for generating the LD modulation signal and the state signal will be described.
First, an LD modulation signal (WSP signal) and a state signal (S
The TEN signal) generates a signal as indicated by a portion surrounded by a dashed-dotted line frame (C) in FIG. The state signal STEN2 shown in (e-2) of the figure is generated from the LD modulation signal WSP and the state signal STEN, and similarly becomes as shown by a broken line in the figure. At this time, the state machine SM of the sequencer 21
a and SMb make the following state transitions.

{State Machine SMa} In the state Pe,
If the state signal STEN2 = low (Low) and the rising edge of the LD modulation signal WSP (time t13), the state Pcl
Transitions to. At this time, the modulation data corresponding to the final bottom pulse power Pcl is the power P2 (=
Peta) is output. That is, this state (Pe
When the LD modulation signal WSP is low (ta) at ta), the light is emitted with the power P2 for η detection for a predetermined period. At the same time, the EtaSmp signal is set to High (sample). Then, the state returns to the state Pe at the rising of the next LD modulation signal WSP (time t15). Further, CompCK is set to High in accordance with the transition to this state,
Next, when the state transits to the state Pb, it is set to low. After that, it is the same as usual.

{State Machine SMb} At the falling edge of LD modulation signal WSP at time t12, state signal S
Since TEN is low, the state remains at Pe. The same applies to time t14. At the falling of the LD modulation signal WSP at time t16, the state signal STEN = high (Hi)
gh), the state transits to the state Ptp. After that, it is the same as usual.

[High-Frequency Modulation Unit] Generally, in an optical disk device, so-called high-frequency superposition is performed in which modulation is performed with a high-frequency signal during reproduction in order to suppress noise of a light source due to return light from an information medium. The high-frequency modulation unit 30 generates a high-frequency superimposition signal HFMOD and an offset current Ihfmofs to be applied to the bias current when the high-frequency superposition is performed. Further, in the present embodiment, the high frequency modulation itself is performed using the modulation unit 23, and therefore, the operation of the modulation unit 23 when the high frequency is superimposed will also be described. The VCO 64 is an oscillator that generates a signal HFMOD having a frequency according to the frequency setting signal output from the FreqDAC 63.

The MUX 65 selectively outputs the high-frequency superimposed signal HFMOD and the modulation signal MOD output from the sequencer 21 according to the HF-ON signal, and supplies the selected signal to the modulation unit 23. Here, the case of high frequency superposition will be described.
It is assumed that the OD signal is selected. Also, HFBDAC
The offset current Ihfmofs to be added is generated by the buffer amplifier 67 and the buffer amplifier 67, and the presence or absence of application is set by the switch 68. Furthermore, when the VCO 64 does not perform high-frequency superposition (instructed by HF-ON), unnecessary power consumption can be suppressed by stopping oscillation. Modulation unit 2
3 performs the following operation during high-frequency superposition.

The modulation data DmodL and DmodH are provided with data corresponding to the bottom level and the top level, respectively, and the PbDAC 40 and the PtpDAC 41 respectively output Imod
btm and Itop are output. The modulation degree can be changed by changing the modulation data. Then, the switch 42 modulates the modulation current Im according to the high-frequency superimposition signal HFMOD.
generate od.

The LD drive current is obtained by the calculation based on the equation shown in the above equation (4), and the optical modulation waveform is as shown in the diagram of FIG. 9 (in FIG. 9, for convenience, the amplification factor Ai of the current drive unit is shown).
Is omitted). Then, the bias current is controlled so that the average light amount Pavg becomes the target light amount Ptarget. Also, PbDAC40 and Ptp are equivalent to the above description.
The full scale of the DAC 41 is set by the Scale signal, and if the control operation by the differential quantum efficiency controller 28 is not performed during reproduction, the initial value RSscale of the Scale signal during reproduction is given constant.

In the above description, the operation for outputting the optical waveform shown in FIG. 4C has been described. However, other optical waveforms can be output by changing the state signal STEN, the set value, and the like. FIG. 10 is a waveform diagram showing an example of another output signal. As shown in FIG. 10, in order to control the edge position after the recording mark, the final pulse power Pl
Instead of adding the control of p and the cooling pulse power Pcl, a method of adding the control of the erase start power Pep (broken line portion (iv) in FIG. 10) to the pulse width control is realized. The LD modulation signal WSP and the state signal STEN are given as shown in FIG. The only difference from the case of FIG. 4 is the fall timing of the state signal STEN. Further, the state machines SMa and SMb can be handled only by partially changing the transition conditions.

Therefore, a condition based on the optical waveform mode setting may be added to the transition condition. That is, in the state machine SMa of FIG.
Alternatively, the transition of (b) may be performed. The irradiation power Pep corresponds to the state Plp. Thus, the irradiation power corresponding to each state of the state machine,
Various optical waveforms can be generated by changing the transition condition.

Next, the LD modulation signal generator 10 will be described in detail. FIG. 15 shows an LD modulation signal generation unit 10.
FIG. 3 is a diagram showing the configuration of FIG. The LD modulation signal generator 10 generates a clock signal PCK multiplied by n from the recording clock signal WCK.
And a PLL unit 110 for generating a plurality of clock signals having different phases by a predetermined amount from the clock signal PCK;
Recording data signal Wd supplied from the controller 19 of FIG.
at run-length signal Le.
n0-Len2, and outputs a delayed recording data signal dWdata obtained by delaying a predetermined amount of recording data signal by a run length detector (RunLength Det.) 1
11 and a drive waveform generation information holding unit (Strategy Memory) 112 for storing drive waveform generation information and outputting information corresponding to the run length signals Len0 to Len2 in accordance with the delay recording data signal dWdata.
It has.

Further, a timing signal generating section 113 for generating a modulation timing signal from the driving waveform generation information output from the driving waveform generation information holding section 112, and an LD modulation based on the modulation timing signal generated by the timing signal generating section 113. A modulation signal generation unit 114 for generating a signal WSP, and a state signal STE from a modulation timing signal also generated by the timing signal generation unit 113.
N for generating a state signal (STEN Ge)
n. ) 115 and the command signal STCMD from the drive waveform generation information output from the drive waveform generation information holding unit 112.
Command generation unit (STCmd Ge
n. ) 116 and a sample signal generator (Sample Timing G) for generating a sample-and-hold APC control sample signal from the recording data signal Wdata.
en. ) 117 and a control unit 118 that receives a control command supplied from the controller 19 in FIG. 2 and supplies a control signal to each unit.

Next, the detailed internal configuration and operation of each section of the LD modulation signal generation section 10 shown in FIG. 15 will be described. [PLL] The PLL unit 110 outputs the recording clock signal WCK.
, A plurality of clock signals PCK having different phases by a predetermined amount from the clock signal PCK (in this embodiment, eight clock signals CK0 to CK7, and CK0 as the clock signal PCK). Generate. Further, it also generates a recording channel clock signal CKch.

M frequency divider (1 / M) 1 in PLL section 110
20, phase comparator (PC) 121, loop filter (F
ilter) 122, oscillator (VCO) 123, and N divider (1 / N) 124 include a PLL (Phase Loc).
(Ked Loop) circuit. The operation of each of the above components is the same as that of a normal PLL circuit, and a detailed description thereof will be omitted. The M frequency divider 120 divides the recording clock signal WCK by M. The division ratio 1 / M can be set (for example, M
= 2, 4), which corresponds to the case where the recording clock signal WCK is supplied as a signal obtained by dividing the recording channel clock signal CKch. Therefore, noise can be reduced by lowering the frequency of the recording clock signal WCK for transfer.

The oscillator 123 generates m clock signals (in this embodiment, eight clocks CK0 to CK7 (m = 8) and CK0 is PCK) having phases different by a predetermined amount. This is composed of, for example, a ring oscillator. The N divider 124 divides one clock signal (for example, CK0) output from the oscillator 123 by N. The frequency division ratio 1 / N can be set, and N / M is a clock signal PCK multiplied by n with respect to the recording clock signal WCK.
Becomes the multiplication number n. Further, the M / N frequency divider 125 divides the clock signal PCK multiplied by n by M / N to generate a recording channel clock signal CKch, which is supplied to each unit.
As described later, the LD modulation signal WSP is the clock signal C
Generated based on K0 to CK7. That is, the division ratio 1
/ N, 1 / M to set the LD modulation signal WS
The pulse width setting resolution of P can be set.

For example, the supplied recording clock signal WC
It is assumed that K is transferred at the same frequency as the recording channel clock CKch, and if M = 4 and N = 16, the clock signal PCK has a frequency that is four times the channel clock signal CKch, and the LD modulation signal WSP has the channel clock. The signal CKch can be generated with a pulse width setting resolution of 1/32 (= m · M / N). Hereinafter, this is referred to as a pulse width setting step (also referred to simply as a step as appropriate). In the case of the above example, 32 steps correspond to one channel clock cycle.

[Run Length Detection Unit] The run length detection unit 111 detects the run length of the recording data signal Wdata supplied from the controller 19 in FIG. 2, and supplies the run length signals Len0 to Len2. The recording data signal Wdata is NRZI (Non Return).
In the binary signal of “to Zero Inverted”, a high (H) section represents a recording mark and a low (L) section represents a space. That is, the run length detection unit 1
Numeral 11 detects the mark length and space length of the recording data. Here, it is assumed that Len1 supplies the mark length, Len0 supplies the immediately preceding space length, and Len2 supplies the immediately following space length.

The run-length detecting section 111 is configured in accordance with the minimum and maximum run-lengths of the recording data signal to be applied. In the present embodiment, the recording medium of DVD format (D
It is assumed that the present invention is applied to an optical information recording apparatus that records information on an optical disc such as VD + RW, DVD-R, DVD-RAM, etc., and the recording data signal Wdata is described assuming a signal that has been subjected to EFM + modulation. That is, the run lengths are 3T to 11T and 14T (T is a channel clock cycle). Further, the recording data is delayed by a predetermined amount in consideration of a predetermined time required to detect the run length and each circuit delay time, and the like, and the delayed recording data signal dWdata
Is output.

FIG. 16 is a diagram showing a detailed configuration example of the inside of the run length detecting section 111. FIG. 17 shows FIG.
FIG. 7 is a waveform diagram of a signal output from each unit in the run-length detecting unit 111 shown in FIG. Counter 1
Numeral 40 counts and outputs the run lengths (high-level section and low-level section) of the recording data signal Wdata ((b) in FIG. 17) based on the recording channel clock signal CKch ((a) in FIG. 17). : (C) in FIG. The run length data counted by the counter 140 is temporarily stored in the FIFO 143 once. The delay circuit (Delay) 141 is configured by a shift register or the like, and outputs the recording data signal Wdata by a predetermined amount (dl).
y) Delayed recording data signal dWdata (FIG. 1)
7 (d)) is output. In addition, signals having different delay amounts for generating the control signals of the respective units are also generated and the FIFO control unit (F
IFO Ctrl) 142.

The FIFO control unit 142 has a FIFO 143
And write / read control of each section and control signals of each section.
The register (Reg) 144 holds and outputs the run-length data read from the FIFO 143 (Len).
0, Len1, Len2). The read timing of the FIFO 143 (the retention timing of the register 144) is set so that the FIFO 143 matches the delay recording data signal dWdata.
It is determined by a control signal supplied from the O control unit 142. That is, as shown in FIG. 17, the mark length Len1, the immediately preceding space length Len0, and the immediately succeeding space length Len2 match the delayed recording data signal dWdata (or, as shown in FIG. 17F, Len0 to Len0). Le
The drive waveform generation information converted by n2 is matched. Note that the delay amount dly and the size of the FIFO 143 may be determined in consideration of the minimum / maximum run length of the recording data Wdata and each circuit delay so that the FIFO is not empty or full.

[Drive Waveform Generation Information Storage Unit] The drive waveform generation information storage unit 112 stores drive waveform generation information, and stores information corresponding to the run length signals Len0 to Len2 in the delay recording data signal dWdata. Output together. FIG. 18 is a timing chart illustrating the relationship between the drive waveform generation information and the optical waveform in the present embodiment. FIG. 19 is a diagram of a list showing an example of combinations of drive waveform generation information for each of a plurality of pieces of timing information.

The drive waveform generation information is composed of timing information indicating the change timing of the irradiation level of the optical waveform, that is, the change timing of the LD modulation signal WSP, and command information transferred as a command signal STCMD such as the LD irradiation level. This timing information is represented by the number of pulse width setting steps, and each timing information (TSS, TS) shown in FIG.
..) Are accumulated from a reference time (for example, the rising edge of the delayed recording data) to determine the change timing of the LD modulation signal WSP. NMP is the number of repetitions of TMS and TMP. Thus, the multi-pulse period and the duty can be set arbitrarily.

In the present embodiment, the rising edge (a) and the falling edge (b) of the last pulse are set independently of the accumulation from the reference time, not from the reference time (the timings (c) and (d)). ) Is cumulative from (b)). In many types of information recording media, their timing largely depends on the trailing edge position control of the formed recording mark. On the other hand, TSS,
Timing information such as TSP becomes important. By independently setting the main parameters for the front and rear edge position control, the setting value of each parameter does not affect the final pulse timing, and the influence on the recording mark edge position is limited.

That is, when changing each parameter set value during the recording operation, even if each parameter is sequentially changed, the influence of the recording mark shape is small. For example, for high-accuracy recording mark shape control, it is necessary to change each parameter according to the recording linear velocity, and when performing CAV recording, change to a set value according to the recording linear velocity during the recording operation. Therefore, it is suitable in such a case. Further, for simplification of the circuit, the timings (a) and (b) may be determined by accumulating the timing information TLS and TLM, respectively, as shown by the broken lines in the figure.

In the present embodiment, the drive waveform is changed depending on the mark length of the recording data signal Wdata and the length of the space adjacent to the recording data signal Wdata, and the position of the recording mark edge to be formed is controlled with high precision. When a recording mark is formed, the edge is thermally affected on the information recording medium by the adjacent space length, and the edge changes according to the adjacent space length. In order to avoid this, the drive waveform is changed in consideration of the adjacent space length. That is, the drive waveform generation information corresponding to each combination of the mark length and the space length immediately before and after is stored, and the run length detection unit 11
1 run-length signals Len0-Len detected by
2 and supplies the corresponding drive waveform generation information.

When the mark length and the adjacent space length are equal to or larger than the predetermined values, the thermal influence and the change thereof are small. Therefore, it is not necessary to prepare drive waveform generation information corresponding to all combinations. For example, as shown in FIG. 19, by preparing a table in which only combinations having a high degree of influence are registered in advance, it is possible to reduce the memory capacity required for holding information. Further, in this embodiment, the combination prepared according to each parameter is also changed to achieve both reduction of the memory capacity and high accuracy of the mark shape control.

FIG. 20 is a diagram showing a detailed internal configuration example of the drive waveform generation information holding unit 112 shown in FIG. The memories 152a to 152n storing the respective parameters operate independently, and the run length signals Len0 to Len2
To the address conversion unit (Addr Convert)
er) 150a to 150n, and the selector 1
The signals are supplied as address signals of the memories 152a to 152n through 51a to 151n. Output buffer 153a-
Reference numeral 153n controls output of read data corresponding to a memory for which a read request has been issued from the control unit 118. An output enable signal is generated by the register access control unit 154 and supplied to each output buffer.

Register access control unit (Register)
r Access Control) 154 corresponds to FIG.
The access control to each of the memories 152a to 152n is performed in response to the write / read request from the control unit 118. The selectors 151 a to 151 n correspond to the register access control unit 1.
When the memory is accessed from 54, the address supplied from the address conversion units 150a to 150n and the address supplied from the register access control unit 154 are switched. Also, the register access control unit 154
Is designed to access the memories 152a to 152n during the space period in response to a memory access request during the recording operation.

[Timing Signal Generation Unit and Modulation Signal Generation Unit] The timing signal generation unit 113 generates a modulation timing signal from drive waveform generation information (timing information). The modulation timing signal includes a timing pulse signal synchronized with the clock signal PCK multiplied by n and a phase selection signal. The modulation signal generator 114 generates an LD modulation signal WSP from the modulation timing signal supplied from the timing signal generator 113. At the time of generation, with reference to the clock signals CK0 to CK7, the time corresponding to the phase difference between the clock signals becomes the pulse width setting resolution of the LD modulation signal WSP.

FIG. 21 is a diagram showing a detailed internal configuration example of the timing signal generator 113 and the modulation signal generator 114. FIGS. 22 and 23 are waveform diagrams of signals output from each unit of the timing signal generation unit 113 and the modulation signal generation unit 114 shown in FIG. FIG. 24 is an explanatory diagram showing the operation of two sequencers in the timing control section 160 shown in FIG. The outline of the operation of generating the LD modulation signal WSP from the drive waveform generation information via the generation of the timing pulse signal and the phase selection signal will be described with reference to FIGS.

The timing control unit (Timi) shown in FIG.
ng Ctrl) 160 generates a control signal for each unit described later based on the operation of the two sequencers shown in FIG. Further, a reference time of a pulse train of the LD modulation signal WSP which is delayed from the delay recording data signal dWdata by a predetermined time Δ (PCK unit) is generated. Timing calculation unit 161
Calculates the number of pulse width setting steps from the timing information supplied from the drive waveform generation information holding unit 112 to the next modulation timing based on the operation instruction signal supplied from the timing control unit 160.

In this embodiment, the rising modulation timing and the falling modulation timing are separately processed in order to realize a high-speed operation of the circuit, and the next rising modulation timing Next is processed.
Timing1 and next falling modulation timing NextT
imaging2 is calculated. Then, as for the calculated number of steps up to the next rising modulation timing NextTiming1, the upper 5 bits are the counter (Count).
er) 163a, the lower three bits are supplied as a phase selection signal to a phase selection signal holding unit (Reg) 164a (here, the number of pulse width setting steps is 8 bits). Similarly, the next falling modulation timing Next
As for the number of steps up to Timing2, the upper 5 bits are supplied to a counter (Counter) 163b, and the lower 3 bits are supplied to a phase selection signal holding unit (Reg) 164b.

Further, similarly, the timing calculation section 16
2 is a pulse (i) of the LD modulation signal WSP shown in FIG.
And (ii) the rising / falling modulation timing is calculated respectively (the rising / falling modulation signal NextT
iming3 and falling modulation timing signal NextTi
ming4), each counter (Counter) 1
63c and 163d and a phase selection signal holding unit (Reg) 1
64c and 164d. Further, the timing control section 160 converts (n−n) from the delay recording data signal dWdata.
3) Channel clock (n is the delay recording data signal dWd)
The second reference time is generated by delaying the mark length of the data (the mark length of the data. Modulation timing signal NextTimin
g3 and NextTiming4 are generated based on the second reference time.

The counters 163a to 163d count the time until the next modulation timing by the clock signal PCK. The number of steps up to the next modulation timing is fetched and the clock signal PCK
Count down by When the count value becomes zero, the set pulse signal (Fse
t, Rset) / reset pulse signal (Frst, Rr
st) (these signals are collectively referred to as “timing pulse signals”). Phase selection signal holding units 164a to 164
d holds the phase selection signals ckph1 to ckph4 and supplies them to the next stage. The holding timing is determined based on a signal supplied from the timing control unit 160 (not shown).

The timing pulse signal control unit 165 includes timing pulse signals Fset, Rset, Frst, and Rr supplied from the counters 163a to 163d, respectively.
From the st, a set / reset signal for each of the flip-flops 167a to 167d is generated. The phase selection signals ckph1 to ckph4 supplied from the phase selection signal holding units 164a to 164d are supplied to the clock selectors 166a to 166d, respectively. The flip-flop 167a outputs the set pulse signal Fset
(Or Rset) to make the output signal q_A high (H)
To At that time, the rising modulation timing signal is determined by the clock signal (one of CK0 to CK7) selected by the clock selector 166a according to the phase selection signal ckphA. For example, FIG. 23 is an enlarged view of a portion (P) in FIG. 22, and CK2 is selected as shown in FIG.

On the other hand, the flip-flop 167b changes the output signal q_B to low (L) according to the reset pulse signal Frst (or Rrst). At that time, the falling modulation timing signal is determined by the clock signal (one of CK0 to CK7) selected by the clock selector 166b according to the phase selection signal ckphB. Then, the logical product of the output signals q_A and q_B is calculated, and the LD modulation signal WSP is obtained.
Generate

The reset pulse signal Rst_A of the flip-flop 167a and the flip-flop 167b
Are generated in accordance with the set pulse signal Fset (or Rset) and the reset pulse signal Frst (or Rrst), respectively. Similarly, the LD modulation signal WSP is also supplied to the flip-flops 167c and 167d and the clock selectors 166c and 166d.
, And the portions (I) and (II) shown by the dashed line frame in FIG.
Finally, the logical sum is calculated to generate an LD modulation signal WSP. The timing pulse signal control unit 165 transmits the timing pulse signals Fset, R
set, Frst, Rrst and phase selection signal ckph
1 to ckph4. Logic circuit 16
Reference numeral 8 denotes a logical product of the output signals q_A and q_B and a logical product of the output signals q_C and q_D, and a logical sum of the logical product output values to generate an LD modulation signal WSP.

FIG. 24 is a state transition diagram of two sequencers provided in the timing control section 160 shown in FIG. 21. FIG. Control of each section. Next, transition conditions of the sequencers 1 and 2 will be described. FIGS. 22 and 23 show an example of state transition.

(A) Sequencer 1 State Idle: Initial state. Delayed recording data signal dWda
The state transits to the state SP by the rise of ta. Until then, stay here. State SP: The state transits to the next state by the load1 signal issued at the reference time, and the others stay here. At that time, the transition destination differs depending on the drive waveform generation information (TSMS and TMS). That is, when TSMS ≒ 0, the state SM
To P, to state MP when TSMS = 0 and TMS ≒ 0,
Otherwise (TSMS = 0 and TMS = 0) state L
Transition to P respectively. State SMP: The state transits to the next state by the load1 signal issued at the same time as the reset pulse signal Frst, and the others stay here. At that time, the drive waveform generation information (TM
The transition destination differs depending on S). That is, when TMS ≒ 0, the state transits to state MP, and when TMS = 0, the state transits to state LP.

State MP: Transit to state LP by the load1 signal issued simultaneously with the reset pulse signal Frst. However, the number of MP repetitions specified by NMP stays here. FIG. 22 shows a case where NMP = 2. State LP: State W by reset pulse signal Frst
transit to ait. State Wait: a standby state when each unit is controlled by the sequencer 2. After the transition of the sequencer 2 to the initial state, the state transitions to the state Idle.

(B) Sequencer 2 state Idle: initial state. Delayed recording data signal dWda
The state transits to the next state by the rise of ta. (N-3) T (n: n) from the rise of the delay recording data signal dWdata
The wait signal is output during the mark length (T: channel clock cycle), and in that case, the state transits to the state Wait. On the other hand, when n = 3 and no wait signal is output, the state transits to the state LMP. State Wait: Stays here while the wait signal is being output. The state is changed to the state LMP by the release of the wait. State LMP: Transits to state EP by load2 signal (issued after wait release predetermined time Δ). State EP: Transits to state End by the load2 signal issued simultaneously with the reset pulse signal Rrst. State End: Transition to state Idle by reset pulse signal Rrst.

Next, a timing calculation formula for each state of each sequencer calculated by the timing calculation units 161 and 162 will be described. << Timing calculation unit 161 >> NextTiming1 = TSS @Idle or SP TSMS + ckph2 @SMP TMS + ckph2 @MP NextTiming2 = TSS + TSP @Idle or SP TSMS + TSMP + ckph2 @SMP TMS + TMP + ckph2 @MP ｛Timing calculation unit 162｝ NextTiming3 = TLMP @Idle or Wait or LMP TES + ckph4 @EP NextTiming4 = TEMP @Idle or Wait or LMP TES + TEP + ckph4 @EP

FIG. 25 is a waveform chart for explaining the signal deletion processing in timing pulse signal control section 165 shown in FIG. Further, generation of the set pulse signal Fset and the reset pulse signal Frst and the set pulse signal Rs
and the reset pulse signal Rrst are generated independently of each other. Therefore, as shown in FIG. 25, the pulse signal WSP_F generated by the set pulse signal Fset and the reset pulse signal Frst, and the set pulse signal Rset
And the pulse signal WSP_R generated by the reset pulse signal Rrst in some cases. In this case, the reset pulse signal Frst and the set pulse signal Rset are deleted in the timing pulse signal control unit 165 (the positions where the reset pulse signal Fset and the set pulse signal Rset are deleted are indicated by circles in FIG. 25), and the set pulse signal Fset and the reset pulse signal Rrst are used as LDs. The signal is supplied to the next stage so that the modulation signal WSP is generated.

In the above-described embodiment, the explanation is made ignoring the delay of each circuit for the sake of simplicity. However, the actual circuit inserts a holding circuit based on the clock signal PCK on each signal line. Produces a minute delay. Therefore, the output LD modulation signal WSP, that is, the optical waveform is delayed by several PCK clocks (referred to as Δ ′) from the reference time, and a total of Δ + Δ ′ is obtained from the delayed recording data signal dWdata synchronized with the recording channel clock signal CKch. Delay. By the way, as described above, the multiple of the clock signal PCK with respect to the recording channel clock signal can be set, and if the multiple is changed at the time of additional writing or rewriting, the recording mark for the recording channel clock signal will be off. In such a case, the delay amount Δ for generating the reference time may be set according to the PCK multiplication number. For example, circuit delay Δ '= 3PCK, Δ + Δ' = 2
If CKch is used, the multiplication number is 2 (1 CKch = 2PC
K), Δ = 1PCK, and when the multiplier is 4, Δ
= 5PCK.

The timing signal generator 113 also includes a STEN timing pulse generator 170 for generating a modulation timing signal for generating the state signal STEN. Further, the bias current control unit 2 shown in FIG.
7. Light source (L) driven by differential quantum efficiency control unit 28
When controlling the irradiation light amount of D), a pulse indicating a sampling timing is inserted into the LD modulation signal WSP to generate various sample signals (ApcSmp signal, EtaSmp signal). For example, in the signal waveform diagrams shown in FIGS. 4 and 10, t11 to t12, t13 to t14, and t15
The pulse inserted at t16 or the like corresponds to the pulse.

The APC timing pulse generation section 171
The modulation timing signal for that purpose is generated,
The generated modulation timing signal is supplied to the timing pulse signal control unit 165, and the LD modulation signal WSP is generated in the same manner as described above. The generation of these modulation timing signals is performed by a control signal from the timing control unit 160. In this manner, by inserting a pulse indicating the sampling timing into the LD modulation signal WSP, the sampling timing can be instructed without adding a signal line, so that the number of signal supply lines transmitted on the FPC board can be reduced. .

FIG. 26 shows the STEN timing pulse signal generated by the STEN timing pulse generator 170 and the APC timing pulse generator 171 shown in FIG.
FIG. 4 is a waveform chart for explaining an example of generating a PC timing pulse signal. [APC timing pulse generator] Timing controller 1
Reference numeral 60 outputs an APC count start signal simultaneously with the second reset pulse signal Rrst. The APC timing pulse generator 171 receives the APC count start signal, and receives a predetermined value APC by an internal counter.
S (PCK unit) is counted, and after the counting, an APCSet pulse signal is output.

The APCRst pulse signal is the APCS signal.
It is output after a predetermined value (for example, 1 PCK) from the et pulse signal. Further, at the time of detecting η, the EtaDetOn signal becomes high (H) and is supplied. The counter continuously counts the predetermined values EtaS and EtaC, and outputs an APCSet pulse signal. APCRst
The pulse signal is output after a predetermined value (for example, 1 PCK) from the APCSet pulse signal in the same manner as described above.

The EtaDetOn signal becomes high (H) when an η detection instruction is issued at a predetermined interval from the controller 19 in FIG. 2 and the space length is equal to or more than the predetermined value EtaLen, and the timing pulse signal generation processing is performed. Later, the η detection instruction is automatically cleared. On the other hand, EtaD
If the etOn signal is low (L), the APCSet pulse signal, APC in the frame (D) circled in FIG.
No Rst pulse signal is generated, and the pulses (B) and (C) in the figure do not appear in the LD modulation signal WSP.

[STEN Timing Pulse Generator] As described above, in this embodiment, the optical waveform can be changed by changing the falling modulation timing of the state signal STEN. The waveform shown in FIG. 4 is called an LP mode, and the waveform shown in FIG. 10 is called an EP mode. The generation of a STEN timing pulse signal in each mode (instructed by LP / EPMode) will be described. As shown in FIG. 26, the STENRst pulse signal is Seq. 2 = Output simultaneously with EP and Rset pulses ((A) in FIG. 26). In the LP mode, Seq. 1 = LP and output simultaneously with the Fset pulse (broken line (a) with arrow in FIG. 26). ST
The output timing of the ENSet pulse signal is EtaDet
The output varies depending on the On signal and is output at the timing shown in FIG. Further, similarly, not only the sampling timing but also a command instruction or the like can be transferred without adding a signal line.

[State Signal Generation Unit] The state signal generation unit 115 shown in FIG.
, A state signal STEN is generated from a STEN timing pulse signal which is a modulation timing signal generated from drive waveform generation information (timing information). The internal configuration of the state signal generation unit 115 may be the same as that in the dashed line frame (I) in FIG.
Since the generation of N is not as fast as that of the LD modulation signal WSP, it is not necessary to perform the alternating operation. Also, the state signal STE
Since the edge position accuracy of N is not required as much as that of the LD modulation signal WSP, it is not necessary to use all three bits of the phase selection signal, and may be fixed to any one of the clock signals CK0 to CK7. The bits of the selection signal may be reduced.

[State Command Generation Unit] The state command generation unit 116 generates a command signal STCMD from the drive waveform generation information (command information). The command signal STCMD is transmitted to the command decoder 2 as described above.
In step 2, the signal is fetched at both edges of the state signal STEN. Therefore, the data change timing of the command signal STCMD only needs to ensure a sufficient capture time before and after the edge of the state signal STEN. here,
The supplied command information is sequentially supplied to the LD drive integrated circuit (LD driver) 1 using the reference time and the APC count start time as switching timing.

[Sample Signal Generating Unit] The sample signal generating unit 117 generates a sample-hold type APC control sample signal from the recording data signal Wdata. Since the light emission waveform of the light source is delayed from the recording data signal Wdata by a delay in the run length detection unit 111, a sample signal is generated in accordance with the light emission waveform. However, as described above, the sample signal generated here is not used when APC control is performed with the configuration shown in FIG.

[Error Detecting Unit and Error Processing Unit] When incorrect data is stored in the driving waveform generation information due to some accident, or when the combination becomes invalid due to the combination of the driving waveform generation information, the LD modulation signal WSP and the state signal STEN are output. Cannot generate a pulse signal at a desired timing, and the LD drive integrated circuit 1 that receives these signals and drives the LD cannot obtain a desired optical waveform, and erroneous information may be recorded. Further, there is a risk that an error propagates to the next and subsequent marks, or that light emission with high power continues, leading to destruction of the LD.

FIG. 27 is a block diagram showing a configuration example of an embodiment in which an error detection means and an error processing means are added to the LD modulation signal generation section 10. The error detection unit 180 includes a timing control unit 160 in the timing signal generation unit 113.
Of the sequencer and the delay recording data signal dWdata
Then, the occurrence of an error is detected. For example, if the sequencers Seq1 and Seq2 do not return to the state Idle within a predetermined time after the recording data signal dWdata becomes a space, an error occurrence signal is output as an error. Also,
The error may be determined by calculating from the drive waveform generation information (timing information).

The error processing section 181 instructs the timing signal generation section 113 to stop supplying the modulation timing signal and to return the sequencer to the initial state by inputting the error occurrence signal, and controls the sequencer 21 in the LD drive integrated circuit 1 to operate. In order to generate the LD modulation signal WSP and the state signal STEN so as to reset to the initial state, the modulation signal generation unit 114
And an error processing pulse to the state signal generation unit 115. Further, by supplying the error occurrence signal directly to the controller 19 (or via the control unit 118),
Instructs correction of drive waveform generation information (timing information). In this way, it is possible to prevent the propagation of the error and prevent the erroneous data from being continuously recorded.

The second error detection section 182 shows another embodiment of the error detection. The second error detection section 182 has the same configuration as that of the sequencer 21 and receives the LD modulation signal WSP and the state signal STEN, and performs LD drive integration. The irradiation level state in the circuit 1 is pseudo-monitored. In this manner, the occurrence of an error is detected and the same error processing as described above is performed.

[Another Embodiment of Command Signal and Command Decoder] FIG. 28 is a diagram showing a configuration example of another embodiment of the state command generator and the command decoder. FIG. 29 is a waveform diagram of a signal output from each unit shown in FIG. As shown in FIG. 28, the state command generator (STCmd Gen.) 190 outputs a command signal STCMD in synchronization with the LD modulation signal WSP based on the modulation timing signal. Command decoder (C
MD Decoder) 191 is an LD modulation signal WSP
And a command signal STCMD to convert to a mode control signal SeqMode for designating an LD irradiation level and an irradiation mode. By doing so, the number of signal lines for the command signal STCMD can be reduced.

[Other Embodiments of Modulating Unit and Sequencer] (Description of Claims 1 to 2 and 4 to 5 of the Invention) FIG. 30 shows a configuration example of another embodiment of the modulating unit and sequencer. FIG. FIG. 31 is a state transition diagram of the state machines SM0 to SM2 provided in the sequencer (Sequencer) 301 shown in FIG. Further, FIG.
FIG. 2 is a waveform diagram of a signal output from each unit shown in FIG.
This sequencer 301 fulfills the function of the state control means. Hereinafter, the configuration and operation of another embodiment of the modulation unit and the sequencer will be described with reference to FIGS.
In addition, the description which overlaps with the above description is omitted suitably.

In the modulation section and the sequencer of this embodiment,
The LD modulation signal WSP indicating the change timing of the irradiation level of the light source LD is converted into two LD modulation signals WSP1 and WSP2 as shown in (e-1) and (e-2) of FIG.
(That is, the first half of the multi-pulse train is divided into the LD modulation signal WSP1 and the second half is divided into the LD modulation signal WSP2). The division between the LD modulation signal WSP1 and the LD modulation signal WSP2 indicates a point in time when the irradiation level of the light source LD is changed, that is, the same function as the above-described state signal STEN is performed, and the LD modulation signals WSP1 and WSP2 are changed. Sequencer (Sequenc)
er) 301 to control the irradiation level of the light source LD.

The sequencer 301 shown in FIG.
Are provided, and each state of each of the state machines SM0 to SM2 corresponds to the irradiation level of the light source LD in the same manner as described above. Then, according to the current state of each of the state machines SM0 to SM2, the modulation data P0Data, P1Data, P2Data
a is output. (G-1) to (g-3) of FIG. 32 indicate state states of the state machines SM0 to SM2, respectively.
0 to state2 are shown. The transition condition of the state will be described later. The transition condition of the sequencer 301 is the command decoder (CMD Decode) as described above.
r) Mode control signal SeqMod supplied from 300
The transition condition is changed by eSel, and the modulation data to be supplied is selected by the power selection signal PwrSel. The command decoder 300 functions as the command demodulating means.

The modulating section 302 modulates the modulated data P0Data, P1Data, P2 supplied from the sequencer 301.
Data and LD modulation signal WSP1 and LD modulation signal WS
An LD modulation current Imod is generated based on P2. This modulating section 302 fulfills the function of the modulating means. P0DA
C303 is a current output DAC that supplies a current in accordance with the modulation data P0Data, and similarly a P1DAC304.
Supplies the current to the modulation data P1Data, and the P2DAC 305 supplies the current to the modulation data P2Data.
The switch 306 controls on / off of the current output from the P1 DAC 304 according to the LD modulation signal WSP1 (turns on when the LD modulation signal WSP1 is “High (H)”). Similarly, the switch 307 outputs the current output from the P2 DAC 305 to the LD.
On / off control is performed according to the modulation signal WSP2, and the switch 3
08 is a signal Mo obtained by NORming the current output from the P0 DAC 303 with the LD modulation signal WSP1 and the LD modulation signal WSP2.
On / off control is performed according to d3 (that is, the LD modulation signal W
SP1 and LD modulation signal WSP2 are both on when low (L).

The current adding section 309 includes the switches 306 to 306
08, and the LD modulation current I
Generate mod. That is, when the LD modulation signal WSP1 is “high (H)”, the state is in the state 1, when the LD modulation signal WSP2 is “high (H)”, the state is in the state 2, and when both are “low (L)”. The currents corresponding to the state 0 are output as LD modulation currents Imod, and an optical waveform as shown in FIG. 32C is obtained. The full scale Iscl of the DACs 303 to 305 is supplied from the scale DAC 43, and the operation is the same as described above.

Next, transition conditions of each of the state machines SM0 to SM2 will be described. It should be noted that the state Pr at the time of reproduction is omitted for simplicity of description (the same as described above). First, each pulse of a portion of the LD modulation signal WSP1 shown in (e-1) of FIG. 32, which is surrounded by a dotted circle in the drawing, is a start pulse indicating the start of a multi-pulse train.
Each of the state machines SM0 to SM0 is generated by the start pulse.
The transition operation of SM2 is started. When the start pulse is “high (H)”, the state of the optical waveform shown in (c) of FIG. 7 does not change because the state 1 shown in (g-2) of FIG. 10 is in the initial state Pe. The start pulse is a "pulse instructing a state transition" according to claim 5 of the present invention.
This is an example.

The PEEnb signal shown in (f) of FIG. 32 indicates a transition between the LD modulation signal WSP1 and the LD modulation signal WSP2, becomes “High (H)” by the start pulse, and changes to the next LD modulation signal WSP2. Rises to a "low (L)" level, and has the same function as the above-described state signal STEN.
It is also used as a clock for taking in the D signal.
The start pulse may be inserted into the LD modulation signal WSP2, or a signal corresponding to the PEEnb signal may be transferred instead of inserting the start pulse.

* State machine SM0 {state Pe} Initial state at the time of recording. When the PEnb signal = "high (H)" and the LD modulation signal WSP1 rises, the state transits to the state Pb. Others stay here. State Pb: WS
The state transits to the state Pcl at the rise of P2. Others stay here. {State Pcl} State P at rising of LD modulation signal WSP2
Transition to e. * State machine SM1 {State Pe} Initial state. PEEnb signal = “high (H)”
At the falling edge of LD modulation signal WSP1, the state transits to state Ptp. Others stay here.

{State Ptp} The state transits to the state Pmp at the falling edge of the LD modulation signal WSP1. Also, the PEEnb signal =
The state transits to the state Pe with “low (L)”. ｛State Pmp｝ PEnb signal = "Low (L)" and state P
Transition to e. * State machine SM2 {State Pe} Initial state. PEEnb signal = “high (H)”
At the falling edge of the LD modulation signal WSP1, the state transits to the state Plp. Others stay here. ｛State Plp｝ State P at falling of LD modulation signal WSP2
Transition to e. Others stay here. In the same manner as described above, these state transitions are performed at the time when the switch is not selected, so that a change in modulation data does not affect the optical waveform.

As can be understood from the above, the change timing of the LD light waveform is determined by the change timing of the LD modulation signal WSP1 or LD modulation signal WSP2, and the two signals are prevented from changing at the same time. Even if there is skew, optical waveform disturbance is not caused. In particular, since the state where the switches are turned on at the same time is eliminated, the concern of LD destruction due to excessive light emission can be eliminated. Therefore, the modulation signal generation unit 10 may be constituted by an integrated circuit different from the LD drive unit 12, and it becomes possible to select a semiconductor process suitable for each required circuit characteristic, and to provide an apparatus suitable for cost and performance. Can be configured.

(Explanation of claim 10 of the present invention)
The delay adjuster 311 in FIG. 30 includes a delay setting signal DlyAd
j, the LD modulation signal WSP1 or the LD modulation signal W
This is for adjusting the delay amount of SP2. That is, it corresponds to the delay adjusting means. In this way, even if there is a skew between the signals of the LD modulation signal WSP1 and the LD modulation signal WSP2, it is possible to correct the skew, generate an optical waveform having a desired pulse width, and more precisely control the recording mark position. Can be. (Hereinafter, description points according to claim 11 of the present invention)
This delay adjustment unit 311 is connected to the LD modulation signal generation unit 10 on the supply side of the LD modulation signal WSP1 and the LD modulation signal WSP2.
(Not shown). The means for adjusting the amount of delay can be easily realized by adding or subtracting an offset from the timing information of one signal by an amount corresponding to the skew.

(Description of Claims 6 and 7 of the Invention) In this embodiment, the ApcSmp signal and the EtaSm
A timing signal such as a p signal can be transferred while being superimposed on the LD modulation signal WSP1 or the LD modulation signal WSP2. For example, a start pulse having a waveform as shown by a chain line in (e-1) of FIG. Further, as shown by the broken line (A) in (e-2) of the figure, the EtaSmp signal is superimposed on the LD modulation signal WSP2 in the long space.
In this way, the number of signal lines transferred on the FPC board can be reduced.

(Explanation of claim 8 of the present invention) Also, a plurality of pulses are inserted in the space period (period from the last pulse of LD modulation signal WSP2 to the start pulse) of LD modulation signal WSP1 or LD modulation signal WSP2. Alternatively, predetermined command data may be indicated by the number of inserted pulses. (Hereinafter, description points according to claim 9 of the present invention) Alternatively, a clock for STCMD transfer as shown in (i) and (j) of FIG. 32 may be inserted. The LD modulation signal WSP2 shown in (i) of FIG. 32 is the LD modulation signal WSP of FIG.
The STCMD shown in (j) of FIG.
D respectively.

(Explanation of Claim 3 of the Invention) Still Another Embodiment of Modulating Unit and Sequencer FIG.
FIG. 14 is a state transition diagram of state machines SM0 to SM2 in still another embodiment of the modulation unit and the sequencer.
FIG. 34 is a diagram illustrating another waveform example of a signal output from each unit in still another embodiment of the modulation unit and the sequencer. The configurations of the modulator and the sequencer in this embodiment may be the same as those in FIG. However, the state machine in the sequencer follows the state transition diagram shown in FIG.
In the same manner as described above, the change timing of the irradiation level of the light source LD is divided into two LD modulation signals WSP1 and WSP2 as shown in (e-1) and (e-2) of FIG. WSP1 includes the first pulse and the last pulse of the multi-pulse train, and LD modulation signal WSP2 includes the remaining intermediate pulses.

Next, transition conditions of each of the state machines SM0 to SM2 in this embodiment will be described. * State machine SM0 {State Pe} Initial state at the time of recording. PEnb signal = “high (H)” and state Pb at the rise of LD modulation signal WSP1
Transitions to. However, when the exCL signal = "1", the state transits to the state Pcl. Others stay here. {State Pb} State Pc at the rise of LD modulation signal WSP1
Transitions to 1. {State Pcl} State P at rising of LD modulation signal WSP1
Transition to e.

* State machine SM1 {State Pe} Initial state. PEEnb signal = “high (H)”
At the falling edge of LD modulation signal WSP1, the state transits to state Ptp. However, when the exCL signal is “1”, the state Plp
Transitions to. Others stay here. ｛State Ptp｝ State P at falling of LD modulation signal WSP1
Transition to lp. ｛State Plp｝ State P at the falling edge of the LD modulation signal WSP1
Transition to e. * State machine SM2 {State Pe} Initial state. PEEnb signal = “high (H)”
To transition to the state Pmp. Others stay here. "State Pmp @ PEnb signal =" Low (L) "and state P
Transition to e. Others stay here.

In this case, the same effect as described above can be obtained. Furthermore, in multi-pulse train recording, the first pulse and the last pulse are usually the main factors determining the leading and trailing edge positions of the recording mark, and the duty ratio of the intermediate pulse is important, and a slight time lag can be tolerated. That is, the LD modulation signal WSP1 and the LD modulation signal W
There is a skew between the signal with SP2 and the intermediate pulse
Even if the position is slightly shifted as shown in FIG. 4B, the influence on the recording mark edge position is slight. Therefore, according to this embodiment, the skew margin between signals can be increased. Of course, if the delay adjustment unit 311 is provided, more accurate recording mark control becomes possible.

Next, still another embodiment of the modulator will be described. FIG. 35 is a diagram illustrating a configuration of still another embodiment of the modulation unit. This modulation section 319 has a P0DA
C320 to P2DAC 322 correspond to P0 in FIG.
It corresponds to the DAC 303 to the P2 DAC 305. The switch 323 outputs the signal P0DAC3 according to the LD modulation signal WSP1.
The switch 324 switches between the output of the P2 DAC 322 and the output of the P2 DAC 322 in accordance with the LD modulation signal WSP2. The current adder 325 adds the currents input via the switches 323 and 324 to generate an LD modulation current Imod.
Here, when the switch 324 is turned on, P0DAC
P2Data is P
The value corresponding to 0Data is subtracted. That is, Pw-Pb
Set the data corresponding to. By doing so, there is no problem with the switch timing deviation, so that relative errors such as switching characteristics between switches and delay of a switching signal in the integrated circuit can be reduced, and the design of the integrated circuit becomes easy.

According to the light source driving device of the above-described embodiment, the change timing of the optical waveform is determined by the change timing of the first or second modulation signal, and the two signals are prevented from changing at the same time. Even if there is a skew between the two signals, an optical waveform is not disturbed, and an accurate emission waveform can be obtained. And speeding up information recording,
It is possible to realize a simple configuration without sacrificing cost, performance, etc., even for requests for high-density recording of an information recording medium. If the light source driving device of this embodiment is applied to an optical information recording device, an accurate recording mark can be formed.

In particular, when applied to an optical information recording apparatus, in multi-pulse train recording, the first pulse and the last pulse are the main factors determining the leading and trailing edge positions of the recording mark, and the duty ratio of the intermediate pulse is important.
A slight time shift is acceptable, there is a skew between the two signals, and even if the intermediate pulse is slightly shifted, the influence on the recording mark edge position is slight. Therefore, the skew margin between signals can be increased. Further, the state control means can be easily realized. Further, since the transition of each state is performed at the time when the switch is not selected, the change of the modulation data does not affect the optical waveform.

Further, the state can be reliably changed without increasing the number of signal lines, and the light amount control of the light source and various information can be transferred. Furthermore, the number of command signal lines can be reduced. In addition, since it is possible to correct even if there is a skew between two signals, the deviation of the optical modulation waveform from a desired value can be further reduced. And the adjustment of the delay amount can be easily realized.

[0167]

As described above, according to the light source driving apparatus of the present invention, the deviation of the optical modulation waveform from a desired value due to the distortion or skew of the optical modulation control signal waveform is suppressed.
Even with demands such as high-speed information recording and high-density recording on an information recording medium, the present invention can be realized without causing problems such as an increase in cost and a decrease in performance.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of an information recording / reproducing apparatus to which a light source driving device according to the present invention is applied.

FIG. 2 is a block diagram showing an internal configuration of a signal processing unit 104 shown in FIG.

FIG. 3 shows an LD control unit 9 and an LD drive unit 12 shown in FIG.
1 is a configuration diagram of an LD drive integrated circuit 1 in which is integrated.

4 is a waveform chart showing an example of an output signal of each section of the LD drive integrated circuit 1 shown in FIG.

5 is a state transition diagram of the sequencer 21 shown in FIG.

FIG. 6 is a block diagram showing another configuration example of the modulation unit 23 shown in FIG.

FIG. 7 is a block diagram showing another configuration example of the bias current control unit 27 shown in FIG.

FIG. 8 is a diagram illustrating an example of a drive current-light output characteristic.

FIG. 9 is a diagram showing an example of an optical modulation waveform.

10 is a waveform chart showing another example of the output signal of each section of the LD drive integrated circuit 1 shown in FIG.

FIG. 11 is a block diagram showing still another configuration example of the modulation unit 23 shown in FIG.

FIG. 12 is a waveform chart showing output signals of respective units of the modulation unit 23 shown in FIG.

FIG. 13 is a diagram for explaining an optical waveform disturbance based on a shift in switch timing of an LD drive current.

FIG. 14 is a diagram illustrating an example of each signal waveform used for describing the operation of the bias current control unit 27 illustrated in FIG. 3;

FIG. 15 is a diagram showing a configuration of an LD modulation signal generation unit 10 shown in FIG.

16 is a diagram illustrating a detailed configuration example of the inside of a run length detection unit 111 illustrated in FIG. 15;

17 is a waveform diagram of a signal output from each unit in the run length detection unit 111 shown in FIG.

FIG. 18 is a timing chart showing a relationship between drive waveform generation information and an optical waveform in this embodiment.

FIG. 19 is a table showing a combination example of drive waveform generation information for each of a plurality of pieces of timing information.

20 is a drive waveform generation information holding unit 11 shown in FIG.
2 is a diagram illustrating a detailed internal configuration example of FIG.

21 is a timing signal generator 113 shown in FIG.
2 is a diagram illustrating a detailed internal configuration example of a modulation signal generation unit 114. FIG.

FIG. 22 is a timing signal generator 113 shown in FIG. 21;
FIG. 4 is a waveform diagram of signals output from each unit of the modulation signal generation unit 114.

FIG. 23 is a waveform diagram of signals output from respective units of the timing signal generator 113 and the modulation signal generator 114 shown in FIG. 21;

FIG. 24 is an explanatory diagram showing operations of two sequencers in the timing control section 160 shown in FIG.

FIG. 25 is a waveform chart for explaining signal deletion processing in the timing pulse signal control unit 165 shown in FIG. 21;

26 shows a STEN timing pulse signal and A by the STEN timing pulse generator 170 shown in FIG. 21;
FIG. 9 is a waveform chart for explaining an example of generation of an APC timing pulse signal by a PC timing pulse generation unit 171.

FIG. 27 is a block diagram illustrating a configuration example of an embodiment in which an error detection unit and an error processing unit are added to the LD modulation signal generation unit 10 illustrated in FIG. 2;

FIG. 28 is a diagram illustrating a configuration example of a state command generation unit and a command decoder according to another embodiment of the present invention.

29 is a waveform diagram of a signal output from each unit shown in FIG. 28.

FIG. 30 is a diagram illustrating a configuration example of another embodiment of a modulation unit and a sequencer.

31 is a state transition diagram of state machines SM0 to SM2 provided in the sequencer 301 shown in FIG.

32 is a waveform chart of a signal output from each unit shown in FIG. 30.

FIG. 33 is a state transition diagram of state machines SM0 to SM2 in still another embodiment of the modulation unit and the sequencer.

FIG. 34 is a diagram illustrating another waveform example of a signal output from each unit in still another embodiment of the modulation unit and the sequencer.

FIG. 35 is a diagram showing a configuration of still another embodiment of the modulation unit.

[Explanation of symbols]

1: LD drive integrated circuit 2: light reception signal processing unit 4: RF selection unit 6: wobble signal generation unit 9: LD control unit 10: LD modulation signal generation unit 12: LD drive unit 13: servo signal calculation processing unit 14: servo Processor 15: Wobble signal processing unit 16: RF signal processing unit / PLL unit 17: WCK generation unit 18: Rotation control unit 19: Controller 20: Servo driver 21: Sequencer 22: Command decoder (CMDDecoder) 23: Modulation unit (Data-Modulation) 24, 309, 325: Current adder 25: Current driver 26: PD amplifier (PD-AMP) 27: Bias current controller (Bias-Contro)
l) 28: Differential quantum efficiency controller (η-Control) 29: Bias current selector (MUX) 30: High-frequency modulator (HF-Modulation) 33: Controller 40: PbDAC 41: PtpDAC 42, 44, 54, 96 , 323, 324: switch 43: scale DAC (Scale DAC) 45, 46: current amplifier 47: current-voltage converter (I
/ V) 48, 65: MUX 49: Offset DAC (Offset DAC) 50: Adder 51: Gain switching amplifier (X1 / X4 / X8 / X16)
AMP) 52: P-BDAC 53: P-PDAC 55: Error amplifier 56: S / H integrator (S / H Integra.) 57: Sample and hold circuit (S / H) 58: Difference device 59: etarefDAC 61: Comparator (Comp) 62: Counter (Count
t) 63: FreqDAC 64: VCO 66: HFBDAC 67: Buffer amplifier 70: Bias scale DAC (BSscaleDAC) 71: Bias DAC (BiasDAC) 80a: PrDAC 80b: PeDAC 80c: PbDAC 80d: PclDAC 81a: PeDAC DAC: 81Pac DAC PmpDAC 81d: PlpDAC I0, I0a to I0d, I1, I1a to I1d: current 82, 83, 84, 306 to 308, switch 90: Pb + DAC 91: PbDAC 92: Pt + DAC 93: PtDAC 94, 95: adder ILD: drive Current 100: information recording medium 101: pickup 102: light source (LD) 103: light receiving unit 104: signal processing unit 105: rotation driving unit 106: controller 110: PL Part 111: run-length detector (RunLength D
et. 112): Drive waveform generation information holding unit (Strategy)
Memory 113: timing signal generator 114: modulation signal generator 115: state signal generator (STEN Gen.) 116: state command generator (STCmd Ge)
n. 117): Sample signal generator (Sample Timi)
ng Gen. 118: control unit 120: M frequency divider (1
/ M) 121: Phase comparator (PC) 122: Loop filter (Filter) 123: Oscillator (VCO) 124: N frequency divider (1
/ N) 125: M / N divider 140: Counter (C
counter) 141: Delay circuit (Delay) 142: FIFO control unit (FIFO Ctrl) 143: FIFO 144: Register (R)
eg) 150a to 150n: Address conversion unit (Addr Co)
nverter) 151a to 151n: Selector 152a to 152n:
Memory 154: Register access control unit (Register)
Access Control 160: Timing control unit (Timing Ctrl) 161, 162: Timing calculation units 163a to 163d: Counters 164a to 164d: Phase selection signal holding unit (Reg) 165: Timing pulse signal control unit 166a to 166d: Clock selectors 167a to 167d: flip-flop 170: STEN timing pulse generator 171: APC timing pulse generator 180: error detector 181: error processor 182: second error detector 190: state command generator (STCmd Ge)
n. 191: Command Decoder (CMD Decoder) 300: Command Decoder (CMD Decoder) 301: Sequencer 302, 319: Modulator 303, 320: P0
DAC 304, 321: P1 DAC 305, 322: P2
DAC IoutSel: selection signal PD1 to PD5: light receiving units LD1, LD2: light source

Continuation of front page    F term (reference) 5D090 AA01 BB02 BB03 BB04 BB05                       BB10 CC01 CC02 CC16 DD03                       EE01 FF11 FF21 KK04 KK05                       LL08                 5D119 AA06 AA22 AA23 AA24 AA40                       AA41 BA01 BB01 BB02 BB03                       BB04 BB05 DA01 DA05 EA02                       EA03 FA05 HA04 HA12 HA41                       HA45 HA47 HA49 HA52 HA60                       HA68                 5D789 AA06 AA22 AA23 AA24 AA40                       AA41 BA01 BB01 BB02 BB03                       BB04 BB05 DA01 DA05 EA02                       EA03 FA05 HA04 HA12 HA41                       HA45 HA47 HA49 HA52 HA60                       HA68

Claims (11)

[Claims] 1. A light source driving device for causing a light source to emit light at a multi-level irradiation level, wherein the light source driving device controls a state corresponding to the irradiation level, and shows a part of a change timing of the irradiation level of the light source. Controlling the transition of the state based on the modulation signal and the second modulation signal indicating the remaining part of the change timing of the irradiation level of the light source and a preset transition rule, and the state selected by the control. State control means for generating modulation data corresponding to the above, and modulation for modulating a drive current of the light source based on the modulation data generated by the state control means, the first modulation signal and the second modulation signal. And a light source driving device. 2. A light source driving device that emits light at a multi-level irradiation level and transmits one piece of information by a plurality of pulse trains, wherein a state corresponding to the irradiation level is controlled. Controlling the state transition based on a first modulation signal indicating a change timing of a first half pulse and a second modulation signal indicating a change timing of a second half pulse of the pulse train and a preset transition rule, State control means for generating modulation data corresponding to the state selected by the control, and the light source of the light source based on the modulation data, the first modulation signal and the second modulation signal generated by the state control means. A light source driving device, comprising: modulation means for modulating a driving current. 3. A light source driving device that emits light at a multi-level irradiation level and transmits one piece of information by a plurality of pulse trains, wherein a state corresponding to the irradiation level is controlled. The first modulation signal indicating the change timing of the first half pulse and the second half pulse, the second modulation signal indicating the change timing of the middle pulse of the pulse train, and the transition of the state based on a preset transition rule. Controlling, a state control means for generating modulation data corresponding to the state selected by the control, based on the modulation data generated by the state control means and the first modulation signal and the second modulation signal A light source driving device, comprising: a modulation unit for modulating a driving current of the light source. 4. The light source driving device according to claim 1, wherein the state control unit controls three state groups each including a part of the state. , Respectively, and generates first to third modulated data, wherein the modulating means is configured to generate the first to third modulated data according to a combination of the first modulated signal and the second modulated signal. A light source driving device for selecting a third modulation data to modulate a driving current of the light source. 5. The light source driving device according to claim 1, wherein at least one of the first modulation signal and the second modulation signal indicates a transition of the state. A light source driving device characterized in that a light source is inserted. 6. The light source driving device according to claim 1, further comprising: a light source control unit configured to sample a predetermined irradiation level of the light source and control a light amount of the light source; A pulse indicating a timing for sampling the predetermined irradiation level is inserted into at least one of the modulation signal and the second modulation signal. 7. The light source driving device according to claim 1, further comprising: a light source control unit configured to sample a predetermined irradiation level of the light source and control a light amount of the light source; A pulse indicating a timing for instructing the transition of the state to at least one of the modulation signal and the second modulation signal and sampling the predetermined irradiation level is inserted. Light source drive. 8. The light source driving device according to claim 1, wherein a plurality of pulses are inserted into at least one of the first modulation signal and the second modulation signal. A light source driving device wherein information is transferred based on the presence or absence of a plurality of pulses or the number of pulses. 9. The light source driving device according to claim 1, wherein a plurality of pulses are inserted into at least one of the first modulation signal and the second modulation signal. A light source driving device comprising command demodulation means for demodulating a command signal transmitted in synchronization with a modulation signal into which a pulse is inserted. 10. The light source driving device according to claim 1, wherein delay adjusting means adjusts a delay amount of at least one of the first modulation signal and the second modulation signal. A light source driving device, comprising: 11. The light source driving device according to claim 1, wherein a delay amount of at least one of the first modulation signal and the second modulation signal is adjusted and output. A light source driving device comprising a modulation signal generating means.