JP2003344455A - Waveform measuring device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a waveform measuring device capable of suppressing power consumption during a measurement waiting time. <P>SOLUTION: This waveform measuring device for storing in a memory, waveform data acquired when a memory control part converts a measuring waveform by an AD conversion part based on a trigger signal at an operation speed corresponding to the frequency of a clock signal is characterized by having a clock output part for outputting a high-frequency clock signal when the trigger signal is inputted within a prescribed time, and outputting a low-frequency or constant-level clock signal when the trigger signal is not inputted within the prescribed time. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform measuring device for measuring a waveform to be measured at an operating speed corresponding to the frequency of a clock signal and storing it as waveform data.
The present invention relates to a waveform measuring device that suppresses power consumption while waiting for measurement.

[0002]

2. Description of the Related Art A waveform measuring device converts a waveform to be measured into digital data by an AD converter, stores the digital data in a memory as waveform data, and further reads the waveform data stored in the memory as necessary. The read waveform data and the analysis result of the waveform data are displayed on the display screen of the display unit, and examples thereof include a digital oscilloscope and a digital power meter.

FIG. 3 is a diagram showing a configuration example of a conventional waveform measuring apparatus. In FIG. 3, the clock output unit 1 has a clock generator 1a and a frequency conversion means 1b and outputs a clock signal of a desired frequency. Clock generator 1a
Is an oscillator, which generates and outputs a reference clock signal. The frequency conversion means 1b is, for example, a frequency divider or a phase locked loop circuit, and performs at least one of frequency division and multiplication on the frequency of the reference clock signal from the clock generator 1a, and outputs the clock signal.

The input circuit 2 receives the waveform to be measured and outputs the waveform to be measured as a signal having a desired amplitude level. A
The D conversion unit 3 is, for example, a bipolar type capable of high-speed sampling, operates at a sampling rate corresponding to the frequency of the clock signal from the clock output unit 1, and converts the signal output from the input circuit 2 into digital data. Output. Generally, the input circuit 2 has a plurality of channels, and the AD converter 3 is also provided for each input circuit 2, but only one channel is shown.

The trigger detection circuit 4 outputs a trigger signal according to the signal from the input circuit 2. The memory control unit 5
The digital data from the AD conversion unit 3 is output as waveform data by the trigger signal from the trigger detection circuit 4 at the operation speed corresponding to the frequency of the clock signal from the clock output unit 1.

The memory control section 5 has three types of modes for outputting digital data as waveform data: a single trigger mode, a normal trigger mode, and an auto trigger mode. In general, single trigger mode
Used to measure single-shot phenomena. Further, the normal trigger mode and the auto trigger mode are used to measure a phenomenon that repeatedly occurs.

The memory 6 is, for example, a plurality of SRAMs.
(Static Random Access Memory) 6a, and stores a desired number of waveform data output from the memory control unit 5 at an operation speed corresponding to the frequency of the clock signal from the clock output unit 1.

The operation unit 7 is a button or a rotary knob for instructing display conditions, analysis conditions, etc., and outputs an operation signal each time it is operated. The display processing unit 8 reads the waveform data of the memory 6, performs desired processing on the waveform data according to an instruction from the operation unit 7, generates display data, and displays the display data on the display unit 9.

The operation of such an apparatus will be described. The clock generator 1a of the clock output unit 1 generates a clock signal and outputs it to the frequency conversion means 1b.

Then, the frequency conversion means 1b converts the clock signal from the clock generator 1a into a clock signal of a desired frequency and outputs it to the AD conversion section 3, the memory control section 5, and the memory 6. Here, the frequency of the clock signal output from the frequency conversion unit 1b may be different in each of the AD conversion unit 3, the memory control unit 5, and the memory 6, and conversion is performed so that the operating speed becomes optimum.

On the other hand, the input circuit 2 attenuates or amplifies the measured waveform to a desired amplitude level and outputs it to the AD conversion section 3 and the trigger detection circuit 4. The AD conversion unit 3 operates at a sampling rate corresponding to the frequency of the clock signal from the clock output unit 1, converts the signal from the input circuit 2 into digital data, and outputs the digital data to the memory control unit 5.

When a desired signal, for example, a signal whose signal level changes from negative to positive, is input from the input circuit 2, the trigger detection circuit 4 outputs a trigger signal to the memory control section 5. Then, the memory control unit 5 operates in the auto trigger mode, and stores digital data for a desired time among the digital data from the AD conversion unit 3 as waveform data in the desired SRAM 6a of the memory 6 by the trigger signal. . If the trigger signal is not input within a fixed time (called a timeout time), digital data is stored in the memory 6 as waveform data after the timeout time even if the trigger signal is not input.

Further, since the sampling rate of the AD conversion unit 3 is generally much higher than the operation speed of the memory 6, the memory control unit 5 sequentially stores the digital data from the AD conversion unit 3 in the memory 6. The data is divided into individual SRAMs 6a and stored. For example, each piece of digital data from the AD conversion unit 3 is converted into d1, d2, ..., Di, ..., dn (i,
If n: integer, i <n), the memory control unit 5 stores the data d1 in the first SRAM 6a and the second SRAM 6a.
The data d2 and the data di are stored in the i-th SRAM 6a. In this way, the high sampling rate A
The data d1 to dn from the D converter 3 are stored in the memory 6 operating at low speed.

Then, the display processing unit 8 reads the waveform data from the memory 6 in accordance with the display conditions input via the buttons of the operation unit 7 or the rotary knob, and performs desired processing to display the display screen of the display unit 9. To display.

[0015]

Such a device is
Electric power is consumed in each device such as the D conversion unit 3, the memory control unit 5, the memory 6, and the display unit 9. Therefore, even if the trigger signal is not generated during the measurement standby mode that does not require measurement, for example, in the auto trigger mode, and a considerable amount of time has elapsed after the timeout time, or the observer does not intend to perform the measurement. Even if the device is measuring,
The waveform measuring device consumes power.

An example of suppressing power consumption by turning off the display screen of the display unit 9 in order to suppress power consumption is disclosed in Japanese Patent Laid-Open No. 8-29.
No. 2212 and the like.

However, in recent years, it has been required to increase the capacity of the memory 6 in order to measure the waveform to be measured for a long time, and the SRAM 6a is used very much. Further, the memory control unit 5 that controls the large-capacity memory 6 is also complicatedly composed of many parts, and consumes a large amount of power.

The power consumption will be described in detail below.
When the size of the display screen of the display unit 9 of the waveform measuring device is about 8.4 type, the power consumption of the display unit using the cathode ray tube is about 1
It is 2 W, and the power consumption of the display unit using the liquid crystal which has been popularized in recent years is about 5 W.

On the other hand, although the power consumption varies depending on the frequency of the clock signal, the capacity of the memory 6 becomes several M words (1 word is 8 bits to 32 bits and differs depending on the application), and a general-purpose SRAM which is generally used is used. When 64 pieces are used, the total power consumption is about 25W.
That is, the ratio of power consumption in the device by the memory 6 and the memory control unit 5 is much higher than that in the display unit 9. Therefore, as the number of SRAMs 6a increases, the ratio of power consumed during the measurement standby also becomes very large.

Further, in order to measure a large number of measured waveforms at the same time, the number of measurement channels including the AD conversion section 3 is increased, and the ratio of power consumed during the measurement standby is also increased.

Therefore, an object of the present invention is to realize a waveform measuring apparatus that suppresses power consumption during measurement standby.

[0022]

The invention according to claim 1 is
In a waveform measuring device in which a memory control unit stores waveform data in which a measured waveform is converted by an AD conversion unit in a memory at an operation speed corresponding to a frequency of a clock signal with reference to the trigger signal within a predetermined time. Is input, the clock signal having a high frequency is output, and if the trigger signal is not input within a predetermined time, the clock output unit outputs the clock signal having a low frequency or a constant level. It is a thing.

According to a second aspect of the present invention, in the first aspect of the invention, the clock output section inputs the clock generator for generating and outputting the reference clock signal, and the reference clock signal of the clock generator. It has a frequency conversion means for converting a frequency and outputs it as a clock signal, and a clock control means for controlling the frequency of the frequency conversion means according to a time interval when a trigger signal is input and the trigger signal is input. It is what

According to a third aspect of the present invention, the operating speed corresponds to the frequency of the clock signal and the trigger signal is used as a reference.
In the waveform measuring device in which the memory control unit stores the waveform data obtained by converting the waveform to be measured by the AD conversion unit in the memory, and the operation signal of the operation unit is input within a predetermined time in the waveform measurement device operated by the operation signal of the operation unit And a clock output unit that outputs the clock signal of a high frequency and outputs the clock signal of a low frequency or a constant level when the operation signal of the operation unit is not input within a predetermined time. Is.

According to a fourth aspect of the present invention, in the third aspect of the invention, the clock output section inputs a clock generator for generating and outputting a reference clock signal, and the reference clock signal of the clock generator. Frequency conversion means for converting the frequency and outputting as a clock signal, and the operation signal is input, by the time interval when the operation signal is input,
And a clock control means for controlling the frequency of the frequency conversion means.

According to a fifth aspect of the invention, in the invention according to any one of the first to fourth aspects, the clock output section outputs a clock signal to at least the memory.

According to a sixth aspect of the invention, in the fifth aspect of the invention, the memory is an SRAM.

According to a seventh aspect of the invention, in the invention according to any one of the first to sixth aspects, the clock output section is AD.
It is characterized by outputting a clock signal to the conversion unit.

The invention described in claim 8 is characterized in that, in the invention described in claim 7, the AD converter is of a bipolar type.

According to a ninth aspect of the present invention, in the invention according to any one of the first to eighth aspects, the clock output section outputs a clock signal to the memory control section.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. Here, the same parts as those in FIG. 3 are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 1, a clock output unit 1
0 is provided in place of the clock output unit 1 and outputs a high-frequency clock signal when the trigger signal of the trigger detection circuit 4 is input within a predetermined time and outputs the trigger signal of the trigger detection circuit 4 within the predetermined time. If is not input, a constant level clock signal is output.

The clock output unit 10 includes the clock generator 1
1, a frequency conversion means 12 and a clock control means 13. The clock generator 11 is an oscillator and generates and outputs a reference clock signal.

The frequency conversion means 12 is, for example, a frequency divider or a phase lock loop circuit, and is a clock generator 11.
The frequency of the reference clock signal from is divided or multiplied, and the clock signal is output to each of the AD converter 3, the memory control unit 5, and the memory 6.

The clock control means 13 has a timer 13a, receives the trigger signal from the trigger detection circuit 4, and based on the count value of the timer 13a, the frequency conversion means 1
Control 2 The timer 13a counts the time interval at which the trigger signal is input, and resets the count value when the trigger signal is input.

The operation of the apparatus shown in FIG. 1 will be described next. When a desired signal is input from the input circuit 2, the trigger detection circuit 4 outputs a trigger signal to the clock control unit 13 and the memory control unit 5 operating in the auto trigger mode.

On the other hand, the clock generator 11 of the clock output unit 10 generates a reference clock signal and outputs it to the frequency conversion means 12. Further, the timer 13a of the clock control means 13 resets the count value each time a trigger signal is input from the trigger detection circuit 4, and counts the time interval until the next trigger signal is input.

Further, the frequency conversion means 12 divides or multiplies the reference clock signal from the clock generator 11, converts the frequency, and outputs it to the AD conversion section 3, the memory control section 5, and the memory 6. Here, the frequency conversion means 12
The frequency of the clock signal output from the AD converter 3 may be different in each of the AD converter 3, the memory controller 5, and the memory 6, and the clock signal is converted to have an optimum operation speed.

Next, a case where the trigger signal is not input from the trigger detection circuit 4 within a fixed time will be described. When the trigger signal is not input to the clock control unit 13 for a certain period of time and the count value of the timer 13a exceeds a desired value (for example, a time period after which a specific time period elapses after the time-out period),
The clock control unit 13 controls the frequency conversion unit 12, and the frequency conversion unit 12 masks the reference clock signal from the clock generator 11 to supply a low level or high level constant level clock signal to the AD conversion unit 3 and memory control. Output to the unit 5 and the memory 6.

As a result, the operations of the frequency conversion unit 12, the AD conversion unit 3, the memory control unit 5 and the memory 6 are stopped and the sleep state is entered.

When the trigger signal from the trigger detection circuit 4 is input to the clock control means 13 again, the count value of the timer 13a is reset and the clock control means 13 causes the frequency conversion means 12 to operate. Resume. As a result, each of the AD conversion unit 3, the memory control unit 5, and the memory 6 restarts its operation.

Here, when the trigger signal for resuming the output of the clock signal is input to the clock control means 13, each of the frequency conversion means 12, the AD conversion section 3, the memory control section 5 and the memory 6 is in the sleep state. However, when the measurement is performed in the auto trigger mode, since the repeated waveform is measured, it does not matter if the waveform data cannot be acquired when the measurement is restarted.

Further, in the operation of such a device, the clock control means 13 causes the frequency conversion means 12 to output a low level or high level clock signal according to the time interval of the trigger signal from the trigger detection circuit 4, and AD conversion is performed. In addition to putting the unit 3, the memory control unit 5, and the memory 6 into the sleep state,
Since it is the same as the device shown in FIG. 3, its description is omitted.

As described above, in the auto-trigger mode, the clock control means 13 sets the output of the frequency conversion means 12 to a constant level unless the trigger signal from the trigger detection circuit 4 is input within a fixed time. The unit 3, the memory control unit 5, and the memory 6 can be put into a sleep state. As a result, it is possible to suppress the power consumption during the measurement standby. Therefore, the cost of power consumption can be reduced and the measurement time of an apparatus using a battery such as a battery can be lengthened.

Further, in the recent waveform measuring apparatus, the number of AD conversion units 3 is increased by the increase in the number of measurement channels, and the memory 6 is used.
Increase the number of SRAM 6a to increase the capacity of
Due to the increase in the circuit scale of the memory control unit 5 due to the increase in the SRAM 6a, the power consumption ratios of the AD conversion unit 3, the memory control unit 5, and the memory 6 in the waveform measuring device are increasing. In such a device, the clock control unit 13 keeps the output of the frequency conversion unit 12 at a constant level during the measurement standby, so that the AD conversion unit 3, the memory control unit 5, and the memory 6 are provided.
Can be put to sleep. For example, the power consumption of the memory 6 in the sleep state is reduced by about 30 to 50% compared to the power consumption. As a result, it is possible to further reduce the power consumption during the standby for measurement as compared with the display unit 9.

Further, since the AD conversion unit 3 uses a bipolar type, unlike the unipolar type AD conversion unit, the temperature change of the AD conversion unit 3 itself is small even in the sleep state. As a result, the error in the value of the digital data before and after the measurement is restarted is small.

Further, since the memory 6 uses the SRAM, unlike the DRAM (Dynamic Random Access Memory), the stored waveform data is not erased even in the sleep state. Thereby, the waveform data before the measurement is restarted can be stored.

Further, since the supply of the clock signal is stopped and the sleep state is set in the standby state for the measurement, it is not necessary to turn off the power supply once in order to suppress the power consumption, and then to turn on the power supply again when the measurement is restarted. As a result, when the power is turned on again, the power-on drift and the fluctuation of the DC accuracy, which cause the measurement error, do not occur. Therefore, the measurement result of the waveform data does not vary before and after the measurement standby.

The present invention is not limited to this, and may be as follows. (1) Although a digital oscilloscope has been taken as an example of the waveform measuring device, the AD conversion unit 3 includes the clock output unit 10.
Waveform measurement of a configuration in which the input signal is converted into digital data by operating at a sampling rate corresponding to the frequency of the clock signal, and the memory 6 stores the data based on the AD conversion unit 3 at the operating speed corresponding to the frequency of the clock signal. It can be applied to all devices.

(2) Although the clock control means 13 sets the count value at which the output of the frequency conversion means 12 is stopped to be the time after which a specific time elapses after the time-out time, the stop count value is made equal to the time-out time. Good. This makes it possible to further reduce the power consumption during the measurement standby.

(3) The trigger detection circuit 4 is configured to detect the trigger condition with the signal from the input circuit 2 and output the trigger signal. However, a signal is input from an external device (not shown),
The trigger condition may be detected by a signal input from an external device (not shown).

(4) While waiting for measurement, the clock output unit 10
Shows a configuration in which a clock signal of a constant level is output to each of the AD conversion unit 3, the memory control unit 5, and the memory 6 to enter the sleep state, but at least the AD conversion unit 3, the memory control unit 5, and the memory 6 are included. It is also possible to output a constant level clock signal to one and put it in a sleep state during the measurement standby.

(5) The frequency conversion means 12 frequency-converts the clock signal of the clock generator 11 so that each of the AD converter 3, the memory controller 5, and the memory 6 operates at an optimum speed during measurement. However, if the frequency of the reference clock signal of the clock generator 11 is maintained, the frequency conversion means 12 may not be provided. In this case, the clock control means 13 uses the clock generator 11
Stop the output of.

(6) If the clock control means 13 does not input the trigger signal within the fixed time, the frequency conversion means 12
Although the configuration in which the low-level or high-level clock signal is output has been described above, the configuration may be such that the clock signal having a frequency lower than the frequency output during measurement is output to the frequency conversion means 12.

(7) In the apparatus shown in FIG. 1, the clock control means 13 controls the clock signal at time intervals of the trigger signal from the trigger detection circuit 4, but the operation unit 7 is used instead of the trigger signal. The clock control means 13 may control the output of the clock signal at the time interval of the operation signal output from. That is, the configuration is as shown in FIG. An operation signal output for each operation of the button or rotary knob of the operation unit 7 is output to the display processing unit 8 and the clock control unit 13.

Such an apparatus is almost the same as the operation of the apparatus shown in FIG. 1, but a different operation is performed every time the button or the like of the operation section 7 is operated instead of the trigger signal from the trigger detection circuit 4. Depending on the time interval of the output operation signal,
The clock control means 13 controls the output of the frequency conversion means 12.

As described above, the clock control unit 13 sets the output of the clock signal of the frequency conversion unit 12 to a constant level unless the operation signal from the operation unit 7 is input for a fixed time, so that the AD conversion unit 3 and the memory control unit. The unit 5 and the memory 6 can be put to sleep. As a result, it is possible to suppress the power consumption during the measurement standby. Therefore, the cost of power consumption can be reduced and the measurement time of an apparatus using a battery such as a battery can be lengthened.

[0057]

The present invention has the following effects. According to claim 1, 2, 5 to 9, the clock output unit 1
When the trigger signal is 0, if the trigger signal is not input for a predetermined time, the frequency of the clock signal is set to a low level or a constant level, so that the power consumption of the device operating at the operating speed corresponding to the frequency of the clock signal can be suppressed. .

If the trigger signal is not input for a predetermined time, the frequency of the clock signal is lowered or the clock signal has a constant level. Therefore, in order to suppress power consumption, the power is turned off once, and the power is turned on again when the measurement is restarted. No need. As a result, when the power is turned on again, the power-on drift and the fluctuation of the DC accuracy, which cause the measurement error, do not occur, and accurate measurement can be performed.

According to claims 3 to 9, the clock output unit 1
If the operation signal is 0, if the operation signal is not input for a predetermined time, the frequency of the clock signal is set to a low level or a constant level, so that the power consumption of the device operating at the operating speed corresponding to the frequency of the clock signal can be suppressed. .

If the operation signal is not input for a certain period of time, the frequency of the clock signal is lowered or the clock signal of a certain level is used. Therefore, the power supply is turned off once in order to suppress power consumption, and the power supply is turned on again when the measurement is restarted. No need. As a result, when the power is turned on again, the power-on drift and the fluctuation of the DC accuracy, which cause the measurement error, do not occur, and accurate measurement can be performed.

According to the sixth aspect, since the SRAM is used as the memory, unlike the DRAM, the stored waveform data is not erased even if the frequency of the clock signal is low or the clock signal has a constant level. Thereby, the waveform data before the measurement is restarted can be stored.

According to the eighth aspect, since the bipolar type AD converter is used, unlike the unipolar type AD converter, the temperature change of the AD converter itself due to the frequency of the clock signal is small. As a result, there is little error in the value of digital data depending on the frequency of the clock signal.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a conventional waveform measuring device.

[Explanation of symbols]

3 AD converter 5 Memory controller 6 memory 6a SRAM 10 Clock output section 11 clock generator 12 Frequency conversion means 13 Clock control means 13a timer

Claims (9)

[Claims] 1. A waveform measuring device for storing, in a memory, waveform data obtained by converting a waveform to be measured by an AD conversion unit by a memory control unit at an operating speed corresponding to a frequency of a clock signal with a trigger signal as a reference, at a predetermined time. And a clock output unit that outputs the clock signal having a high frequency when the trigger signal is input, and outputs the clock signal having a low frequency or a constant level when the trigger signal is not input within a predetermined time. A waveform measuring device characterized in that 2. The clock output section includes: a clock generator that generates and outputs a reference clock signal; and frequency conversion means that inputs the reference clock signal of the clock generator, converts the frequency, and outputs the clock signal. 2. The waveform measuring apparatus according to claim 1, further comprising a clock control unit that controls a frequency of the frequency conversion unit according to a time interval when the trigger signal is input and the trigger signal is input. 3. The waveform data obtained by converting the waveform to be measured by the AD conversion unit by the memory control unit is stored in the memory at the operating speed corresponding to the frequency of the clock signal with the trigger signal as a reference, and the operation signal from the operation unit is used. In the operated waveform measuring apparatus, when the operation signal of the operation unit is input within a predetermined time, the clock signal of high frequency is output, and when the operation signal of the operation unit is not input within the predetermined time, the signal is low. A waveform measuring apparatus having a clock output section for outputting the clock signal having a frequency or a constant level. 4. The clock output section includes a clock generator that generates and outputs a reference clock signal, and frequency conversion means that inputs the reference clock signal of the clock generator, converts the frequency, and outputs the clock signal. 4. The waveform measuring device according to claim 3, further comprising: a clock control unit that controls the frequency of the frequency conversion unit according to a time interval when the operation signal is input and the operation signal is input. 5. The clock output section outputs a clock signal to at least a memory.
The waveform measuring device according to any one of 1. 6. The memory is an SRAM (Static Random Ac).
6. The waveform measuring device according to claim 5, which is a cess memory). 7. The waveform measuring device according to claim 1, wherein the clock output section outputs a clock signal to the AD conversion section. 8. The waveform measuring device according to claim 7, wherein the AD conversion unit is of a bipolar type. 9. The waveform measuring device according to claim 1, wherein the clock output unit outputs a clock signal to the memory control unit.