JP2003338759A - Output compensation circuit for dac - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit for a DAC (D/C Converter), having stationary frequency characteristics with respect to output voltage change independent of peripheral circuits connected thereto, when an inputted digital value changes by a significant amount. <P>SOLUTION: The output of a first OP-amp (operating amplifier) 13 goes to L level and a capacitance element C1 goes to a charged state as negative input voltage a1 is less than positive input voltage b1, when inputted data bits are stable for example in the state of all '1'. A transistor 16 goes to an off- state while the output of a second OP-amp 23 goes to H level, and a capacitance element C2 goes to a discharged state as a positive input voltage b2 is larger than a negative input voltage a2. A transistor 26 goes to off-state. In this state, if the inputted data bits change to state of all '0', the transistor 16 goes to the off-state, and the transistor 26 goes to on-state, at the same time. The voltage level of an external output terminal falls rapidly from the level of maximum voltage value to the ground level, without delays. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current addition type D
The present invention relates to an AC (digital-analog converter) output correction circuit.

[0002]

2. Description of the Related Art FIG. 6 is a diagram showing the relationship between a conventional current addition type DAC and peripheral circuits. In FIG. 6, the current addition type DAC 1 has, for example, a predetermined number of data bits and 1
A plurality of FF (flip-flop) circuits that are provided in a one-to-one correspondence and take in corresponding data bits by the sampling clock CLK, a positive-phase-side resistor ladder circuit that receives positive-phase outputs of the plurality of FF circuits, and a plurality of FF circuits Reverse-phase side resistance ladder circuit that receives the reverse-phase output, positive-phase output terminal (+) that outputs the positive-phase current I + that was combined in the positive-phase side resistance ladder circuit, and combination in the reverse-phase side resistance ladder circuit And a reversed-phase output terminal (-) for outputting the reversed-phase current I-.

The positive phase output terminal (+) and ground (GND)
A terminating resistance element R1 is connected between and, and a positive phase current I + having a value corresponding to a digital value by a predetermined number of input data bits is voltage-converted by the terminating resistance element R1 and output to the external output terminal 2. It A peripheral circuit 61 is connected to the external output terminal 2. In addition, the negative phase output terminal (-) and ground (G
A terminating resistance element R2 is connected between (ND).
Normally, the negative phase voltage obtained at the negative phase output terminal (-) is not used.

[0004]

By the way, as shown in FIG. 6, the peripheral circuit 61 connected to the external output terminal 2 is
Since the time constant circuit including the resistance element R0 and the capacitance element C0 is provided, it takes some time for the potential of the external output terminal 2 to reach the set value due to the influence of the time constant circuit. The time delay due to this time constant circuit is when all the input data bits change from "1" to all "0", or when all the data bits are "0".
It becomes considerably large when all the values change from "1".
The magnitude of this time delay differs depending on the circuit configuration of the connected peripheral circuit 61. Therefore, conventionally, it has been necessary to set the output current value of the DAC 1 in consideration of the connected peripheral circuit 61 to some extent.

The present invention has been made in view of the above, and the output voltage change when an input digital value changes greatly satisfies a constant frequency characteristic regardless of the load condition of the connected peripheral circuit or the like. DAC that can be
The purpose is to obtain the output correction circuit of.

[0006]

In order to achieve the above object, an output correction circuit of a DAC according to the present invention is connected with a terminating resistance element at each of a positive-phase output terminal and a negative-phase output terminal for input. In the current addition type DAC for converting the positive-phase output current and the negative-phase output current corresponding to the digital value of the predetermined number of data bits into voltage by each of the terminating resistor elements and outputting the converted positive-phase voltage from the external output terminal, A first inverting circuit that inverts and outputs the converted positive-phase voltage, a second inverting circuit that inverts and outputs the converted negative-phase voltage, and an output of the first inverting circuit to a positive-phase input terminal. A first OP amplifier is applied and the converted negative phase voltage is applied to a negative phase input terminal, and an output of the second inverting circuit is applied to a positive phase input terminal, and the converted positive phase voltage is negative phase. Applied to the input end A second OP amplifier, one signal electrode connected to a power supply via a first diode, the other signal electrode grounded, and a first N-type transistor to which the output of the first OP amplifier is applied to a control electrode; Type capacitance element connected in parallel to the transistor and one signal electrode is connected to the power supply, the other signal electrode is grounded via the second diode, and the output of the second OP amplifier is applied to the control electrode. A first P-type transistor, a second capacitance element connected in parallel with the second diode, one signal electrode connected to a power source, and the other signal electrode connected to the positive phase output terminal and the external output terminal. A second P-type transistor connected to a connection line and having a control electrode to which the holding voltage of the first capacitive element is applied, and one signal electrode connected to the positive phase output terminal and the external output terminal. It is connected to,
The other signal electrode is grounded, and the control electrode is provided with a second N-type transistor to which the holding voltage of the second capacitive element is applied.

According to the present invention, when the input data bits are all stable in the state of "1", for example, "output voltage of the first inverting circuit">"converted negative phase voltage" Therefore, the first OP amplifier sets the output to the low level, the first N-type transistor is turned off, and the first
The capacitive element is placed in a charged state via the first diode. As a result, the second P-type transistor is turned off, and the positive-phase output current flows through the termination resistance element, so that the converted positive-phase voltage (maximum value) is output to the external output terminal. On the other hand, since "the output voltage of the second inverting circuit">"the converted positive phase voltage", the second OP amplifier sets the output to a high level, and the first P-type transistor is turned off,
The second capacitive element is placed in a discharged state via the second diode. As a result, the second N-type transistor is turned off. In this state, when the input data bits are all changed to "0", the first capacitive element is charged from the power source through the first diode, and the second P-type transistor is turned off. At the same time, the second capacitive element is charged from the power source through the first P-type transistor, so that the second N-type transistor is turned on and the external output terminal is connected to the ground. As a result, the voltage level of the external output terminal rapidly falls from the level of the maximum voltage value to the ground potential without time delay.

In a DAC output correction circuit according to the next invention, in the above invention, a plurality of the second P-type transistors and a plurality of the second N-type transistors are provided respectively, and each of the plurality of second P-type transistors is provided. , A plurality of first switches connecting one of the signal electrodes and a voltage holding end of the first capacitance element to a control electrode, and the other of the plurality of second N-type transistors. A plurality of second switches for selecting one of the signal electrode and the voltage holding end of the second capacitive element to connect to the control electrode.

According to this invention, in the above invention,
For example, various operation patterns for individually operating the plurality of first switches and the second switches are set in the register, and according to the status of the load connected to the external output terminal,
An appropriate number of transistors can be selected from the plurality of second P-type transistors and second N-type transistors to correct the frequency characteristic of output voltage change to a desired characteristic.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the DAC output correction circuit according to the present invention will be described in detail below with reference to the accompanying drawings.

Embodiment 1. 1 is a circuit diagram showing a configuration of an output correction circuit of a DAC which is Embodiment 1 of the present invention. In FIG. 1, the current addition type DAC 1 is provided, for example, in a one-to-one correspondence with a predetermined number of data bits, and has a plurality of FF (flip-flop) circuits for fetching the corresponding data bits by the sampling clock CLK and a plurality of FFs. A positive phase resistance ladder circuit that receives the positive phase output of the circuit, a negative phase side resistance ladder circuit that receives the negative phase outputs of a plurality of FF circuits, and a positive phase current I + that is combined by the positive phase side resistance ladder circuit are output. The positive phase output terminal (+) and the negative phase output terminal (-) to which the negative phase current I- synthesized by the negative phase side resistance ladder circuit is output.

Then, a terminating resistor element R1 is connected between the connection line between the positive phase output terminal (+) and the external output terminal 2 and the ground (GND), and a digital value by a predetermined number of input data bits is converted into a digital value. The positive phase current I + having the corresponding value is converted into a voltage by the terminating resistance element R1, and the voltage Vo is output to the external output terminal 2. Further, a terminating resistance element R2 is connected between the negative phase output terminal (−) and the ground (GND), and a negative phase current I + having a value corresponding to a digital value by a predetermined number of input data bits is applied to the terminating resistance element. The voltage is converted by R2. The resistance values of the load resistance elements R1 and R2 are assumed to be equal.

In the DAC output correction circuit according to the first embodiment, in such a DAC 1, for example, when all the input data bits are changed from a state of "1" to a state of "0", the data bit is also changed. , The PMOS transistors 11, 14, 1 are used to correct the frequency characteristic of the voltage change speed at the external output terminal 2.
6, 21, 24 and the NMOS transistors 12, 15,
22, 25, 26, the first OP amplifier 13, and the second OP
The amplifier 23 and the capacitive elements C1 and C2 are provided.

The gate electrode of the PMOS transistor 11 is connected to the connection line between the positive phase output terminal (+) of the DAC 1 and the external output terminal 2, and the source electrode is connected to the power supply Vcc. The gate electrode of the NMOS transistor 12 is connected to the drain electrode of the PMOS transistor 11 together with the drain electrode, and the source electrode is connected to the ground (GND). The connection terminal between the drain electrode of the PMOS transistor 11 and the drain electrode of the NMOS transistor 12 is connected to the negative phase input terminal (−) of the first OP amplifier 13.

The PMOS transistor 11 and the diode-connected NMOS transistor 12 form an inverting circuit as a whole. As its inversion potential, it has an offset value “−α” determined by the transistor ratio between the PMOS transistor 11 and the NMOS transistor 12. The offset value “−α” is a value smaller than the LSB of a predetermined number of input data bits.

The positive-phase input terminal (+) of the first OP amplifier 13 is connected to the negative-phase output terminal (-) of the DAC 1 and
The output terminal of the amplifier 13 has an NMOS transistor 15
The gate electrode of is connected. The drain electrode of the NMOS transistor 15 is connected to the drain electrode and the gate electrode of the PMOS transistor 14. NMO
The source electrode of the S transistor 15 is connected to the ground (GND), and the source electrode of the PMOS transistor 14 is connected to the power supply Vcc.

The connection terminal between the drain electrode of the PMOS transistor 14 and the drain electrode of the NMOS transistor 15 is connected to the gate electrode of the PMOS transistor 16. Further, a capacitive element C1 is provided between the connection end of the drain electrode of the PMOS transistor 14 and the drain electrode of the NMOS transistor 15 and the ground (GND). The source electrode of the PMOS transistor 16 is connected to the power supply Vcc. The drain electrode of the PMOS transistor 16 is the positive phase output terminal (+) of the DAC1.
And the external output terminal 2 are connected to each other.

The gate electrode of the PMOS transistor 21 is connected to the negative-phase output terminal (-) of the DAC 1, and the source electrode is connected to the power supply Vcc. The gate electrode of the NMOS transistor 22 is a PMOS together with the drain electrode.
It is connected to the drain electrode of the transistor 21 and the source electrode is connected to the ground (GND). The drain electrode of the PMOS transistor 21 and the NMOS transistor 22
Of the second OP amplifier 23 is connected to the positive-phase input terminal (+) of the second OP amplifier 23. PMOS transistor 21 and diode-connected NMOS transistor 22
Form an inverting circuit as a whole. As the inversion potential, an offset value “+” determined by the transistor ratio of the PMOS transistor 21 and the NMOS transistor 22
I have an α ”. The offset value “+ α” is a value smaller than the LSB of a predetermined number of input data bits.

The connection line between the positive phase output terminal (+) of the DAC 1 and the external output terminal 2 is connected to the negative phase input terminal (-) of the second OP amplifier 23, and the output terminal of the second OP amplifier 23 is The gate electrode of the PMOS transistor 24 is connected. The source electrode of the PMOS transistor 24 is
The drain electrode is connected to the power supply Vcc, and the drain electrode is connected to the drain electrode and the gate electrode of the NMOS transistor 25. The source electrode of the NMOS transistor 25 is
It is connected to ground (GND).

The connection terminal between the drain electrode of the PMOS transistor 24 and the drain electrode of the NMOS transistor 25 is connected to the gate electrode of the NMOS transistor 26. Further, a capacitive element C2 is provided between the connection terminal of the drain electrode of the PMOS transistor 24 and the drain electrode of the NMOS transistor 25 and the ground (GND). The source electrode of the NMOS transistor 26 is connected to the ground (GND), and the drain electrode thereof is the DAC.
1 is connected to the connection line between the positive phase output terminal (+) and the external output terminal 2.

Next, with reference to FIGS. 1 to 4, the operation of the DAC output correction circuit according to the first embodiment configured as described above will be described. 2 is a diagram showing an input waveform of the first OP amplifier shown in FIG. 1 when all the input data bits change from "1" to "0". FIG. 3 is a diagram showing an input waveform of the second OP amplifier shown in FIG. 1 when all the input data bits change from “1” to all “0”. FIG. 4 is a comparison diagram of the frequency characteristics of the correction output according to the first embodiment and the output of the conventional circuit when the input data bits are all changed from "1" to "0".

In FIG. 1, when all the input data bits are stable in the state of "1", the conversion potential of the positive phase output terminal (+) of the DAC1 is "1" for all the data bits. It is at the level of the maximum voltage value corresponding to the digital value at a certain time. The conversion potential of the negative-phase output terminal (-) is at the level of the minimum voltage value corresponding to the digital value when all the data bits are "0".

Since the maximum voltage value from the positive phase output terminal (+) of the DAC 1 is applied to the gate electrode of the PMOS transistor 11, it is in an off operation state. That is, the first
Voltage a applied to the negative-phase input terminal (-) of the OP amplifier 13
1 becomes a voltage level due to the on-resistance of the diode-connected NMOS transistor 12. On the other hand, the voltage b1 of the positive phase input terminal (+) of the first OP amplifier 13 is the minimum voltage value from the negative phase output terminal (−) of the DAC 1, and b1> a1. Therefore, the first OP amplifier 13 sets the output terminal to the low level (hereinafter referred to as “L level”).

As a result, the NMOS transistor 15
Is turned off, the capacitive element C1 has a PMO
It is placed in a state of charging through the S-transistor 14.
The terminal voltage of the capacitive element C1 is at a high level (hereinafter "H level").
It means that the PMOS transistor 1
6 is turned off. The potential of the external output terminal 2 is held at the potential generated in the terminating resistance element R1.

On the other hand, the negative phase input terminal of the second OP amplifier 23
The (-) voltage a2 is the maximum voltage value from the positive phase output terminal (+) of the DAC1. On the other hand, the PMOS transistor 21 is in the on-operation state because the minimum voltage value from the negative-phase output terminal (−) of the DAC 1 is applied to the gate electrode. That is, the positive phase input terminal (+) of the second OP amplifier 23.
Of the voltage b2 of FIG. At this time, b2> a2. Therefore, the output terminal of the second OP amplifier 23 is H
Become a level.

As a result, the PMOS transistor 24
Is turned off, and the capacitive element C2 is placed in a state of discharging through the diode-connected NMOS transistor 25. Since the terminal voltage of the capacitive element C2 is at the L level, the NMOS transistor 26 is turned off.

As described above, when all the input data bits are stable in the state of "1", the PMOS transistor 16 is turned off and the NMOS transistor 26 is turned off. The maximum voltage value corresponding to the digital value when all the data bits output from the positive phase output terminal (+) of the DAC 1 are “1” is output to the external output terminal 2.

On the contrary, when the input data bits are all stable in the state of "0", the potential of the positive phase output terminal (+) of the DAC1 is "0" for all the data bits. It is at the level of the minimum voltage value corresponding to the digital value of. The potential of the negative-phase output terminal (-) is at the level of the maximum voltage value corresponding to the digital value when all the data bits are "1".

Since the minimum voltage value from the positive phase output terminal (+) of the DAC 1 is applied to the gate electrode of the PMOS transistor 11, it is in an ON operation state. That is, the first
The voltage a1 at the negative-phase input terminal (-) of the OP amplifier 13 is almost at the level of the power supply Vcc through the PMOS transistor 11. On the other hand, the positive phase input terminal (+) of the first OP amplifier 13
Is a maximum voltage value from the negative-phase output terminal (−) of the DAC 1 and b1> a1. Therefore, the first O
The output terminal of the P amplifier 13 becomes L level.

As a result, the NMOS transistor 15
Is turned off, the capacitive element C1 is connected to the power source Vcc through the diode-connected PMOS transistor 14.
It is placed in a state of being charged from. Since the terminal voltage of the capacitive element C1 is at the H level, the PMOS transistor 16 is turned off.

On the other hand, the negative phase input terminal of the second OP amplifier 23
The (-) voltage a2 is the minimum voltage value from the positive phase output terminal (+) of the DAC1. On the other hand, the PMOS transistor 21 is in the off-operation state because the maximum voltage value from the negative-phase output terminal (−) of the DAC 1 is applied to the gate electrode. That is, the negative phase input terminal (+) of the second OP amplifier 23.
Is a voltage level due to the on resistance of the diode-connected NMOS transistor 22. At this time, b
2 <a2. Therefore, the output terminal of the second OP amplifier 23 becomes L level.

As a result, the PMOS transistor 24
Is turned on, and the capacitive element C2 is placed in a state of being charged from the power supply Vcc through the PMOS transistor 24. Since the terminal voltage of the capacitive element C2 is at the H level, the NMOS transistor 26 is turned on. The potential of the external output terminal 2 is held at the ground (GND) potential level.

As described above, when all the input data bits are stable in the state of "0", the PMOS transistor 16 is turned off and the NMOS transistor 26 is turned on. The minimum voltage value corresponding to the digital value when all the data bits output from the positive phase output terminal (+) of the DAC1 are "0" is output to the external output terminal 2 as the ground (GND) voltage level. It

Now, the operation when the input data bits change from the state of all "1" to the state of all "0" is as follows. In FIG. 2 showing the input waveform of the first OP amplifier 13, the voltage b1 is a voltage output from the negative-phase output terminal (−) of the DAC 1 and has a characteristic of rising linearly from the minimum voltage value level to the maximum voltage value level. is there. The voltage a1 is the drain electrode of the PMOS transistor 11 and the diode-connected NMOS transistor 12
Is the voltage at the connection end with the drain electrode.

Since the PMOS transistor 11 is in the OFF operation state when the voltage output from the positive phase output terminal (+) of the DAC 1 is the maximum value, the voltage a1 is initially the ON state of the diode-connected NMOS transistor 12. It is at the voltage level due to the resistance. At this time, b1> a1. Since the first OP amplifier 13 outputs the L level and the terminal voltage of the capacitive element C1 becomes the H level, the PMOS transistor 16 is in the off operation state.

When the voltage output from the positive-phase output terminal (+) of the DAC1 changes to the minimum value, the PMOS transistor 11 performs the ON operation, so that the voltage a1 rises toward the maximum value. Since the rising characteristic becomes gentler than the voltage b1, b1> a1, and the first OP amplifier 13 outputs the L level, and the terminal voltage of the capacitive element C1 becomes the H level, so that the PMOS transistor 16 is turned off. .

On the other hand, in FIG. 3 showing the input waveform of the second OP amplifier 23, the voltage a2 is the positive phase output terminal of the DAC1.
This is the voltage output from (+). The voltage b2 is PMOS
The drain electrode of the transistor 21 and the diode-connected N
It is the voltage at the connection end with the drain electrode of the MOS transistor 22.

Since the PMOS transistor 21 is in the ON operation state when the voltage output from the negative phase output terminal (-) of the DAC 1 is at the minimum value, the voltage b2 is almost equal to the power supply Vcc.
Voltage level. At this time, b2> a2. Since the second OP amplifier 23 outputs H level and the terminal voltage of the capacitive element C2 becomes L level, the NMOS transistor 26 is in the OFF operation state.

When the voltage output from the positive phase output terminal (+) of the DAC 1 changes to the minimum value, that is, when the voltage output from the negative phase output terminal (-) changes to the maximum value,
Since the PMOS transistor 21 performs the OFF operation, the voltage b2 falls toward the minimum value. Since the falling characteristic becomes gentler than the voltage a2, b2 <a2, the second OP amplifier 23 outputs the L level, and the terminal voltage of the capacitive element C2 becomes the H level, so that the NMOS transistor 26 is turned on. Become.

In short, when the input data bits are all changed from "1" to all "0", the PMOS transistor 16 is immediately changed from the ON operation state to the OFF operation state. The NMOS transistor 26 immediately changes from the off-operation state to the on-operation state and holds that state. Therefore, the speed of change when the voltage output from the external output terminal 2 changes from the maximum value to the minimum value is accelerated, and good frequency characteristics are obtained.

In FIG. 4, the ideal output 41 is an ideal characteristic when the input data bits are all changed from "1" to "0". It has a fairly steep falling characteristic. On the other hand, the correction output 4
2 is the characteristic obtained by the operation described above.
It can be seen that the characteristics considerably close to the characteristics of the ideal output 41 are obtained. Since the conventional output 43 is affected by the characteristics of the connected peripheral circuit 61 as described in FIG. 6,
It has a fairly gentle fall characteristic. As described above, according to the first embodiment, it can be understood that the frequency characteristic is significantly improved.

The above is the case where all the input data bits are changed from the state of "1" to the state of all "0". On the contrary, all the input data bits are changed from the state of all "0" to all. When the state changes to "1", the same operation is performed, the PMOS transistor 16 immediately changes from the off operation state to the on operation state, and similarly, the NMOS transistor 26 immediately changes from the on operation state to the off operation state. It changes and maintains its state. Therefore, the speed of change when the voltage output from the external output terminal 2 changes from the minimum value to the maximum value is accelerated, and good frequency characteristics are obtained.

At this time, when the input data bits are all changed from "1" to "0",
When the state of all "0" changes to the state of all "1", there is a delay corresponding to the charging / discharging time in the capacitive elements C1 and C2, so that overshoot or undershoot does not occur.

When the input data bits are in an arbitrary state between all "1" and all "0", the first OP amplifier 13 sets the output to the L level, so that the capacitance The terminal voltage of the element C1 is held at the H level, and the PMOS transistor 16 maintains the off operation state. Further, since the second OP amplifier 23 sets the output to the H level, the terminal voltage of the capacitive element C2 is held at the L level,
The NMOS transistor 26 maintains the off operation state.
That is, the output correction circuit does not adversely affect the DA conversion value output from the external output terminal 2.

Embodiment 2. FIG. 5 is a circuit diagram showing the configuration of the DAC output correction circuit according to the second embodiment of the present invention. In addition, in FIG. 5, the same reference numerals are given to the same or similar components as those shown in FIG. Here, the description will focus on the part related to the second embodiment.

As shown in FIG. 5, D according to the second embodiment
In the AC output correction circuit, in the configuration shown in the first embodiment (FIG. 1), the P-type transistor 16 is replaced with P-type transistors 51-1 to 51-n and a switch 52-1.
52-n are provided. Further, instead of the N-type transistor 26, N-type transistors 61-1 to 61-n and switches 62-1 to 62-n are provided.

The switches 52-1 to 52-n select one of the voltage holding end and the source electrode of the capacitive element C1 in the P-type transistors 51-1 to 51-n and connect it to the gate electrode. It has become.

The switches 62-1 to 62-n select one of the voltage holding terminal of the capacitive element C2 and the ground (GND) in the N-type transistors 61-1 to 61-n and connect it to the gate electrode. It is supposed to do.

According to the above configuration, for example, the switches 52-1 to 52-n, 62-1 to 62- are provided in the internal register.
Various operation patterns for individually operating -n are set, and the P-type transistors 51-1 to 51-n and the N-type transistor are preliminarily set according to the load condition of the peripheral circuit or the like connected to the external output terminal 2. It is possible to select and prepare a number of transistors capable of performing appropriate output correction from 61-1 to 61-n.

Further, for example, if it is known that all the input data bits are in the state of "0", then all of the input data bits are in the state of "1", then all of the input "." It is possible to select and operate, from the P-type transistors 51-1 to 51-n, a number of transistors capable of performing appropriate output correction in association with the 1 ″ data bit.

[0051]

As described above, according to the present invention, a terminating resistor element is connected to each of the positive phase output terminal and the negative phase output terminal, and the positive phase signal corresponding to the digital value of a predetermined number of input data bits is input. In a current addition type DAC that converts the output current and the negative-phase output current into voltage by each of the terminating resistance elements and outputs the converted positive-phase voltage from the external output terminal, for example, if all the input data bits are "1", When the state is stable, “the output voltage of the first inverting circuit”> “the converted negative phase voltage” is satisfied, so that the first OP amplifier sets the output to the low level, and the first N-type transistor is in the off operation state. And the first capacitive element is placed in a charged state via the first diode. As a result, the second P-type transistor is turned off, and the positive-phase output current flows through the termination resistance element, so that the converted positive-phase voltage (maximum value) is output to the external output terminal. On the other hand, since "output voltage of second inverting circuit">"converted positive phase voltage", the second OP amplifier sets the output to a high level, the first P-type transistor is turned off, and the second capacitive element is turned off. It is placed in a discharged state via a second diode. As a result, the second N-type transistor is turned off. In this state, when the input data bits are all changed to "0", the first capacitive element is charged from the power source through the first diode, and the second P-type transistor is turned off. At the same time, the second capacitive element is charged from the power source through the first P-type transistor, so that the second N-type transistor is turned on and the external output terminal is connected to the ground. As a result, the voltage level of the external output terminal rapidly falls from the maximum voltage level to the ground potential without time delay. In this way, the frequency characteristic when the output voltage changes greatly can be significantly improved.

According to the next invention, in the above invention, for example, various operation patterns for individually operating the plurality of first switches and the second switches are set in the register and are connected to the external output terminal. It is possible to correct an output voltage change frequency characteristic to a desired characteristic by selecting an appropriate number of transistors from the plurality of second P-type transistors and second N-type transistors according to the load situation.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an output correction circuit of a DAC which is Embodiment 1 of the present invention.

FIG. 2 is a diagram showing an input waveform of the first OP amplifier shown in FIG. 1 when input data bits are all changed from “1” to “0”.

FIG. 3 is a diagram showing an input waveform of the second OP amplifier shown in FIG. 1 when input data bits are all changed from “1” to “0”.

FIG. 4 is a comparison diagram of the frequency characteristics of the correction output according to the first embodiment and the output of the conventional example circuit when all the input data bits change from “1” to all “0”.

FIG. 5 is a circuit diagram showing a configuration of an output correction circuit of a DAC which is Embodiment 2 of the present invention.

FIG. 6 is a diagram showing a relationship between a conventional current addition type DAC and peripheral circuits.

[Explanation of symbols]

1 current addition type DAC (digital-analog converter), 2 external output terminals, 11, 14, 16, 21,
24, 51-1 to 51-n PMOS transistors, 1
2, 15, 22, 25, 26, 61-1 to 61-n N
MOS transistor, 13 1st OP amplifier, 23 2nd OP amplifier, 52-1 to 52-n, 62-1 to 62-
n switch, R1, R2 termination resistance element, C1, C2
Capacitive element.

Claims (2)

[Claims] 1. A terminating resistor element is connected to each of the positive-phase output terminal and the negative-phase output terminal, and a positive-phase output current and a negative-phase output current corresponding to a digital value of a predetermined number of input data bits are supplied to each of the terminating resistors. In a current addition type DAC that converts a voltage by an element and outputs the converted positive phase voltage from an external output terminal, a first inverting circuit that inverts and outputs the converted positive phase voltage, and the converted negative phase A second inverting circuit that inverts and outputs a voltage; and a first OP in which the output of the first inverting circuit is applied to a positive phase input terminal and the converted negative phase voltage is applied to a negative phase input terminal.
An amplifier and a second OP in which an output of the second inverting circuit is applied to a positive phase input terminal and the converted positive phase voltage is applied to a negative phase input terminal.
An amplifier and one signal electrode are connected to a power source via a first diode, the other signal electrode is grounded, and the control electrode is connected to the first O
A first N-type transistor to which the output of the P amplifier is applied, a first capacitive element connected in parallel to the first N-type transistor, one signal electrode connected to a power source, and the other signal electrode connected to a second diode. Is grounded via the second O
A first P-type transistor to which the output of the P amplifier is applied, a second capacitance element connected in parallel to the second diode, one signal electrode connected to a power source, and the other signal electrode connected to the positive phase output terminal. And a second P-type transistor connected to a connection line between the external output terminal and the control electrode to which the holding voltage of the first capacitive element is applied, and one signal electrode of the positive phase output terminal and the external output terminal. Connected to the connection line of the other signal electrode is grounded,
A second N-type transistor to which the holding voltage of the second capacitance element is applied to a control electrode, and an output correction circuit of a DAC. 2. The second P-type transistor and the second N-type transistor
A plurality of type transistors are provided respectively, and in each of the plurality of second P-type transistors, one of the signal electrode and the voltage holding end of the first capacitive element is selected and connected to the control electrode. In each of the plurality of first switches and the plurality of second N-type transistors, one of the other signal electrode and the voltage holding end of the second capacitance element is selected and connected to the control electrode. The output correction circuit of the DAC according to claim 1, further comprising: