JP2003338538A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low-cost semiconductor integrated circuit device in which a chip area is reduced by using p-n junction isolation for isolating side faces. <P>SOLUTION: In the semiconductor integrated circuit device, the chip area is reduced and cost reduction is attained by using an n-isolation region 51a and a p-isolation region 51b formed on an SOI substrate or a buried epitaxial substrate as an n-well region and a p-well region, respectively, and forming a p-source region and an n-source region in the isolation regions 51a and 51b, respectively. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display (hereinafter referred to as FPD) formed by using junction separation.
And a semiconductor integrated circuit device such as a driving IC.

[0002]

2. Description of the Related Art Plasma display panels (hereinafter referred to as P
FPDs such as DPs and electroluminescent displays (hereinafter abbreviated as EL displays) have features of being thin and lightweight, and are being actively developed as next-generation displays. For example, a PDP that has a wide viewing angle and a large screen is strongly expected as a general home TV, and the PDP has been enthusiastically working on high brightness, high definition, and cost reduction. There is. In addition, since the EL display has features such as self-luminous and capable of reproducing moving images, which are not present in the liquid crystal display, product development aiming at application to mobile terminals is being actively conducted.

In order to realize a high-performance and low-cost FPD, not only the panel technology but also the performance of the driver IC for driving the panel largely contributes. Therefore, the driver IC
However, there is a strong demand for cost reduction as well as high performance such as low power consumption and high noise immunity. The driver IC that drives the FPD has the following 2
There are two characteristics. (1) It is composed of a high breakdown voltage output section composed of a circuit including a high breakdown voltage device and a control circuit composed of a low breakdown voltage device. (2) A large number of high breakdown voltage output circuits are provided on one chip to provide multi-bit output.

In order to realize high performance and low cost of the FPD driving IC, how to realize these two features as an IC is an important item. Hereinafter, the features and problems of the FPD driving IC will be described in detail by taking a PDP driver IC as an example. FIG. 7 illustrates a high withstand voltage output circuit 911 including a MOS drive type high withstand voltage device and a control circuit 922 including a low withstand voltage device. The circuit example of the comprised PDP driver IC is shown. The high breakdown voltage output circuit 911 of this IC includes a push-pull circuit including a high breakdown voltage p-channel MOSFET 94a on the upper arm side and a high breakdown voltage n-channel MOSFET 95a on the lower arm side, and a high breakdown voltage p-channel MO.
The level shifter circuit 96a drives the SFET 94a. In addition, the control circuit 922 is usually a low breakdown voltage n-channel MOSFET and p-channel MOSFET.
It is composed of a CMOS circuit.

The output of the high breakdown voltage output circuit 911, that is, the output Do of the push-pull circuit is connected to the output pad 933 as the output of the IC, and this signal drives the PDP. The control of the output Do, that is, the operation of the push-pull circuit is controlled by the control circuit 922. In the PDP driver IC, the output Do has 64 to 128 outputs, and as many high breakdown voltage output circuits 911 as the number of outputs are mounted on the IC.

Various combinations can be considered for the structure of the high breakdown voltage output circuit depending on the required output characteristics. Here, the push-pull circuit of FIG. 7 will be described as a typical example. In the figure, VH is the output side power supply voltage / terminal, VL
Is an input side power supply voltage / terminal, Vss is a reference voltage (ground) / terminal, and Vin is an input signal voltage / terminal. Figure 8
FIG. 8 is a chip plan view showing an example of device arrangement of the PDP driver IC of FIG. 7, FIG. 7A is a schematic view, and FIG. 8B is a detailed view of a portion B in FIG.

The chip 90 is divided into two parts: a control circuit portion 92 and a high breakdown voltage portion 91 in which a high breakdown voltage output circuit is arranged. Also,
The IC requires as many output pads 933 as the number of outputs, and these are arranged as the output pad row 93. The control circuit unit 92 is equipped with the control circuit 922 shown in FIG. 7. In the control circuit unit 92, control circuits for all output circuits are formed in one area.

An output circuit is formed for each output in the high breakdown voltage portion 91. That is, a high breakdown voltage p-channel MOSFET
A push-pull circuit composed of a column 94 and a high breakdown voltage n-channel MOSFET column 95, and a high breakdown voltage p-channel MO
The high withstand voltage output circuits 911 including the level shifter circuit rows 96 for driving the SFET rows 94 are present in the high withstand voltage portion 91 by the number of outputs. Therefore, the high breakdown voltage portion 91
In order to eliminate mutual interference between adjacent circuits, element isolation is required. In addition, the high breakdown voltage portion 91 and the control circuit portion 9
For the same purpose, element isolation is also required between the two.

In the figure, 50a is a high breakdown voltage p-channel MO.
The p region forming the SFETR column 94 and 50b have a high breakdown voltage n
N region forming channel MOSFETR column 94, 52
a is a p source region, 52b is an n source region, and 53a is a p source region.
Drain region, 53b n drain region, 54a p contact region, 54b n contact region, 55a high breakdown voltage p-channel MOSFET gate electrode, 55b high breakdown voltage n channel MOSFET gate electrode, 56a p.
Drift region, 56b is an n drift region, 61a is an n isolation region formed in the p region 50a, and 61b is an n region 5.
0b, a p isolation region 62a, an n well region in which the p source region 53a is formed, 62b a p well region in which the n source region 53b is formed, 70 and 80 are high breakdown voltage p channel MOSFETs, 71, 81 is a high breakdown voltage n-channel MOSFET, 93 is an output terminal row, Do700, D
o800 is an output terminal.

Next, a method of realizing the PDP driver IC of FIG. 8 by the semiconductor element isolation technique will be described.
9 is a cross-sectional structure diagram when the pn junction isolation technique of the buried epitaxial substrate 124 is used for the cross-section taken along the line AA in FIG. 8, and the cross-sectional structure taken along the line BB is shown in FIG. FIG. 11 shows a sectional structure taken along line C-C. This separation technology has been applied to PDP driver ICs since the 1980s, and has many product achievements. Hereinafter, this separation technique will be briefly described with reference to FIG.

A p-type epitaxial layer 5 is formed on the surface of the support layer 1 which is a p-type semiconductor substrate. At the interface between the support layer 1 and the epitaxial layer 5, an n-type buried layer 4a is formed. The buried layer 4 a is formed at the same time as the growth of the epitaxial layer 5 by introducing an n-type impurity into a desired region of the support layer 1 before the growth of the epitaxial layer 5.

After the epitaxial layer 5 is formed, the epitaxial layer 5 and the n isolation region 61a are divided into regions in which an element is to be formed (where the diffusion region is not formed becomes the n drift region 56a). The n isolation region 61a is formed by ion implantation and thermal diffusion like other diffusion regions forming the element. Then, the n isolation region 61a reaches the buried layer 4a, and a high breakdown voltage p-channel MOSFET is formed in each element formation region surrounded by the n isolation region 61a and the n buried layer 4a.
(70, 80, ...) Is formed. Next, the operation will be described.

Output side power supply voltage VH is applied to n isolation region 61a.
Is applied, the potential of the n-buried layer 4a also becomes VH. As a result, the function of the pn junction isolation acts, the two high breakdown voltage p-channel MOSFETs (70, 80) are isolated between the elements, and each element can operate independently. That is, the high breakdown voltage p-channel MOSFET 70 is controlled by its gate signal VgH70, and the result is the terminal Do.
It is output to 700. Similarly, high breakdown voltage p-channel MO
The SFET 80 is controlled by its gate signal VgH80, and the result is output to the terminal Do800.

The n-buried layer 4a is formed in order to reduce a parasitic current described later. Since this parasitic current is generated in the high breakdown voltage p-channel MOSFET 94a arranged on the upper arm side in the output circuit of FIG. 7, it is necessary to form the n-buried layer 4a immediately below this element. Therefore, the high breakdown voltage p-channel MOSFET 9
In FIG. 9 showing a sectional view of 4a, an n-buried layer 4a is formed on the entire interface between the support layer 1 and the epitaxial layer 5.

FIG. 10 shows a high breakdown voltage n-channel MOSFET.
FIG. 10 is a cross-sectional view of an essential part of the row 95, which is the conductivity type of FIG. 9 inverted. Detailed description is omitted. Further, although the p-buried layer 4b is formed in the figure, it is not always necessary to provide it because no parasitic current is generated in the high breakdown voltage n-channel MOSFET 95a arranged on the lower arm side. Reference numeral 57a in FIGS. 9 and 10 denotes a PMOS source electrode, and 57a.
b is an NMOS source electrode, 58a is a PMOS drain electrode, 58b is an NMOS drain electrode, and 62a is n.
A well region, 62b is a p well region, 63a is a reference electrode formed on the n isolation region, and 63b is a reference electrode formed on the p isolation region.

FIG. 11 shows a high breakdown voltage p-channel MOSFET.
The vicinity of a separation point 50c that separates the column 94 and the high breakdown voltage n-channel MOSFET column 94 is shown. Since a high voltage is applied between the output side power supply voltage terminal VH and the reference voltage terminal Vss, it is necessary to secure a predetermined distance at this separation point. Further, as described above, it is not necessary to form the buried layer in the region where the parasitic current does not occur, and when viewed from the entire IC, the buried layer is partially present at the interface between the support layer 1 which is the semiconductor substrate and the epitaxial layer 5. It is formed.

FIG. 12 is a cross-sectional view of the control circuit section 92 when this separation technique is used. Since no parasitic current is generated in the control circuit portion 92, it is not necessary to form the buried layers 4a and 4b at the interface between the support layer 1 and the epitaxial layer 5. This control circuit section 92 is a p-channel MOSFET 92.
It is composed of CMOS of p and n channel MOSFET 92n.

Since the support layer 1 is partially connected to the epitaxial layer 5 as shown in FIG. 12, the voltage of the element formed in the epitaxial layer 5 is applied to the support layer 1. The voltage of the support layer 1 in FIG. 12 is the n-channel MOS that constitutes the CMOS circuit of the control circuit unit 92.
It is fixed by the voltage Vss applied to the FET 92n.

The pn junction isolation method using the epitaxial substrate 124 has a problem that a parasitic transistor exists. In the case of FIG. 9, a parasitic transistor is formed by the p-type epitaxial layer 5, the n-type buried layer 4 a, and the p-type support layer 1. Depending on the operation of the IC, a situation occurs in which this parasitic transistor is likely to operate. When this parasitic transistor operates, a large parasitic current flowing into the support layer 1 will be generated.
If the area of the high breakdown voltage p-channel MOSFET is large,
Even if the injection efficiency of the parasitic transistor is suppressed by forming the n-buried layer 4a, the parasitic current has a magnitude that cannot be ignored. Therefore, the generation of this parasitic current causes an increase in the power consumption of the IC, which is a major drawback of the pn junction separation method using the epitaxial substrate. In the case of FIG. 10 also, an npn parasitic transistor is formed,
The same inconvenience occurs.

To alleviate this drawback, a dielectric isolation scheme has been developed which combines an SOI substrate and trench isolation. FIG. 13 shows a sectional structure when this separation technique is applied to the sectional structure taken along the line AA in FIG. Here, the sectional structure taken along the line BB or CC of FIG. 8 is omitted. The SOI substrate 123 includes a support layer 1 which is a semiconductor layer, an SOI layer 3 which is a semiconductor layer forming an element, and an oxide film 2 which is an insulating film formed between the support layer 1 and the SOI layer 3. . The semiconductor element is formed on the SOI layer 3, and the supporting layer 1 on one side is the SOI substrate 12.
Play the role of supporting 3.

In FIG. 13, the SOI layer 3 is a p-type semiconductor layer. The SOI layer 3 is divided into element formation regions by a trench isolation region 60, and high breakdown voltage p-channel MOSFETs (70, 70) are formed in two element formation regions separated from each other.
80) has been formed. The trench isolation region 60 is formed by trench etching, and the inside thereof is filled with a dielectric layer such as an oxide film.

Two high breakdown voltage p-channel MOSFETs
The elements (70, 80) are isolated from each other by the trench isolation region 60, and each element can operate independently. That is, the high breakdown voltage p-channel MOSFET 70 is controlled by its gate signal VgH70, and the result is output to the terminal Do700. Similarly, the high breakdown voltage p-channel MOSFET 80 is controlled by its gate signal VgH80, and the result is output to the terminal Do800.

It is necessary to fix the support layer 1 of the SOI substrate 123 to an arbitrary voltage, which must be done by applying a voltage from an external power source. Figure 1
In No. 3, the voltage is applied via the electrode terminal 100, but the electrode terminal 100 is not intentionally formed. For example, I
IC in package or module that mounts C
It is also possible to fix the potential of the support layer 1 through a stage for fixing the chip.

In the method in which the SOI substrate and the trench isolation are combined, the element formation region is covered with the insulating film, so that the semiconductor elements can be completely electrically isolated. Therefore, in this method, there is no parasitic transistor as in the pn junction separation method using the epitaxial substrate, and it is possible to prevent an increase in the current consumption of the IC due to the generation of a parasitic current. As a result, an IC with low power consumption can be realized.

However, in this method, the trench isolation region 60 is formed.
To form the trench groove, a complicated process is required for forming a trench groove and filling the trench groove with an insulator, which increases the manufacturing lead time (manufacturing man-hour) of the semiconductor integrated circuit. As described above, the pn junction isolation using the buried epitaxial layer and the dielectric isolation method combining the SOI substrate and the trench isolation have advantages and disadvantages. Therefore, a pn junction separation method using an SOI substrate can be considered using the method disclosed in Japanese Patent Laid-Open No. 7-74242. An example thereof is shown in FIG.

This method is used for the epitaxial substrate 124 of FIG.
Is replaced with the SOI substrate 123 shown in FIG. Isolation between elements is performed by the oxide film 2 on the SOI substrate 123.
This is done by the separation area 61 reaching up to. Since the IC using this method does not require trench isolation and there is no parasitic element, the manufacturing process can be simplified and the power consumption can be reduced. However, the following problems remain in the IC using this method. In the following description, a high breakdown voltage p-channel MOSFET will be described as an example.

In the pn junction isolation, elements are isolated by the n isolation region 61a. The n isolation region 61a needs to reach the oxide film 2 of the SOI substrate 123, and the diffusion depth depends on the thickness of the SOI layer 3. FP such as PDP
Since the driver IC for driving D requires a withstand voltage of about 100 V, the SOI layer thickness is as thick as 5 μm or more. Therefore, the diffusion depth of the n isolation region 61a is 5 μm or more,
The lateral diffusion width is also 4 μm or more. Since the lateral diffusion width depends on the diffusion depth, as the SOI layer thickness increases, n
The lateral diffusion width of the isolation region 61a will increase.

An increase in the lateral diffusion width of the n isolation region 61a causes an increase in the isolation area occupied in the IC. In particular, in the FPD driving IC having a multi-bit output, this increase in the separation area remarkably appears in the increase in the IC chip area. Therefore, the separation method (SOI substrate (upper and lower separation) and pn shown in FIG.
In the case of using the junction isolation (side isolation), the occupied area of the n isolation region 61a increases as the withstand voltage becomes higher, and the increase of the IC chip area becomes a problem. Then, this causes an increase in the cost of the IC, which hinders the cost reduction required for the FPD driving IC.

On the other hand, Japanese Unexamined Patent Publication No. 10-189950 discloses a method of reducing the chip area of the IC by reducing the isolation area for the PDP driver IC in which the buried epitaxial substrate and the pn junction isolation are combined. However, in the method disclosed in FIG. 2 of Japanese Patent Application Laid-Open No. 10-189950, the area outside the n separation region is
An n well region is formed, and a p channel region is formed in the surface layer of the protruding n well region. That is, in the method disclosed in Japanese Unexamined Patent Publication No. 10-189950, the p source region forming the high breakdown voltage element is formed so as to protrude from the n isolation region.

Therefore, as described above, the higher the breakdown voltage element is, the larger the isolation area is, and the increase in the chip area of the IC becomes a problem. Then, this causes an increase in the cost of the IC, which hinders the cost reduction required for the FPD driving IC.

[0031]

As described above, by adopting the separation method in which the SOI substrate and the pn junction separation are combined in the formation of the FPD driving IC, the IC can be formed.
It is possible to simplify the manufacturing process and reduce power consumption. However, the isolation region (diffusion layer) for element isolation is S
It is necessary to reach the oxide film of the OI substrate, which is the IC
Cause an increase in separation area. Therefore, the chip area of the IC is increased, and as a result, the IC chip cost is increased.

An object of the present invention is to solve the above problems and to provide a semiconductor integrated circuit device which uses a pn junction separation method for side surface separation and can reduce the chip area and cost. is there.

[0033]

To achieve the above object, a first semiconductor layer and a second semiconductor layer, a first isolation region interposed between the two semiconductor layers, and the first semiconductor layer are provided. A second isolation region which is formed of a semiconductor region having a conductivity type opposite to that of the first semiconductor layer and which extends from the surface of the first isolation region to the first isolation region, and is surrounded by the first isolation region and the second isolation region. A divided region of the first semiconductor layer and a first region having a conductivity type opposite to that of the second separated region formed in the surface layer of the second separated region, the first region and the divided region. A gate electrode formed via a gate insulating film on the second isolation region sandwiched between regions, a first main electrode formed on the first region, and selectively formed on a surface layer of the divided region A second region having the same conductivity type as or a conductivity type opposite to that of the divided region, and on the second region A structure having a second main electrode formed.

Further, it is preferable that the first isolation region is formed of an insulating film. The first isolation region may be formed of a semiconductor region having a conductivity type opposite to that of the second semiconductor layer. In addition, an SOI substrate having two semiconductor layers above and below the insulating film via an insulating film is used as a semiconductor substrate, and an output circuit including a plurality of MOS drive type high withstand voltage devices and a low voltage device is formed on one of the semiconductor layers. In a semiconductor integrated circuit device having a control circuit composed of a withstand voltage device and having a large number of the output circuits mounted on a semiconductor substrate, an inversion channel (channel region) for injecting majority carriers of a MOS drive type high withstand voltage device that constitutes the output circuit. A diffusion layer (well region) having a conductivity type opposite to that of the semiconductor layer forming a surface layer reaches the insulating film of the SOI substrate, and the diffusion layer forms an output circuit to form a MOS drive type high breakdown voltage. The devices are separated from each other.

Further, two semiconductor layers are formed on one of the semiconductor layers by using a buried epitaxial substrate existing above and below the buried layer with a buried layer having a conductivity type opposite to that of the at least one semiconductor layer therebetween. In a semiconductor integrated circuit device having an output circuit including a plurality of MOS drive type high withstand voltage devices and a control circuit composed of low withstand voltage devices, and a plurality of the output circuits mounted on a semiconductor substrate, a MOS forming the output circuit An inversion channel (a channel region) for injecting majority carriers of a drive type high breakdown voltage device is formed in a surface layer, and a diffusion layer (a well region) having a conductivity type opposite to that of the one semiconductor layer is embedded in the buried epitaxial substrate. Reach the layer, and the MOS drive type high breakdown voltage device constituting the output circuit is separated by the diffusion layer. That.

As described above, the isolation region also serves as the well region, the source region is formed in this isolation region, and the channel region is formed in the surface layer of the isolation region sandwiched between the source region and one of the semiconductor layers. Therefore, the chip area can be reduced. As a result, cost reduction can be realized.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1, 2, 3 and 4 are
1A and 1B are schematic diagrams of a semiconductor integrated circuit device according to a first embodiment of the present invention, FIG. 1A being a schematic plan view, and FIG.
1A is an enlarged view of part A, FIG. 2 is a sectional view of an essential part taken along line AA of FIG. 1B, and FIG. 3 is a sectional view of an essential part taken along line BB of FIG. 1B. FIG. 4 is a cross-sectional view of the principal part taken along the line CC of FIG. 1 (b). 1 is an FP corresponding to FIG.
FIG. 2 is a plan view of a main part of the D driving IC. FIG.
ET, FIG. 3 is an n-channel MOSFET adjacently arranged in the lower arm, and FIG. 4 is a p-channel MOS of FIG.
FIG. 4 is a cross-sectional view of essential parts near a separation portion between the FET and the n-channel MOSFET of FIG. In the plan view of FIG. 1B, the source electrode and the drain electrode are omitted. Further, in the reference numerals in the drawing, the same portions as those in FIGS. 8 to 11 are denoted by the same reference numerals.

In FIGS. 1A, 1B, 2 and 3, the support layer 1 which is a p or n semiconductor substrate and 60Ω.
A surface concentration for forming a p-channel MOSFET is 10 using an SOI substrate 123 in which a p-type semiconductor substrate 3 having a high resistance of about cm is bonded via an oxide film 2 which is an insulating layer.
¹⁶ cm ^-3 of about p region 50a (p semiconductor layer) and the surface concentration to form an n-channel MOSFET is formed to 10 ¹⁶ cm ^-3 approximately n region 50b and (n semiconductor layer) reaches the oxide layer 2. The p region 50a is penetrated to reach the oxide film 2, the p region 50a is divided to form an n isolation region 51a, and the n region 50b is penetrated to reach the oxide film 2 to reach the oxide film 2. A p isolation region 51b to be divided is formed. The p source region 52a is formed in the surface layer of the n isolation region 51a (n base region), and the p isolation region 51b is formed.
An n source region 52b is formed in the surface layer of (p base region).

The p source region 52a and the p region 50a are also included.
On the n isolation region 51a sandwiched between (the non-diffusion region becomes the n drift layer 56a) and the p isolation region 51b sandwiched between the n source region 52b and the n region 50b (the non-diffusion region serves as the n drift layer 56b). Gate electrodes 55a and 55b are formed on a gate insulating film (not shown), respectively.
The isolation region 51a immediately below the gate electrodes 55a and 55b,
A channel (inversion channel for majority carrier injection of MOS drive type high breakdown voltage device) is formed on the surface of 51b.
Further, on the p source region 52a and the n contact region 54
Source electrodes are formed on a. A p drain region 53a is formed on the surface layer of the p region 50a, and an n region 50b is formed.
An n drain region 53b is formed on the surface layer of the above, and drain electrodes 58a and 58b are formed on the p drain region 53a and the n drain region 53b, respectively. p region 5
The areas where the diffusion region is not formed in the 0a and n regions 50b become drift regions 56a and 56b, respectively.

The above-mentioned n isolation region 51a and p isolation region 51
The surface concentration of b is adjusted by the ion implantation dose amount and diffusion conditions for forming the isolation regions 51a and 51b so that the threshold voltage of the MOSFET is optimized.
Usually, the surface concentration is about 10 ¹⁷ cm ⁻³ to 10 ¹⁸ cm ^−2, which is the same as the surface concentration of the conventional n base region (n well region) or p base region (p well region). Of course, the surface concentration of the n isolation region 51a and the p isolation region 51b where the source regions 52a and 52b are not formed may be higher than this.

As described above, the source regions 52a and 52b and the gate portions (55a and 55b) are formed in the isolation regions 51a and 51b.
Etc.), the length in the Y direction (direction parallel to the AA cutting line) can be reduced. The degree of reduction is about 16 μm per cell (one MOSFET). Since several tens to several hundreds of cells are formed in the FPD driving IC, the chip size can be reduced on the order of 0.1 mm to 1 mm.

Further, the isolation regions 51a and 51b are MOSFs.
ET base region (well region 58 in FIGS. 9-11)
a, 58b), there is no need to separately form a base region (well region) in the p region 50a and the n region 50b, and a step of forming a base region (well region) (1150 ° C., 200 minutes) Can be omitted. SOI
Since the substrate 123 is used, there is almost no leakage current flowing to the semiconductor substrate 1, and low power consumption can be achieved.

Further, the high breakdown voltage p-channel MOSFET 7
The p source regions 52a of 0 and 80 are connected to the output power supply voltage VH. Therefore, as shown in FIG. 2, the n isolation region 51a is formed by sharing the n base region (n
Since it can be used as a well region), the conventional n isolation region 57a can be omitted, so that the chip area can be reduced.

On the other hand, high breakdown voltage n-channel MOSFET 7
The n source region 52b of 1 is fixed to the reference voltage Vss (ground potential). Therefore, as shown in FIG. 3, since the p isolation region 51b can be used as a common p base region (p well region) between two adjacent elements, the conventional p isolation region 57b can be omitted and the chip can be omitted. The area can be reduced.

As a result, it becomes possible to reduce the cost by reducing the IC chip area and the number of manufacturing steps.
It is possible to reduce the cost of the FPD driving IC. The two high breakdown voltage p-channel MOSs shown in FIG.
As in the case shown in FIG. 14, the FETs (70, 80) are separated from each other and each element can operate independently. That is, the high breakdown voltage p-channel MOSFET 7
0 is controlled by the gate signal VgH70, and the result is output to the terminal Do700. Similarly, high breakdown voltage p
The channel type MOSFET 80 has its gate signal VgH8.
It is controlled by 0, and the result is output to the terminal Do800.

Two high breakdown voltage n-channel MOSFs are also provided.
The ETs (71, 81) are isolated from each other by the p-type isolation region 51a, and each element can operate independently. That is, the high breakdown voltage n-channel MOSFET 71 is controlled by its gate signal VgL71, and the result is output to the terminal Do700. Similarly, the high breakdown voltage n-channel MOSFET 81 is controlled by its gate signal VgL81, and the result is output to the terminal Do800.

Further, in FIG. 1, since the FPD driving IC chip is taken as an example, a high breakdown voltage n-channel MOSFET is used.
The high breakdown voltage p-channel MOSFET and the high breakdown voltage p-channel MOSFET are formed on the same chip. However, in the case of an IC chip for other applications, the high breakdown voltage n-channel MOSFET and the high breakdown voltage p-channel MOSFET may be formed on different chips. Absent. Figure 4
11 is a diagram corresponding to FIG. 11 and shows a high breakdown voltage p-channel MO.
The vicinity of a separation location 50c that separates the SFET 70 and the high breakdown voltage n-channel MOSFET row 71 is shown. Since VH has a high potential and Vss has a low potential, and a voltage between VH and Vss is applied to this separation point, it is necessary to secure a predetermined distance. Although the distance of the separation point 50c is the same as that in FIG. 11, in FIG. 4, the source region is formed in the separation region, so that the chip can be reduced by about twice the L shown in FIG.

5 and 6 show a semiconductor integrated circuit device according to a second embodiment of the present invention. FIG. 5 is a sectional view of an essential part corresponding to FIG. 2, and FIG. 6 is a sectional view of an essential part corresponding to FIG. It is a figure.
The plan view of this semiconductor integrated circuit device is the same as FIG.
The difference from the first embodiment is that a buried epitaxial substrate 124 is used instead of the SOI substrate 123. Also in this case, the same effect as that of the first embodiment can be expected.

By forming the source side region (source region 52a and gate portion) in the isolation region, the chip area can be reduced and the cost can be reduced as compared with the structure disclosed in the above-mentioned Japanese Patent Laid-Open No. 10-189950. Can be realized.

[0050]

According to the present invention, the chip area can be reduced by forming the source region and the gate portion in the isolation region (pn junction isolation region) for isolating the elements. Further, since the base region for forming the source region is the isolation region, the step for individually forming the base region can be omitted. Thus, the manufacturing cost can be reduced by reducing the chip area and the base forming process.

Further, since the pn junction isolation is used, a complicated process such as trench isolation is not required, and the manufacturing cost can be reduced as compared with the trench isolation method. Further, when the SOI substrate is used, the occurrence of the alignment error in the patterning process at the time of forming the isolation region, which occurs when the buried epitaxial substrate is used, is eliminated.
The separation region can be easily formed, and the manufacturing cost can be reduced.

Further, by using the SOI substrate, the leakage current can be reduced and the power consumption can be reduced as compared with the case of the buried epitaxial substrate.

[Brief description of drawings]

FIG. 1 is a schematic view of a main part of a semiconductor integrated circuit device according to a first embodiment of the present invention, FIG.
FIG. 1B is an enlarged view of part A of FIG.

FIG. 2 is a sectional view of an essential part taken along the line AA of FIG.

FIG. 3 is a sectional view of an essential part taken along line BB in FIG.

FIG. 4 is a sectional view of an essential part taken along the line C-C in FIG.

FIG. 5 is a cross-sectional view of a main portion of a semiconductor integrated circuit device according to a second embodiment of the present invention, which corresponds to FIG.

FIG. 6 is a cross-sectional view of a main portion of a semiconductor integrated circuit device according to a second embodiment of the present invention and corresponds to FIG.

FIG. 7 is a circuit diagram of a PDP driver IC

8A and 8B are chip plan views showing an example of device arrangement of the PDP driver IC of FIG. 7, where FIG. 8A is a schematic plan view and FIG. 8B is a detailed view of a portion B in FIG. 8A.

9 is a cross-sectional view of the main part taken along the line AA in FIG.

10 is a cross-sectional view of a main part taken along line BB in FIG.

11 is a cross-sectional view of the main part taken along the line CC of FIG.

FIG. 12 is a cross-sectional view of the main parts of the control circuit unit in FIG.

FIG. 13 is a sectional view of an essential part of a PDP driver IC chip using a conventional SOI substrate and a trench isolation region.

FIG. 14 is disclosed in Japanese Patent Laid-Open No. 7-74242;
Sectional view of a main part of a pn junction separation type PDP driver IC chip using an SOI substrate

[Explanation of symbols]

1 Support Layer 2 Oxide Film 3 SOI Layer 4a n Buried Layer 4b p Buried Layer 5 Epitaxial Layer 50a p Region 50b n Region 51a p Isolation Region 51b n Isolation Region 52a p Source Region 52b n Source Region 53a p Drain Region 53b n Drain Region 54a n contact region 54b p contact region 55a gate electrode (PMOS) 55b gate electrode (NMOS) 56a p drift region 56b n drift region 57a source electrode (PMOS) 57b source electrode (NMOS) 58a drain electrode (PMOS) 58b drain electrode ( NMOS) 70,94a high breakdown voltage p-channel MOSFET 71,95a high breakdown voltage n-channel MOSFET 80 high breakdown voltage p-channel MOSFET 81 high breakdown voltage n-channel MOSFET 90 chip 91 high breakdown voltage portion 92 control Road section 93 output terminal row 94 high-voltage p-channel MOSFET column 95 high-voltage n-channel MOSFET column 96 level shift circuit array 96a the level shift circuit 123 SOI substrate 124 epitaxial substrate 911 high-voltage output circuit 933 output terminal / pad (Do700, Do80
0) VH output side power supply voltage / terminal VL input side power supply voltage / terminal Vss reference voltage / terminal Vin input signal voltage / terminal VgH p-channel MOSFET gate signal / terminal VgL n-channel MOSFET gate signal / terminal

Front page continued (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/08 331 H01L 29/78 621 27/08 102A 27/088 29/786 F term (reference) 5F032 AA06 AB01 AB02 BB06 CA17 CA20 CA24 5F038 CA02 CA05 CA06 EZ06 EZ20 5F048 AA05 AB07 AC03 BA12 BA16 BH01 BH04 5F110 AA04 AA09 BB12 CC02 DD01 DD12 GG34 GG52 HM12 NN65 QQ17

Claims (5)

[Claims] 1. A first semiconductor layer, a second semiconductor layer, and the second semiconductor layer.
A first isolation region interposed between the two semiconductor layers;
A second isolation region, which is formed of a semiconductor region having a conductivity type opposite to that of the first semiconductor layer, reaching the first isolation region from the surface of the semiconductor layer, and surrounded by the first isolation region and the second isolation region, A divided region of the first semiconductor layer divided into a plurality of portions, a first region of a conductivity type opposite to that of the second isolation region formed in the surface layer of the second isolation region, and the first region. A gate electrode formed via a gate insulating film on the second isolation region sandwiched between the division regions, a first main electrode formed on the first region, and a surface layer of the division region selective. 2. A semiconductor integrated circuit device, comprising: a second region having the same conductivity type as or a conductivity type opposite to that of the divided region, and a second main electrode formed on the second region. 2. The semiconductor integrated circuit device according to claim 1, wherein the first isolation region is formed of an insulating film. 3. The semiconductor integrated circuit device according to claim 1, wherein the first isolation region is formed of a semiconductor region having a conductivity type opposite to that of the first semiconductor layer. 4. An output including a plurality of MOS drive type high breakdown voltage devices formed on one of the semiconductor layers using an SOI substrate having two semiconductor layers above and below the insulating film with an insulating film interposed therebetween as a semiconductor substrate. Inversion channel for majority carrier injection of a MOS drive type high breakdown voltage device, which constitutes an output circuit, in a semiconductor integrated circuit device including a plurality of output circuits mounted on a semiconductor substrate, the control circuit including a circuit and a low breakdown voltage device. A diffusion layer having a conductivity type opposite to that of the semiconductor layer forming a layer reaches the insulating film of the SOI substrate, and the diffusion layer separates elements of the MOS drive type high breakdown voltage device forming an output circuit. Integrated circuit device. 5. A buried epitaxial substrate in which two semiconductor layers are present above and below the buried layer with at least one buried semiconductor layer having a conductivity type opposite to that of the one semiconductor layer is used as a semiconductor substrate, and is formed on the one semiconductor layer. , Multiple MOs
In a semiconductor integrated circuit device including an output circuit including an S drive type high breakdown voltage device and a control circuit configured of a low breakdown voltage device, and a large number of the output circuits mounted on a semiconductor substrate, a MOS drive type high voltage device that constitutes the output circuit. A MOS drive type high breakdown voltage device that reaches the buried layer of the buried epitaxial substrate having a conductivity type opposite to that of the one semiconductor layer forming the inversion channel for majority carrier injection of the breakdown voltage device and forms an output circuit by the diffusion layer is an element. A semiconductor integrated circuit device characterized by being separated.