JP2003338411A - Laminated chip inductor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To inexpensively and efficiently form a coil having a conductor width of, for example, ≤0.05 mm with high winding efficiency in a laminated chip inductor in which the coil overlapped in the direction of layers is formed by successively connecting conductor patterns of different layers to each other while nonmagnetic electrically insulating layers and the conductor patterns are alternately laminated upon another by screen printing. <P>SOLUTION: Through windows 22, 23, 24, etc., are formed astride a plurality of adjacent chip sections in insulating layers 12, 13, 14, etc., interposed among conductor patterns 31, 32, 33, 34, etc., and the conductor patterns 31, 32, 33, 34, etc., are connected to each other in notched openings formed in a state where parts of the through windows 22, 23, 24, etc., enter into the chip sections. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated chip inductor in which a non-magnetic electric insulating layer and a conductor pattern are alternately laminated by screen printing and a method for manufacturing the laminated chip inductor, and more particularly, to a super chip used in portable equipment. It is effective when applied to a small surface mount type chip inductor.

[0002]

2. Description of the Related Art A multilayer chip inductor is used by being surface-mounted on an electronic circuit board of a portable device or the like, but a smaller one is required as the device becomes smaller and has higher functionality. In this laminated chip inductor, nonmagnetic electrical insulating layers and conductor patterns are alternately laminated, and the conductor patterns of each layer are sequentially connected to form a coil that is superposed in the lamination direction. In this case, it is advantageous in terms of cost to stack the insulating layer and the conductor pattern by screen printing.

FIG. 7 shows steps (a) to (h) of forming a conventional multilayer chip inductor. In the figure, when forming the multilayer chip inductor, first, a first conductor pattern 81 is printed and laminated on a first insulating layer (non-magnetic electrical insulating layer) 61 as a base (a, b). The first conductor pattern 81 does not have the first turn portion of the coil, and the lead conductor portion extends from one end thereof.

From the top of the first conductor pattern 81 to the second
The insulating layer 62 is printed and laminated (c). This insulating layer 62
Has a transparent window 72 through which the other end of the first conductor pattern 81 can be seen. The transparent window 72 is a so-called through hole, and the through hole wiring portion is formed by embedding the conductor portion 92 by printing (d).

After forming the through-hole wiring portion, the second conductor pattern 82 is printed and laminated (e). The conductor pattern 82 is formed so that one end thereof overlaps the conductor portion 92 of the transparent window 72. As a result, the first conductor pattern 81
One end of the second conductor pattern 82 is connected to the other end of the.

After that, the third insulating layer 63 is printed and laminated (f). The insulating layer 63 has a window 72 through which the other end of the second conductor pattern 82 can be seen. This transparent window 7
After embedding the conductor portion 93 in 2, the fourth conductor pattern 83 is printed and laminated (g, h). By repeating the above-described steps, it is possible to form a coil that is superposed in the stacking direction.

Each of the conductor patterns of the above-mentioned multilayer chip inductor has a square U-shape, and each layer has a 3/4 length.
A coil winding for the number of turns is formed. A coil having a predetermined inductance value can be formed by laminating a predetermined number of these 3/4 turn conductor patterns while sequentially connecting the conductor patterns at the through hole wiring portions. The formation of this coil is performed simultaneously on a plurality of processed substrates in which a large number of chip forming regions are defined. Each chip section is cut and divided after the substrate processing is completed, and finally a multilayer chip inductor with external terminals is finished.

[0008]

The multilayer chip inductor described above can be efficiently produced by screen printing at a low equipment cost. For that purpose, pattern formation by screen printing is highly accurate and reproducible. Needs to be done. On the other hand, there is a strong demand for downsizing of multilayer chip inductors due to downsizing and higher functionality of equipment, but in order to downsize, the conductor pattern of the coil must be miniaturized. The through-hole wiring part that sequentially connects the patterns must be miniaturized. For example, in the above-described conventional configuration, the diameter of the through-hole wiring portion must be at least 0.1 mm or less in order to reduce the conductor width of the coil to 0.05 mm or less. It is very difficult to form the structure by screen printing.

When forming a through hole in an insulating layer formed by screen printing, it is necessary to prevent the through hole from being crushed and blocked. For this purpose, it is necessary to sufficiently improve the shape retention of the insulating layer. In order to improve this shape retention property, a high-viscosity printing paste must be used. However, there is a trade-off that a high-viscosity printing paste is not suitable for forming an insulating layer having a flat surface by filling a step of a conductor pattern thereunder because of its lack of fluidity.

In order to connect the conductor patterns of each layer in sequence without using through-hole wiring, an insulating layer is laminated only on one half of the conductor pattern, and the insulating layer and the other half of the above conductor pattern are laid over and next to each other. It is sufficient to repeat stacking the conductor patterns of. In this case, the conductor pattern of each layer forms a coil winding pattern while being superposed and connected to the next conductor pattern half by half. However, with this configuration, the conductor pattern of each layer can only form a coil winding of ½ turn. That is, there is a problem that the winding efficiency of the coil for each layer is poor and a high inductance value cannot be obtained for the number of layers.

The present invention has been made in view of the above problems, and the non-magnetic electrical insulating layers and the conductor patterns are alternately laminated by screen printing, and the conductor patterns of each layer are sequentially connected and overlapped in the layer direction. It is an object of the present invention to provide a technique capable of efficiently forming a coil having a conductor width of 0.05 mm or less in a multilayer chip inductor in which a coil is formed with high winding efficiency and low cost.

[0012]

A first means according to the present invention is a coil in which a non-magnetic electrical insulating layer and a conductor pattern are alternately laminated by screen printing while the conductor patterns of the respective layers are sequentially connected and overlapped in the layer direction. The multilayer chip inductor in which is formed is characterized by having the following respective configurations. That is, the conductor patterns of the respective layers form coil turns of about 3/4 turn. In the insulating layer interposed between the layers of the conductor pattern, a pattern-shaped opening is formed by partially cutting out the end of the insulating layer pattern. The conductor patterns are interlayer-connected at the cutout-shaped openings. In the cutout-shaped opening, one end of the conductor pattern laminated on the upper side of the insulating layer is directly overlapped with and connected to the other end of the conductor pattern laminated on the lower side of the insulating layer.

The first means can have the following modes, for example. That is, each conductor pattern is laminated and formed in a substantially square U-shaped pattern shape, and the pattern shape of the interlayer connection portion is laminated and formed so as to be slightly extended in the direction in which the lower layer and / or upper layer conductor patterns are present. . Thereby, the stability of the interlayer connection can be further enhanced.

The notched opening has a pattern shape in which one corner of the insulating layer pattern is cut out in a square shape. As a result, the cutout-shaped opening can be formed by a window having a size that spans four adjacent chip formation regions on the processed substrate. The window can be sized so that it can be reliably and easily formed by screen printing. The notched opening can be planarized with an insulating paste.

The second means of the present invention is to form a coil in which the non-magnetic electric insulating layers and the conductor patterns are alternately laminated by screen printing while sequentially connecting the conductor patterns to form a coil which is superposed in the layer direction. In a method of manufacturing a multilayer chip inductor in which a plurality of chip forming regions are simultaneously formed on a processed substrate, a transparent window extending over a plurality of adjacent chip sections is formed in an insulating layer interposed between the conductor pattern layers. It is characterized in that the conductive pattern is connected at a notched opening formed by forming a part of the through window into each chip section.

The above-mentioned second means can have the following modes, for example. That is, the transparent window may be formed so as to straddle four adjacent chip sections. This makes it possible to form a notch-shaped opening having an area ¼ that of the through window in each of the four chip sections. Since the transparent window is four times as large as the cutout-shaped opening, it can be reliably and easily formed by screen printing. Further, by forming the transparent window in a rectangular pattern, it is possible to form a rectangular notch-shaped opening in each of a plurality of adjacent chip sections. This rectangular notch-shaped opening is suitable for sequentially connecting the rectangular U-shaped conductor patterns.

In this case, each conductor pattern is laminated in a substantially U-shaped pattern shape, and the pattern shape of the interlayer connection portion is slightly extended in the direction in which the lower layer and / or upper layer conductor patterns exist. By stacking the layers, the stability of interlayer connection can be improved.

By printing an insulating paste on the transparent window, the transparent window portion can be flattened. In this case, the insulating paste may be printed in an island shape at the center of the transparent window. Also, if the insulating paste is printed in a pattern shape along the area other than the conductor pattern in the transparent window,
The inside of the transparent window can be further surely flattened.
On the other hand, the insulating paste may be printed in a pattern shape that uniformly covers the entire portion including the conductor pattern portion of the window. The insulating paste is printed using a paste having a viscosity lower than that of the insulating layer in which the transparent window is formed. As a result, flattening due to the flow of the insulating paste can be reliably performed.

[0019]

1 to 3 show the essential parts of a multilayer chip inductor according to an embodiment of the present invention. In this case, FIGS. 1 and 2 show the forming steps (a) to (h) of the structure which is the main part of this embodiment. FIG. 3 shows a schematic configuration of the entire laminated chip inductor.

In FIGS. 1 and 2, the multilayer chip inductor comprises a non-magnetic electric insulating layer 11, 12, 13, 14 ,.
And the conductor patterns 31, 32, 33, 34, ... Are alternately laminated and the conductor patterns 31, 32, 3 of each layer are laminated.
The coils that are superposed in the stacking direction are formed by sequentially connecting 3, 34, .... Insulating layers 11, 12, 1
3, 14, ... and conductor patterns 31, 32, 33, 3
The lamination of 4, ... Is performed by screen printing, which is suitable for low cost and high efficiency production. Lamination processing by screen printing is performed for each substrate. A large number of chip formation regions are defined on one processed substrate, and one laminated chip inductor is formed for each chip division. After the substrate processing is completed, each chip section is cut and divided into individual multilayer chip inductors.

Conductor patterns 31, 32, 33, 3 of each layer
4, ... are each U-shaped, and each layer is 3 /
A coil winding for 4 turns is formed. A coil having a predetermined inductance value is formed by stacking a predetermined number of layers while sequentially connecting the conductor patterns of 3/4 turns.
This conductor pattern is connected to the insulating layers 12, 13, 14, ...
It is performed in the notched opening formed in.

The insulating layers 11, 12, 13, 14, ... Are formed in a rectangular (substantially square) pattern forming the cross-sectional shape of the chip. The conductor patterns 31, 32, 33 ,.
In the insulating layers 12, 13, 14, ... That are sandwiched in between, pattern-shaped openings are formed by partially cutting off the ends of the rectangular pattern. The notch-shaped opening is formed by the through windows 22, 23, 24, ... Formed over a plurality of adjacent chip sections on the same processed substrate. That is, the notch-shaped openings are joined together in a plurality of adjacent chip sections to form one large through window 22,2.
3, 24, ... are formed. The notch-shaped opening of each chip section forms a part (1/4 section) of the through windows 22, 23, 24 ,. The conductor patterns are interconnected through the notched openings having such a pattern shape.

Regarding the formation positions of the transparent windows 22, 23, 24, ..., It is desirable that they are located on the cross boundary that crosses one corner of four adjacent chip sections. In this case, in each chip section, a notch-shaped opening having a pattern shape obtained by cutting one corner of the insulating layers 12, 13, 14, ... It is formed with a size (area) of / 4. That is, the notch-shaped opening serving as the connection point of the conductor pattern can be formed by using the translucent window which is four times as large as that. As a result, the translucent windows 22 and 2 having a size capable of reliably and easily forming a pattern by screen printing.
Thus, the interlayer connection of the conductor patterns 31, 32, 33, 34, ... In each chip section can be reliably performed in a small area.

In order to sequentially connect the conductor patterns of the respective layers while ensuring the number of coil turns of 3/4 turns, it is necessary to prevent the connecting region from being too wide. It is possible to make it possible to secure the number of turns for 3/4 turns without any hindrance. Transparent window 2
For the shapes of 2, 23, 24, ..., The rectangular pattern as shown in the figure is the most suitable, but the circular shape or any other pattern shape is not hindered.

Further, each conductor pattern 31, 32, 33,
34 and the like are laminated in a substantially U-shaped pattern shape, and the pattern shape of the interlayer connecting portion is as shown in FIG. 1 and FIG.
Alternatively, the stability of the interlayer connection can be further enhanced by stacking the layers in a shape that is slightly extended in the direction in which the upper layer conductor pattern exists. In the example shown in FIGS. 1 and 2, one end or the other end of the conductor pattern having the extension is formed in a hook shape.

Hereinafter, the forming step (a) shown in FIGS. 1 and 2
(H) will be described. In the figure, first, a first conductor pattern 31 is printed and laminated on a first insulating layer (nonmagnetic electrically insulating layer) 11 as a base (a, b). The first conductor pattern 31 has no first turn portion of the coil, and the lead conductor portion extends from one end thereof.

A second insulating layer 12 is printed and laminated on the first conductor pattern 31 (c). The above-mentioned notched opening is formed in this insulating layer 12. This notch-shaped opening is formed by a transparent window 22 that straddles four adjacent chip sections. The transparent window 22 overlaps each other end of the first conductor pattern 31 formed in each chip section.

A second conductor pattern 32 is printed and laminated on the second insulating layer 12 (d). The second conductor pattern 32 is formed so that one end thereof overlaps with the other end of the first conductor pattern 31. As a result, one end of the second conductor pattern 32 is directly overlapped and connected to the other end of the first conductor pattern 31.

Further, the third insulating layer 13 is printed and laminated on the second conductor pattern 32 (e). The transparent window 23 is also formed in the third insulating layer 13. After this, the third
A third conductor pattern 33 is printed and laminated on the insulating layer 13 of (f). One end of the third conductor pattern 33 is connected to the other end of the second conductor pattern 32 at the window 23. Further, after the fourth insulating layer 14 is printed and laminated, the fourth conductor pattern 34 is formed by printing (g,
h). The one end of the fourth conductor pattern 34 also has the transparent window 24.
Is connected to the other end of the third conductor pattern 33.

By repeating the above steps,
It is possible to form a coil that is wound while being superposed in the stacking direction. The conductor pattern of each layer forming the coil has a square U shape, and a coil winding of 3/4 turn is formed for each layer. A coil having a predetermined inductance value can be formed by laminating a predetermined number of the 3/4 turn conductor patterns while sequentially connecting the through windows 22, 23, .... After the processing on the substrate is completed, each chip section is cut and divided into individual multilayer chip inductors.

FIG. 3 shows the overall structure of the laminated chip inductor 50 manufactured through the above-mentioned forming steps (a) to (h). The chip inductor 50 has external terminals 51 and 52 connected to the ends of the coil L. The coil L is formed of conductor patterns 3x that are sequentially connected while sandwiching the insulating layer 1x.

In the above-described multilayer chip inductor, one end of the conductor pattern laminated on the upper side of the insulating layer is directly overlapped with the other end of the conductor pattern laminated on the lower side of the insulating layer to be connected, Coils that overlap in the layer direction can be formed without using through-hole wiring, which is difficult to form by screen printing.

Both the upper and lower conductor patterns are partially overlapped and connected to each other at the cutout-shaped openings, and the cutout-shaped openings are formed in a plurality of chip sections adjacent to each other on the same processed substrate. It is formed by a large translucent window. This large transparent window can be reliably and easily formed by screen printing. For example, even if the cutout-shaped openings in each chip section have a small dimension of 0.1 mm square or less, a transparent window in which a plurality of cutout-shaped openings are associated can be formed reliably and easily by screen printing. It becomes the size.

The conductive patterns 31, 32, 33, 34, ... Of the respective layers, which are sequentially connected by the notched opening, are respectively
A 3/4 turn coil winding can be formed. As a result, in the multilayer chip inductor in which the non-magnetic electrical insulating layers and the conductor patterns are alternately laminated by screen printing, the conductor patterns of the respective layers are sequentially connected to form a coil overlapping in the layer direction, for example, the conductor width is 0. ．
An ultra-small coil of 05 mm or less can be efficiently formed with high winding efficiency and low cost.

FIG. 4 shows an essential part of another embodiment of the present invention by the forming steps (a) to (e). As shown in the figure, in this embodiment, the insulating paste portion 41 is printed in an island shape by screen printing in the transparent window 22 forming the cutout opening. The insulating paste portion 41 is fluidized and deformed in the subsequent printing and laminating process to flatten the portion of the transparent window 22. As a result, the subsequent printing and laminating process can be performed accurately. In this case, the insulating paste portion 41
In order to fill the step inside the transparent window 22 and flatten it, it is desirable to print by using a paste having a viscosity lower than that of the insulating layer 12 forming the transparent window 22.

FIG. 5 shows print pattern examples (a) to (c) of the insulating paste portion 41. The insulating paste portion 41
May be printed in an island shape only on the central portion of the transparent window 22 as shown in (a), but in order to surely flatten the inside of the transparent window 22, as shown in (b), Conductor pattern 3
It is better to print in a pattern shape along an area other than 1, 32. However, since the insulating paste portion 41 can be flattened by the subsequent printing lamination, if the viscosity is appropriately set, as shown in (c), the entire through window 22 is covered with the conductor patterns 31, 32. It may be a pattern shape that evenly covers the portion.

FIG. 6 shows another embodiment relating to the coil direction of the multilayer chip inductor formed according to the present invention. The multilayer chip inductor 50 shown in FIG. 3 is configured as a horizontally wound inductor in which the coil L is oriented in the horizontal direction with respect to the mounting surface, but in the one shown in FIG. 6, the coil L is with respect to the mounting surface. It is configured as a vertically wound type inductor that faces the vertical direction. That is, the present invention can be applied to either a horizontal winding or a vertical winding inductor structure.

Although the present invention has been described above based on its typical embodiment, the present invention can have various modes other than those described above. For example, the conductor patterns 31, 32, 33, 34, ... Which form the number of coil turns of 3/4 turns.
Can have a pattern shape other than the square U-shape, such as a modified C-shape.

[0039]

According to the present invention, a laminated chip in which a non-magnetic electrical insulating layer and a conductor pattern are alternately laminated by screen printing, and the conductor patterns of the respective layers are sequentially connected to form a coil overlapping in the layer direction. In the inductor,
For example, a coil having a conductor width of 0.05 mm or less can be efficiently formed with high winding efficiency and low cost.

[Brief description of drawings]

FIG. 1 is a plan view showing a configuration that is a main part of a multilayer chip inductor according to the present invention at each formation step.

FIG. 2 is a plan view showing a configuration of a main part at each stage of formation, following FIG. 1;

FIG. 3 is a perspective view showing the overall structure of the multilayer chip inductor according to the present invention.

FIG. 4 is a plan view showing a main part of another embodiment of the present invention in each forming step.

FIG. 5 is a plan view showing an example of a printing pattern of an insulating paste portion formed on a window.

FIG. 6 is a perspective view showing another embodiment of the coil direction of the multilayer chip inductor according to the present invention.

FIG. 7 is a plan view showing a main part of a conventional multilayer chip inductor at each formation step.

[Explanation of symbols]

11-14 Nonmagnetic Electrical Insulation Layer 22-24 Through Window 31-34 Formed Across Multiple Chip Sections Conductor Pattern 41 Insulation Paste 61-63 Nonmagnetic Electrical Insulation Layer 72, 73 Through Window (Through Hole) 81 To 83 conductor patterns 92, 93 embedded conductor portion (through hole wiring) L coil 51, 52 external terminal 1x insulating layer (11, 12, 13, 14, ...
…) 3x conductor pattern (31, 32, 33, 3
4, ……)

Claims (12)

[Claims] 1. A multilayer chip inductor in which a non-magnetic electrical insulating layer and a conductor pattern are alternately laminated by screen printing while the conductor patterns of the respective layers are sequentially connected to form a coil overlapping in the layer direction. 1) ~
A multilayer chip inductor having the configuration (4). (1) The conductor pattern of each layer forms a coil turn number of approximately 3/4 turns. (2) The insulating layer interposed between the conductor pattern layers includes:
A pattern-shaped opening is formed by partially cutting the end of the insulating layer pattern. (3) The conductor patterns are interlayer-connected at the cutout-shaped openings. (4) In the notched opening, one end of the conductor pattern laminated on the upper side of the insulating layer is directly overlapped and connected to the other end of the conductor pattern laminated on the lower side of the insulating layer. 2. The conductor pattern according to claim 1, wherein each conductor pattern is laminated in a substantially U-shaped pattern shape, and the pattern shape of the interlayer connection portion is in the direction in which the lower layer and / or upper layer conductor patterns exist. A laminated chip inductor, wherein the laminated chip inductor is formed so as to have a shape that is slightly extended. 3. The multilayer chip inductor according to claim 1, wherein the notch-shaped opening has a pattern shape in which one corner of the insulating layer pattern is cut in a square shape. 4. The multilayer chip inductor according to claim 1, wherein the notched opening is flattened with an insulating paste. 5. A non-magnetic electrical insulating layer and a conductor pattern are alternately laminated by screen printing while sequentially connecting the conductor patterns to form a coil that is superposed in the layer direction.
In a method of manufacturing a multilayer chip inductor in which a large number of coil formations are simultaneously performed on a processed substrate in which a large number of chip formation regions are divided, an insulating layer interposed between the conductor pattern layers is provided with a transparent layer extending over a plurality of adjacent chip divisions. A method for manufacturing a multilayer chip inductor, comprising forming a window, and connecting the conductor pattern at a notched opening formed by a part of the transparent window entering each chip section. 6. The method of manufacturing a multilayer chip inductor according to claim 5, wherein the transparent window is formed so as to straddle four adjacent chip sections. 7. The laminated chip inductor according to claim 5, wherein the through window is formed in a rectangular pattern to form rectangular notch-shaped openings in a plurality of adjacent chip sections. Production method. 8. The method for manufacturing a multilayer chip inductor according to claim 5, wherein the transparent window is flattened by printing an insulating paste on the transparent window. 9. The method of manufacturing a multilayer chip inductor according to claim 8, wherein the insulating paste is printed in an island shape in the center of the through window. 10. The method for manufacturing a multilayer chip inductor according to claim 8, wherein the insulating paste is printed in a pattern shape along a region other than the conductor pattern in the transparent window. 11. The method of manufacturing a multilayer chip inductor according to claim 8, wherein the insulating paste is printed in a pattern shape that uniformly covers the entire conductive pattern of the through window. 12. The method according to any one of claims 8 to 11,
The method of manufacturing a multilayer chip inductor, wherein the insulating paste is printed using a paste having a viscosity lower than that of an insulating layer in which the transparent window is formed.