JP2003337750A - Semiconductor device with internal analysis prevention function - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device hardly allowing estimation based on electric power analysis or timing analysis carried out for estimating secret information inside the device. <P>SOLUTION: A clock conversion mechanism 1 (101) converts a clock signal 110 of the device 100 to input it into a submodule 11 (102) and a submodule 12 (103). A clock conversion mechanism 2 (121) converts the clock signal 110 of the device 100 to input it to the submodule 21 (104) and a submodule 22 (105). The clock conversion mechanism outputs a pseudo random number sequence on the basis of the clock signal 110. Since the pseudo random number sequence is formed inside the device 100, its change can be hardly observed from the outside. The respective submodules use the pseudo random number sequence as a clock signal. In this way, a processing time and a power consumption of the submodule are varied every time on the same processing, so that the timing analysis and the power consumption analysis become difficult. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device or information equipment whose internal operation is difficult to analyze.

[0002]

2. Description of the Related Art With the development of information equipment, various kinds of information have been digitized. Some of this information is
It contains important information such as personal medical history related to privacy and electronic money used for payment. Such important information is protected by using a cryptographic technique to prevent it from being illegally viewed or tampered with by a third party.

Such peeping and tampering actions are called tampering, and the property of preventing them is called tamper resistance.

Cryptographic processing is realized by both software and hardware. When the cryptographic processing is implemented as software that runs on a PC that consists of a CPU, memory, HDD, etc., secret information such as cryptographic keys is stored in memory.
The information stored in the memory is read out by the CPU and processed. At this time, since the confidential information is transferred via the bus connecting the CPU and the memory, there is a risk that the confidential information may leak from the bus. That is, the tamper resistance in this case is low.
On the other hand, when the cryptographic process is realized by a one-chip semiconductor device such as an LSI, the secret information used in the cryptographic process is held inside the device and is not output to the outside. Further, since it is not easy to analyze the inside of the semiconductor device, the tamper resistance is higher than that achieved by software.

[0005]

However, even for semiconductor devices, there is an attack method for estimating secret information such as keys and processing contents by measuring changes in processing time and power consumption and statistically analyzing them. To do. Analysis based on changes in processing time is called timing analysis, and analysis based on changes in power consumption is called power analysis. Since these attack methods can be performed on the device in a non-destructive manner, the problem is that they pose a threat to information security.

[0006]

The present invention provides a semiconductor device in which it is difficult to estimate secret information inside the device by power analysis or timing analysis.

In order to solve the above problems, a semiconductor device with an internal analysis prevention function of the present invention provides an input clock signal, a clock conversion mechanism for converting and outputting the input clock signal, and an output of the clock conversion mechanism. And a module that operates as an operating clock.

The clock conversion mechanism of the present invention further comprises a PLL for generating a signal obtained by multiplying the input clock signal based on a multiplication factor, and a random number generation mechanism for generating a random number sequence obtained by converting the signal sequence generated by the PLL. And a normalization mechanism for generating a signal obtained by converting the random number sequence generated by the random number generation mechanism based on a condition.

Further, the clock conversion mechanism of the present invention comprises an encryption key, and the random number generation mechanism generates a different random number sequence depending on the encryption key.

Further, the clock conversion mechanism of the present invention is characterized by comprising means for externally changing the setting of the condition, the encryption key and the magnification.

Further, the random number generating mechanism and the normalizing mechanism of the present invention are characterized in that the signal generated by the PLL operates as an operation clock.

Further, the random number generation mechanism of the present invention outputs a register for storing and outputting the output of the cryptographic processing section, a ciphertext obtained by encrypting the output of the register with an encryption key, and a cipher code for the cipher. It is characterized by comprising a processing unit and a buffer for storing the ciphertext output from the encryption processing unit and outputting it as a bit string.

Further, the random number generating mechanism of the present invention has an initial value, the register stores the initial value before starting the cryptographic processing, and outputs the initial value to the cryptographic processing unit at the start of the cryptographic processing. And

Further, the normalizing mechanism of the present invention comprises a comparing mechanism for comparing the output of the counter with the above condition and outputting the result, a counter for changing the value according to the output of the result of the comparing mechanism, an output of the buffer and an output of the buffer. It is characterized by comprising a selector that outputs one of the inversions of the output according to the result of the comparison mechanism, and a buffer that stores and outputs the output of the selector.

The storage medium with encryption function of the present invention is
A storage medium with an encryption function that encrypts and stores information.It connects to an external device, inputs information from the external device, outputs information to the cryptographic processing mechanism and memory, and inputs information from the cryptographic processing mechanism and memory. Information output by the interface that outputs to the external device, the internal bus that connects the interface, the cryptographic processing mechanism, and the memory, and that supplies the bus clock to the interface, the cryptographic processing mechanism, and the memory, and the bus clock that is input from the internal bus Encryption processing, which outputs to the memory, outputs the information output from the memory to the interface, and inputs the bus clock from the internal bus, accumulates the information output from the interface, and outputs the accumulated information to the interface. Accumulates and outputs the information that is encrypted and output by the cryptographic processing mechanism The information characterized by comprising a memory to be output to the cryptographic processing mechanism.

Further, the cryptographic processing mechanism of the present invention is provided with a clock conversion mechanism for outputting a signal converted from the internal bus clock, and has a part which operates with the signal converted by the clock conversion mechanism as an operation clock. .

Further, the cryptographic processing mechanism of the present invention is characterized by comprising means for processing a cryptographic algorithm used for authentication and authenticating an external device.

The clock conversion mechanism of the present invention is characterized in that it is connected to an internal bus and supplies a bus clock obtained by converting an input clock.

Further, the information equipment of the present invention is provided with a clock conversion mechanism, and comprises a part which operates with an input clock as an operation clock and a part which operates with an output obtained by converting the input clock by the clock conversion mechanism as an operation clock. A protected module that connects to the internal bus and exchanges information with the non-protected module and interface via the internal bus, and a non-protected module that connects to the internal bus and exchanges information with the protected module and interface via the internal bus And an interface for connecting to an external device for exchanging information from the external device, for connecting to an internal bus, and for exchanging information between the protected module and the non-protected module via the internal bus.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. First, the first embodiment will be described.

FIG. 1 is a diagram showing a configuration example of the device of the present invention. FIG. 2 is a diagram showing a configuration example of the clock conversion mechanism of FIG. FIG. 3 is a diagram showing a configuration example of the random number generation mechanism of FIG. FIG. 4 is a diagram showing a configuration example of the normalization mechanism of FIG. FIG. 5 is a flowchart for explaining the operation for explaining the operation of the normalization mechanism of FIG. The device 100 shown in FIG. 1 is a module 1 (108).
The module 2 (109), the internal bus 107, and the bus bridge 130. The module 1 (108) and the module 2 (109) are connected to the internal bus 107 via the bus bridge 130. The bus bridge 130 can connect buses having different bus clocks. The bus bridge 130 synchronizes the internal bus 106 and the internal bus 107, and module 1 (108) and module 2 (109)
Enables data transfer via the internal bus 107.
The module 1 (108) and the module 2 (109) receive the clock signal 110. Module 1 (108)
Is submodule 11 (102) and submodule 1
2 (103), internal bus 106, and clock conversion mechanism 1
Sub-module 11 (102)
The sub module 12 (103) is connected to the internal bus 106. The submodule 11 (102) and the submodule 12 (103) receive the output 111 of the clock conversion mechanism 1 (101).

The module 2 (109) comprises a sub-module 21 (104), a sub-module 22 (105), an internal bus 126 and a clock conversion mechanism 2 (121), and the sub-module 21 (104) and the sub-module 2
The two (105) are connected by the internal bus 126. The submodule 21 (104) and the submodule 22 (105) receive the output 122 of the clock conversion mechanism 2 (121).

Hereinafter, the module 1 (108) and the module 2 (109) will be simply referred to as modules unless otherwise distinguished. In addition, a module inside the module is called a sub-module. Sub-module 11 (102), sub-module 12 (103), sub-module 21 (1
04) and the sub-module 22 (105) are modules, respectively, but if it should be noted that they are inside another module, they are called sub-modules. The clock conversion mechanism 1 (101) and the clock conversion mechanism 2 (121) are simply referred to as a clock conversion mechanism unless otherwise specified.

Although the number of modules is two, that is, the module 1 (108) and the module 2 (109), as the configuration example of the device 100, the number of modules is not limited to two, and one module is provided. Or three or more. Similarly, the number of submodules in each module is not limited to two. Further, each sub-module can include one or more sub-modules such as module 1 (108). That is, the modules can have a nested structure. Furthermore, although the module 1 (108) and the module 2 (109) each have a clock conversion mechanism, one clock conversion mechanism may be shared by a plurality of modules. The internal bus 106 and the internal bus 107 can be directly connected if the same bus protocol is used. The internal bus 106 and the internal bus 107 can be connected by performing protocol conversion if different bus protocols are used.

The clock conversion mechanism 1 (101) converts the clock signal 110 of the device 100 and inputs it to the submodule 11 (102) and the submodule 12 (103).

The clock conversion mechanism 2 (121) converts the clock signal 110 of the device 100 to convert it to the sub-module 2.
1 (104) and the sub module 22 (105). The clock conversion mechanism outputs a pseudo random number sequence based on the clock signal 110. Since the pseudo random number sequence is generated inside the device 100, it is difficult to observe the change from the outside. Each sub-module uses a pseudo-random number sequence as a clock signal. As a result, the processing time and power consumption of the submodules change for the same processing every time, which makes timing analysis and power consumption analysis difficult.

The sub-module 11 (102) and the sub-module 12 (103) consist of the clock conversion mechanism 1 (10
1) outputs the same pseudo-random number sequence as a clock signal, the internal bus 1 (1) of the module 1 (108)
In 06), synchronous transfer can be performed. Similarly, the sub-module 21 (104) and the sub-module 22 (10
Since 5) inputs the same pseudo-random number sequence output by the clock conversion mechanism 2 (121) as a clock signal, synchronous transfer can be performed by the internal bus 2 (106) of the module 2 (109). Further, the clock conversion mechanism 1 (10
1) and the clock conversion mechanism 2 (121) are clock signals 1
If the same pseudo random number sequence is output in synchronization with 10, the sub module 11 (102) and the sub module 12 (10
3), the sub-module 21 (104) and the sub-module 22 (105) can perform synchronous transfer via the internal bus 107 of the device 100. The clock conversion mechanism 1 (101) and the clock conversion mechanism 2 (121) have a reset signal input for synchronizing the pseudo random number sequence. Clock conversion mechanism 1 (101) and clock conversion mechanism 2 (12
1) outputs different pseudo-random number sequences, the sub-module 11 (102), the sub-module 12 (103), the sub-module 21 (104), the sub-module 22 (10).
5) outputs through the bus bridge 130 to the internal bus 10
Data can be transferred in synchronism with No. 7.

Next, a configuration example of the clock conversion mechanism 1 (101) shown in FIG. 1 will be described with reference to FIG. Clock conversion mechanism 2
(121) can have the same configuration as the clock conversion mechanism 1 (101). The clock conversion mechanism 1 (101) includes a PLL 201, a random number generation mechanism 203, and a normalization mechanism 205.
Composed of. The PLL 201 inputs the clock signal 110 and outputs a signal obtained by multiplying the clock signal based on the setting of the magnification 202. The magnification 202 is composed of a rewritable memory, and its setting may be changed externally.
The random number generation mechanism 203 operates by using the output 211 of the PLL 201 as an operation clock and generates a 1-bit random number sequence using the encryption key 204 as a seed. The encryption key 204 is composed of a rewritable memory, and its setting may be changeable from the outside. The normalization mechanism 205 operates by using the output 211 of the PLL 201 as an operation clock, and based on the setting of the condition 206, converts the 1-bit random number sequence output from the random number generation mechanism 203 and outputs it. The condition 206 is composed of a rewritable memory, and its setting may be changed externally.

The frequency of the clock signal 110 is f, PLL
If the magnification 202 of 201 is set to n times, the PLL 20
The frequency of the output 211 of 1 is nf. Random number generator 2
When 03 generates a 1-bit random number at the rising edge of the output 211, the output 213 of the random number generation mechanism 203 becomes a signal that changes in a time of 2 / nf at the shortest. That is, the output 213 of the random number generator 203 is the clock converter 10
As compared with the clock signal 110 input to 1, the shortest time from the change to the next change is short and the longest time is long.

The normalization mechanism 205 converts the 1-bit random number sequence output from the random number generation mechanism 203 based on the setting of the condition 206 and outputs it. Specifically, the random number generation mechanism 203
If the time from the change to the next change of the 1-bit random number sequence output by is too short, the change is suppressed, and if it is too long, the signal is forcibly changed and the signal is output. The output 111 of the normalization mechanism becomes the output of the clock conversion mechanism.

The PLL 201 is used to generate a signal whose phase is shifted from that of the clock signal 110. By setting the condition 206, the normalization mechanism 205 can control the timing of change of the output 111. The normalization mechanism 205 and the random number generation mechanism 203 may operate on both the rising and falling edges of the output 211 of the PLL. Clock signal 1
If you want to create a signal with a time interval that changes more than 10,
The PLL 201 is not necessary, and the clock signal 110 is P
It may be directly connected to the output 211 of the LL.

The random numbers generated by the random number generation mechanism 203 may have a uniform distribution or a biased distribution. If the distribution is biased, it is possible to set the biasing method from the outside.

Next, the random number generator 20 of FIG. 2 will be described with reference to FIG.
3 shows a configuration example. The random number generator 203 uses the register 30
3, a cryptographic processing unit 305, and a buffer 307.
The register 303 has an initial value 306 or a cryptographic processing unit 305.
The output 315 of the above is stored and output. The initial value 306 is composed of a rewritable memory, and its setting may be changeable from the outside. The cryptographic processing unit 305 receives the notification of the update request 311 from the buffer 307, and encrypts the output 313 of the register 303 using the cryptographic key 214 as a key. The cipher processing unit 305 performs block cipher processing. The block cipher is an encryption algorithm in which data having a fixed bit length is regarded as one block and encryption / decryption for one block is performed in one process. Here, the cipher processing unit 305 and the register 303 form a pseudo random number generator using the OFB mode of block cipher. The buffer 307 stores the output 315 of the cryptographic processing unit 305 and outputs it bit by bit to the outside. When all the stored bits are output, the update request 311 is output to the cryptographic processing unit 305. Buffer 30
The output of 7 becomes the output 213 of the random number generation mechanism 203. The buffer 307 has a role of converting the bit length of the output 315 of the encryption processing unit 305 into 1 bit.

In this configuration example, a random number sequence is generated by forming a pseudo random number generator with the cryptographic processing unit 305 and the register 303. The encryption processing unit 305 has a DES (Data
Encryption Standard) and AES
(Advanced Encryption Stan
common key cryptographic algorithms such as
re Hash Algorithm (SHA-1),
MD5 MessageDigest Algorit
A hash function such as hm can be used. Alternatively, the register 303, the encryption processing unit 305, and the buffer 3
Instead of using 07, LFSR (Linear F
It is also possible to use 1 bit in the LFSR as the output 213 by using the eedback Shift Register). In this case, the LFS using the encryption key 214
The characteristic polynomial of R may be determined. The implementation is not limited to the encryption algorithm described above, and other algorithms may be used in consideration of the characteristics of the generated random number sequence.

Further, the buffer 307 is the encryption processing unit 30.
Instead of storing the output 315 of No. 5 and outputting it one bit at a time, a plurality of bits of the output 315 may be logically operated to output one bit.

Next, referring to FIG. 4, the normalization mechanism 205 shown in FIG.
A configuration example of is shown. The normalization mechanism 205 includes a comparison mechanism 403, a counter 407, a buffer 404, a selector 405, and a logic inversion 406. The comparison mechanism 403, the counter 407, and the buffer 404 have internal states and operate in synchronization with the clock input to the normalization mechanism 205. The selector 405 and the logic inversion 406 are realized by combinational logic. The longest 401 and the shortest 402 are composed of rewritable memories, and their settings may be changed from the outside.
The comparison mechanism 403 outputs the output 417 of the counter 407 and the shortest 4
The output 412 of 02 and the output 411 of longest 401 are compared and the result is output. The counter 407 holds the value and adds 1 to the value or sets the value to 0 according to the output 413 of the comparison mechanism 403. The initial value of the value held by the counter 407 is 0. The logic inversion 406 inverts the output of the buffer and outputs it. The selector 405 uses the output 413 of the comparison mechanism to output either the buffer output or the buffer output inversion 41.
6 is output to the buffer 404. The buffer 404 stores and outputs the output 415 of the selector 405. Buffer 4
The output of 04 becomes the output of the normalization mechanism 205.

Next, the normalization mechanism 205 shown in FIG. 4 will be described with reference to FIG.
The operation of will be described. The process of one cycle of the process of the normalization mechanism 205 is as follows. (S501) Normalization mechanism 2
05 starts one cycle of processing, and proceeds to S502. (S502) The normalization mechanism 205 uses the comparison mechanism 403 to compare the value of the shortest 402 with the value of the counter 407, and calculate the shortest 402.
Is larger, go to S507, and if not, go to S503
Move to. (S503) The normalization mechanism 205 causes the comparison mechanism 403 to compare the maximum length 401 with the value of the counter 407. If the maximum length 401 is smaller, the process proceeds to S505, and if not, the process proceeds to S504. (S504) The normalization mechanism 205 treats the input 213 as a binary signal of 0 and 1. If the input 213 is 0, the process proceeds to S505, and if not, the process proceeds to S507. (S505) The normalization mechanism 205 inverts the output value of the buffer 404, that is, the buffer 404.
If the output value of is 0, it is 1, and if it is 1, it is 0, and S
Move to 506. (S506) The normalization mechanism 205 sets the value of the counter 407 to 0, and proceeds to S508. (S
507) The normalization mechanism 205 increments the value of the counter 407 by 1, and proceeds to S508. (S508) Normalization mechanism 2
05 completes the processing of one cycle.

At each cycle of the normalization mechanism 205, S501
Repeat the following steps. From the above, the normalization mechanism 205
Is the longest 401 and the shortest 4 that the same value continues.
Generate a signal limited by the value set to 02.

Next, a second embodiment will be described. FIG. 6 is a diagram showing a configuration example of a storage medium with an encryption function of the present invention. Storage medium with encryption function 60 shown in FIG.
0 is composed of a cryptographic processing mechanism 601, an interface 602, a memory 603 and an internal bus 610, and the cryptographic processing mechanism 601, the interface 602 and the memory 603 are connected to the internal bus 610. The interface 602 provides a function of connecting to an external device and exchanging information by one or both of wired and wireless. Interface 602
The cryptographic processing mechanism 601 can access part or all of the storage area of the memory 603. Access refers to one or both of read processing and write processing. The interface 602 and the cryptographic processing mechanism 601 have an accessible storage area of the memory 603. The interface 602 and the cryptographic processing mechanism 601 may partially or completely overlap the storage area of the accessible memory 603, or may be independent.

Furthermore, the storage medium with encryption function 600 can prohibit the interface 602 from directly accessing a part or all of the storage area of the memory 603 in order to restrict access to the memory 603 from an external device.

When accessing the storage area of the memory 603 which is prohibited from being directly accessed by the interface 602, the interface 602 uses the cryptographic processing mechanism 6.
01 to request access to the memory 603, the cryptographic processing mechanism 601 accesses the memory 603, and the cryptographic processing mechanism 601 returns the result of accessing the interface 602.
It can be accessed via 1. The cryptographic processing mechanism 601 can perform cryptographic processing when accessing the memory 603. The cryptographic processing mechanism 601 stores key information 620 used in cryptographic processing. The interface 602 can set the key information 620 in the cryptographic processing mechanism 601.

Further, the interface 602 can erase the key information 620 of the cryptographic processing mechanism 601. The data written in the memory 603 by the interface 602 using the key information A via the cryptographic processing mechanism 601 cannot be correctly read unless the same key information A is read via the cryptographic processing mechanism 601. That is, access to the memory 603 is restricted by the key.

The interface 602 accessing one or both of the cryptographic processing mechanism 601 and the memory 603 is synonymous with the external device connected to the interface 602 accessing one or both of the cryptographic processing mechanism 601 and the memory 603. Is.

The cryptographic processing mechanism 601 has a clock conversion mechanism 101, an example of which is shown in FIG. Cryptographic processing mechanism 6
A part of 01 operates using the output of the clock conversion mechanism 101 as an operating clock, and the remaining part operates using the bus clock of the internal bus 610 as an operating clock. The cryptographic processing mechanism 601 has a mechanism for synchronizing a portion operating with the output of the clock conversion mechanism 101 as an operation clock and a portion operating with the bus clock of the internal bus 610 as an operation clock.
The encryption key 204 of the clock conversion mechanism 101 can be set via the interface 602. Since the processing time and power consumption of the portion of the cryptographic processing mechanism 601 which operates using the output of the clock conversion mechanism 101 as an operation clock are different depending on the set encryption key 204, timing analysis and power consumption analysis are made difficult. By using the operation clock of the portion for encryption processing as the output of the clock conversion mechanism 101, the memory 60 by timing analysis and power consumption analysis
This makes it difficult to analyze the key that restricts access to 3.

Further, the storage medium with encryption function 600 can authenticate the external device by inputting the electronic certificate from the external device and verifying the electronic certificate by the encryption processing mechanism 601. The cryptographic processing mechanism 601 processes a cryptographic algorithm used for authentication. The storage medium 600 with the encryption function is the storage medium 600 with the encryption function for external devices that have been successfully authenticated.
Access is permitted, but access to the inside of the storage medium 600 with the encryption function is not permitted to an external device that has failed authentication. The electronic certificate is signed by the certificate authority in a format based on X509.

However, the format of the certificate that can be used by the storage medium with encryption function 600 is not limited to X509. It is signed by a digital signature algorithm md5RSA or the like. md5RSA is a signature algorithm that obtains a hash value of a public key or the like to be included in a certificate with a hash function MD5 and encrypts the hash value with a public key encryption RSA using a private key of a certificate authority. The public key of the certificate authority is required to verify the signature of the certificate authority. The public key of the certificate authority is included in the certificate of the certificate authority. The storage medium 600 with an encryption function can store the certificate of the certificate authority.
The storage medium 600 with the encryption function extracts the public key of the certificate authority from the certificate of the certificate authority and verifies the signature by the certificate authority.

The second embodiment is not limited to the above storage medium, but is applicable to IC cards, memory cards, hard disks, PCs, PDAs, displays, speakers and other information processing devices.

Next, a third embodiment will be described. FIG. 7 is a diagram showing a configuration example of a storage medium with an encryption function of the present invention. Storage medium with encryption function 60 shown in FIG.
Reference numeral 0 denotes a cryptographic processing mechanism 601, an interface 602, a memory 603, a clock conversion mechanism 101, and an internal bus 61.
The encryption processing mechanism 601, the interface 602, the memory 603, and the clock conversion mechanism 101 are connected to the internal bus 610.

The storage medium with encryption function 600 shown in FIG. 7 has the same function as the storage medium with encryption function shown in the second embodiment. The difference from the second embodiment is that the clock conversion mechanism 101 is connected to the internal bus 610.
That is the bus clock. The cryptographic processing mechanism 601, the interface 602, and the memory 603 operate using the output of the clock conversion mechanism 101 as an operation clock. Since the storage medium with encryption function 600 has the clock conversion mechanism 101, it becomes difficult to analyze the operation of the encryption processing mechanism 601, the interface 602, and the memory 603 by timing analysis or power consumption analysis.

The third embodiment is not limited to the above storage medium, but is applicable to IC cards, memory cards, hard disks, PCs, PDAs, displays, speakers and other information processing devices.

Next, a fourth embodiment will be described. FIG. 8 is a diagram showing a configuration example of the information device of the present invention. The information device 800 shown in FIG. 8 includes a CPU 803, a memory 603, a protection target module 801, a non-protection target module 804, an interface 602, and an internal bus 81.
The information device 800 includes a CPU 803, a memory 603, a protection target module 801, a non-protection target module 804, and an interface 602.
Connect to 0.

The CPU 803 accesses the protection target module 801, the memory 603, the interface 602, and the non-protection module 804 via the internal bus 810, and executes the program stored in the memory 603.
Controls the entire information device 800. The CPU 803 has a clock conversion mechanism 101, and part or all of the CPU 803 operates using the output of the clock conversion mechanism 101 as an operation clock, and the other parts operate using the bus clock of the internal bus 810 as an operation clock. The CPU 803 has a mechanism for synchronizing a portion operating with the bus clock of the internal bus 810 as an operating clock and a portion operating with the output of the clock conversion mechanism 101 as an operating clock. CPU8
03 has the clock conversion mechanism 101, which makes it difficult to analyze the internal operation of the CPU 803 by timing analysis and power consumption analysis.

The memory 603 stores programs and data executed by the CPU 803. The memory 603 has a clock conversion mechanism 101. Part or all of the memory 603 operates using the output of the clock conversion mechanism 101 as an operation clock, and the other parts operate using the bus clock of the internal bus 810 as an operation clock. Memory 603
Has a mechanism for synchronizing a portion operating with the bus clock of the internal bus 810 as an operating clock and a portion operating with the output of the clock conversion mechanism 101 as an operating clock. Since the memory 603 has the clock conversion mechanism 101, the memory 603 can be analyzed by timing analysis or power consumption analysis.
Makes the internal operation analysis of the.

The protected module 801 is the internal bus 81.
It is possible to access the CPU 803, the memory 603, the interface 602, and the non-protected module 804 via 0. The protection target module 801 has a clock conversion mechanism 101. A part or all of the protection target module 801 operates using the output of the clock conversion mechanism 101 as an operation clock, and the other parts operate using the bus clock of the internal bus 810 as an operation clock. To do. The protection target module 801 has a mechanism for synchronizing a portion operating with the bus clock of the internal bus 810 as an operating clock and a portion operating with the output of the clock conversion mechanism 101 as an operating clock. The protection target module 801 is the clock conversion mechanism 1
Having 01 makes it difficult to analyze the internal operation of the protection target module 801 by timing analysis or power consumption analysis.

The unprotected module 804 is the internal bus 8
The CPU 803, the memory 603, the interface 602, and the protection target module 801 can be accessed through 10.

The interface 602 provides a function of connecting to an external device and exchanging information by one or both of wired and wireless.

The clock conversion mechanism 101 which the CPU 803, the memory 603, and the protection target module 801 have independently of each other can set different keys via the interface 602. CPU 803 and memory 60
3 and clock conversion mechanism 10 of protected module 801
If the keys set to 1 are different, the CPU
803, the memory 603, and the portion of the protected module 801 that operates using the output of the clock conversion mechanism 101 as an operation clock independently operate at different timings.

When the information device 800 is in a sealed state,
The power consumption of the entire information device 800 becomes a clue for internal analysis. The power consumption of the entire information device 800 is the CPU 803.
And the total power consumption of the memory 603 and the protection target module 801 are included. However, since the CPU 803, the memory 603, and the protection target module 801 operate independently at different timings, it is not possible to calculate each power consumption from the total power consumption. difficult.

When the same key is set in the clock conversion mechanism 101 which the CPU 803, the memory 603, and the protection target module 801 have independently, the modules having the same key internally operate at the timing when the output of the clock conversion mechanism 101 is used as the operation clock. Information can be transferred via the bus 810. When information is transferred between modules that do not have the same key or non-protected modules 804 that do not have a clock conversion mechanism, the internal bus 810 is used.
Information is transferred in synchronization with the bus clock of. The module having the clock conversion mechanism 101 has a reset signal for synchronizing the start of the output of the clock conversion mechanism 101, and operates the output of the same pattern as the operation clock when the same key is set in the clock conversion mechanism 101. .

The fourth embodiment is not limited to the above information equipment, but can be applied to an IC card, a memory card, a hard disk, a PC, a PDA, a display, a speaker, and other information processing devices.

[0061]

According to the present invention, in a semiconductor device, a storage medium, an information device, etc., an internally generated signal operates as an operation clock, and resistance to attacks such as timing analysis and power consumption analysis can be improved. .

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a device of the present invention.

FIG. 2 is a diagram showing a configuration example of a clock conversion mechanism of FIG.

FIG. 3 is a diagram showing a configuration example of a random number generation mechanism of FIG.

4 is a diagram showing a configuration example of a normalization mechanism of FIG.

5 is a flowchart for explaining an operation for explaining an operation of the normalization mechanism of FIG.

FIG. 6 is a diagram showing a configuration example of a storage medium with an encryption function of the present invention.

FIG. 7 is a diagram showing a configuration example of a storage medium with an encryption function of the present invention.

FIG. 8 is a diagram showing a configuration example of an information device of the present invention.

[Explanation of symbols]

100: device 101: Clock conversion mechanism 102: submodule 11 103: Sub module 12 104: Sub-module 21 105: submodule 22 106: Internal bus 107: Internal bus 108: Module 1 109: Module 2 110: Clock signal 111: Clock conversion mechanism output 121: Clock conversion mechanism 122: Clock conversion mechanism output 126: Internal bus 130: Bus bridge 201: PLL 202: Magnification 203: Random number generator 204: encryption key 205: Normalization mechanism 206: Condition 211: PLL output 212: Magnification output 213: Random number generator output 214: Output encryption key 216: Condition output 303: Register 305: encryption part 306: Initial value 307: buffer 311: Update request 313: Register output 315: Output of cipher section 316: Initial value output 401: longest 402: shortest 403: Comparison mechanism 404: buffer 405: Selector 406: Logic inversion 407: Counter 411: longest output 412: Shortest output 413: Comparison mechanism output 415: Selector output 416: Logic inversion output 417: Counter output 600: Storage medium with encryption function 601: Cryptographic processing mechanism 602: Interface 603: Memory 610: Internal bus 612: Interface input / output 620: Key information 800: Information equipment 801: Module to be protected 803: CPU 804: Non-protected module 810: Internal bus

Continued front page    (72) Inventor Toru Owada             1099 Ozenji, Aso-ku, Kawasaki City, Kanagawa Prefecture             Ceremony company Hitachi Systems Development Laboratory (72) Inventor Takayoshi Yawata             1099 Ozenji, Aso-ku, Kawasaki City, Kanagawa Prefecture             Ceremony company Hitachi Systems Development Laboratory F term (reference) 5B017 AA03 BA07 BB03 CA11                 5J104 AA43 AA47 NA02 NA22 NA27                       NA42

Claims (13)

[Claims] 1. A semiconductor device having a function of preventing internal analysis, comprising: an input clock signal; a clock conversion mechanism for converting and outputting the input clock signal; and an output of the clock conversion mechanism for operating as an operation clock. A semiconductor device with an internal analysis prevention function, which comprises a module. 2. A PLL that generates a signal obtained by multiplying the input clock signal based on a scaling factor.
And a random number generation mechanism that generates a random number sequence by converting the signal sequence generated by the PLL, and a normalization mechanism that generates a signal obtained by converting the random number sequence generated by the random number generation mechanism based on conditions. The semiconductor device with an internal analysis prevention function according to claim 1. 3. The clock conversion mechanism comprises an encryption key,
The semiconductor device with an internal analysis prevention function according to claim 2, wherein the random number generation mechanism generates a different random number sequence depending on the encryption key. 4. The condition, the encryption key, and the magnification include means for storing settings, and the clock conversion mechanism includes means for externally changing the settings for the condition, the encryption key, and the magnification. The semiconductor device with an internal analysis prevention function according to claim 3. 5. The clock conversion mechanism, wherein the random number generation mechanism and the normalization mechanism operate with a signal generated by the PLL as an operation clock.
Or a semiconductor device with an internal analysis prevention function according to any one of 4). 6. The random number generation mechanism outputs a ciphertext in which the output of the cryptographic processing unit is stored and output, and a ciphertext in which the output of the register is encrypted using an encryption key, and the cryptographic processing unit for the cipher 6. The semiconductor device with an internal analysis preventing function according to claim 3, 4 or 5, further comprising: a buffer storing the ciphertext output from the cipher processing unit and outputting the ciphertext as a bit string. 7. The random number generation mechanism comprises an initial value, the register stores the initial value before starting the cryptographic processing, and outputs the initial value to the cryptographic processing unit at the start of the cryptographic processing. A semiconductor device with an internal analysis prevention function according to claim 6. 8. The normalization mechanism compares a counter output with the condition and outputs a result, a counter that changes a value according to a result output of the comparison mechanism, a buffer output and a buffer output. 4. A selector for outputting one of the inversions according to the result of the comparison mechanism, and a buffer for storing and outputting the output of the selector.
8. A semiconductor device with an internal analysis prevention function according to any one of 4, 5, 6 and 7. 9. A storage medium with an encryption function for storing information encrypted, which is connected to an external device, inputs information from the external device, and outputs the information to a cryptographic processing mechanism and a memory,
An interface that inputs information from the cryptographic processing mechanism and the memory and outputs it to an external device, an internal bus that connects the interface, the cryptographic processing mechanism, and the memory, and that supplies a bus clock to the interface, the cryptographic processing mechanism, and the memory, and a bus from the internal bus. Input the clock, encrypt the information output by the interface, output to the memory,
Input the bus clock from the internal processing bus, which outputs the information output from the memory to the interface,
A memory for accumulating the information output by the interface, outputting the accumulated information to the interface, accumulating the output information encrypted by the cryptographic processing mechanism, and outputting the accumulated information to the cryptographic processing mechanism. Storage medium with encryption function. 10. The cryptographic processing mechanism comprises a clock conversion mechanism for outputting a signal converted from the internal bus clock, and has a portion which operates using the signal converted by the clock conversion mechanism as an operation clock. Storage medium with encryption function. 11. The storage medium with a cryptographic function according to claim 9, wherein the cryptographic processing mechanism includes means for processing a cryptographic algorithm used for authentication and authenticating an external device. 12. A storage medium with a cryptographic function according to claim 9, wherein the clock conversion mechanism is connected to an internal bus and supplies a bus clock obtained by converting an input clock. 13. A clock conversion mechanism is provided, which comprises a portion that operates with an input clock as an operating clock and a portion that operates with an output obtained by converting the input clock by the clock conversion mechanism as an operating clock. The internal bus is connected to the internal bus. The protected module that exchanges information with the non-protected module via the interface, the non-protected module that connects to the internal bus and exchanges information with the protected module through the internal bus, and connect with the external device. An information device comprising an interface for exchanging information from an external device, connecting to an internal bus, and exchanging information with a protection target module and a non-protection target module via the internal bus.