JP2003337560A - Circuit of driving display device, its control method, portable telephone and portable electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit of driving a display device and its control method in which electric power consumption is reduced, a highly precise output is provided and the cost is reduced. <P>SOLUTION: When a positive polarity gray scale voltage VP is inputted into each of gray scale output circuits 100-1 to 100-n, an offset voltage of an operational amplifier 103 is stored in a capacitor 121, and the output of the amplifier 103 is corrected using the offset voltage stored in the capacitor 121. When a negative polarity gray scale voltage VN is inputted, the offset voltage of the amplifier 103 is stored in a capacitor 122 and the output of the amplifier 103 is corrected utilizing the offset voltage stored in the capacitor 122. Signals that are necessary to drive the display device are selected by selecting circuits 2-1 to 2-m from the corrected output signals of the circuits 100-1 to 100-n and the selected signals are outputted into data lines. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for a display device, a control method therefor, a mobile phone and a portable electronic device, and more particularly to a drive circuit for a display device which performs multi-gradation display.

[0002]

2. Description of the Related Art Liquid crystal display devices are used as display devices for various devices such as notebook personal computers because they have the features of thinness, light weight and low power consumption. Among them, the liquid crystal display device using the active matrix drive system is in high demand because of its features such as high-speed response, high-definition display, and multi-gradation display.

A display portion of a liquid crystal display device using an active matrix driving system generally includes a semiconductor substrate on which transparent pixel electrodes and thin film transistors (TFTs) are arranged, and a counter substrate on which one transparent electrode is formed on the entire surface. Have
It has a structure in which a liquid crystal is sealed between these two substrates facing each other. Then, a predetermined voltage is applied to each pixel electrode by controlling the TFT having a switching function, and the transmittance of the liquid crystal is changed by the potential difference between each pixel electrode and the counter electrode provided on the counter substrate to display an image. it's shown. Data lines for transmitting a plurality of level voltages (grayscale voltages) applied to each pixel electrode and scan lines for transmitting a switching control signal of the TFT are wired on the semiconductor substrate, and the grayscale voltage of each pixel electrode The application is performed via the data line. Various data line driving circuits have been used as a method for driving the data lines. Among them, a typical example of the data line driving circuit will be described below.

FIG. 26 is a diagram showing the structure of a conventional first data line drive circuit. The drive circuit shown in FIG. 26 uses a plurality of gradation voltages generated by the resistor string 401
Impedance conversion is performed by operational amplifiers (op amps) 403-1 to 403-n (n is a positive integer) provided for each gradation voltage, and the voltage required for driving is selected from the impedance-converted gradation voltages. Selection circuit (selector)
The data lines are driven by selecting from 402-1 to 402-m (m is a positive integer) and outputting to the data line load. This driving circuit outputs each of a plurality of grayscale voltages generated by the resistor string 401 to an operational amplifier 403.
Since the impedance conversion is performed by −1 to 403-n, the data line driving capability is high, and the resistance value of the resistor string 401 that generates the grayscale voltage is increased to increase the resistance string 4.
It is possible to reduce the current flowing in the drive circuit 01 and reduce the power consumption of the drive circuit.

On the other hand, in the case of a large liquid crystal display device, since the number of data lines is large and the capacity of each data line is large, the data line driving circuit is required to have a large driving ability.
In the drive circuit of FIG. 26, a plurality of data lines may be driven by one gray scale voltage, so that the drive capability becomes insufficient when used in a large liquid crystal display device. Therefore, a conventional second data line driving circuit shown in FIG. 27 is given as a data line driving circuit that can obtain a sufficient driving ability even when used in a large-sized liquid crystal display device. The drive circuit of FIG. 27 selects a gray scale voltage required for driving from among a plurality of gray scale voltages generated by the resistor string 401, as a selection circuit (selector) 4
02-1 to 402-m, and operational amplifiers 404-1 to 40-40 provided as data line output circuits for each data line.
Impedance conversion is performed by 4-m, and a predetermined gradation voltage is applied to each data line by outputting to one data line load. This drive circuit has sufficient drive capability even when it is used in a large-sized liquid crystal display device because the grayscale voltage selected by the selection circuit is impedance-converted by an operational amplifier provided for each data line.

Further, in a liquid crystal display device which performs multi-gradation display, since the potential difference between adjacent gradation voltages is small, the operational amplifier is required to have high output accuracy. However, the operational amplifier has a problem that an offset voltage is generated due to the characteristic variation of the active elements constituting the operational amplifier. In order to solve this problem, an operational amplifier having an offset correction function may be used in each of the data line output circuits 404-1 to 404-m of the drive circuit shown in FIG. Various methods have been used so far to correct the offset voltage generated in the operational amplifier. Among them, Japanese Patent Laid-Open No. 9-244590 discloses a typical example of an operational amplifier having an offset correction means using a capacitor. The output circuit described is mentioned.

FIG. 28 is a diagram showing a configuration of an output circuit described in Japanese Patent Laid-Open No. 9-244590. In FIG. 28, the input voltage Vin supplied from the outside is input to the positive phase input terminal of the operational amplifier 503 via the input terminal 501 of the output circuit. The output voltage Vout of the operational amplifier 503 is output to the outside via the output terminal 502 of the output circuit.
Switches 506 and 507 are connected in series between the positive phase input terminal of the operational amplifier 503 and the output terminal of the operational amplifier 503. A capacitor 505 is connected between the connection point between the switches 506 and 507 and the negative phase input terminal of the operational amplifier 503. A switch 508 is connected between the negative-phase input terminal of the operational amplifier 503 and the output terminal of the operational amplifier 503. The capacitor 505 and the switches 506 to 508 form an offset correction circuit 504.

Next, the operation of the output circuit shown in FIG. 28 will be described with reference to the timing chart shown in FIG.
First, during the period T1 in the previous state, only the switch 507 is turned on and the other switches 506 and 5 are turned on.
08 is turned off. As a result, the operational amplifier 5
03 output terminal and the negative phase input terminal are connected via a capacitor 505. In this state, the voltage level of the output voltage Vout is the same as the previous output voltage.

In the period T2, in addition to the switch 507,
The switch 508 is turned on. When the voltage level of the input voltage Vin changes, the output voltage Vout changes accordingly and becomes Vin + Voff including the offset voltage Voff. Further, when the switches 507 and 508 are turned on, both ends of the capacitor 505 are connected to the output terminal of the operational amplifier 503 to be short-circuited.
The potentials at both ends of 05 are both Vout (= Vin + Voff) due to the output of the operational amplifier 503.

In a period T3, the switch 508 is turned on while the switch 508 is kept on, and then the switch 5 is turned on.
Turn on 06. As a result, one end of the capacitor 505 is connected to the input terminal 501, and the potential at one end of the capacitor 505 changes from Vout to Vin. Switch 50
Since 8 is on, the potential at the other end of the capacitor 505 remains the output voltage Vout. Therefore, the capacitor 50
The voltage applied to 5 is Vout-Vin = Vin + Voff
Since −Vin = Voff, the capacitor 505 is charged with electric charges corresponding to the offset voltage Voff.

During period T4, switches 506 and 508 are
Is turned off, and then the switch 507 is turned on. By turning off the switches 506 and 508, the capacitor 505 is directly connected between the negative phase input terminal and the output terminal of the operational amplifier 503, and the offset voltage Voff is held in the capacitor 505. By turning on the switch 507, the offset voltage Voff is applied to the negative phase input terminal of the operational amplifier 503 with reference to the potential of the output terminal. As a result, the output voltage Vout of the operational amplifier 503 is V
out = Vin + Voff-Voff = Vin, the offset voltage is canceled, and the operational amplifier 503 can output a highly accurate voltage.

In the timing chart of FIG. 29,
Although there is no delay in each switch and the switch control by the control means 3 is performed at the same time, when each switch has a delay, the switch 506 is turned on before the switch 507 is turned off in the period T3. Switch control is performed in consideration of the delay so that the switch 507 does not turn on before the switches 506 and 508 turn off in the period T4.

[0013]

In recent years, mobile devices such as mobile phones and personal digital assistants have rapidly spread, and the demand for mobile displays as display devices for mobile devices has increased significantly. Conventionally, low power consumption has been the center of performance required for mobile displays, but with the spread of mobile devices, high-definition, multi-gradation display capability is also required.

In a liquid crystal display device which performs multi-gradation display, since the potential difference between the gradation voltages is small, the drive circuit is required to have high output accuracy. However, in the drive circuit shown in FIG. 26, an offset voltage is generated in each of the operational amplifiers 403-1 to 403-n due to the characteristic variation of the transistors forming the operational amplifier, and thus the output voltage accuracy varies. There is a problem that the display quality is degraded. In the drive circuit shown in FIG. 27, similarly to the drive circuit in FIG. 26, an offset voltage is generated in each of the operational amplifiers 404-1 to 404-m due to the characteristic variation of the transistors included in the operational amplifier. There is a problem that variations in voltage accuracy occur and color unevenness occurs. Further, in a liquid crystal display device that performs high-definition display, the number of data lines is generally larger than the number of gray scales, and in the drive circuit of FIG. 27, the data line output circuits 404-1 to 404-for m data lines.
Since m is provided, a large number of circuits are required. Therefore, there is a problem that the required area increases and the cost increases.

Even when the output circuit shown in FIG. 28 is used for each data line output circuit of the drive circuit shown in FIG. 27, in a liquid crystal display device having a large number of data lines, each of the m data lines is provided. Since the output circuit shown in FIG. 28 is provided,
The required area increases and the cost increases.

Further, in the drive circuit shown in FIG. 27, the voltage level of the input signal input to each data line output circuit may differ for each output period. When the voltage level of the input signal changes, the magnitude of the offset voltage generated in the operational amplifier also changes. This offset voltage fluctuation is mV
Although it is a unit change, this mV unit change affects the gradation display of the liquid crystal display device. Therefore, FIG.
When the output circuit shown in FIG. 28 is used for each data line output circuit of the drive circuit shown in FIG. 7, calculation is performed for each output period by changing the voltage level of the input signal to each output circuit for each output period. Since the magnitude of the offset voltage generated in the amplifier 503 is different, in order to realize high-precision output in each output circuit and realize high-definition display and multi-gradation display in the liquid crystal display device, each output circuit outputs each output period. It is necessary to perform the offset correction operation. However, if the offset correction operation is performed for each output period, the capacitor that stores the offset voltage must be charged and discharged for each output period, which causes a problem that power consumption increases.

If the offset correction operation is performed by switch control, the output accuracy of each output circuit may be reduced due to the influence of capacitive coupling that occurs during switching. This is because the MOS transistor used for each switch has a parasitic capacitance, so that the electric charge is moved through the parasitic capacitance at the time of switching, so that the electric charge corresponding to the offset voltage stored and held in the capacitor has an influence. It is to receive. Although it is possible to suppress a decrease in output accuracy by increasing the capacity of the capacitor that stores the offset voltage, increasing the capacity causes an increase in power consumption due to charge / discharge of the capacitor due to the offset correction operation performed for each output period. There is.

In Japanese Patent Laid-Open No. 2001-100704, a plurality of adjusting resistors are provided in a resistance dividing circuit for dividing the voltage of the liquid crystal driving power source, and the offset voltage of each amplifier is reduced by the size of these resistors. A technique for increasing the output accuracy is described. However, since the resistors themselves have variations, the offset voltage of each amplifier cannot be sufficiently reduced depending on the size of the resistors, and thus sufficient output accuracy cannot be obtained.

An object of the present invention is to provide a drive circuit of a display device and a control method thereof for realizing low power consumption, high precision output and low cost.

[0020]

A drive circuit of a display device according to the present invention is provided for a grayscale voltage generating means for generating a plurality of grayscale voltages and a plurality of output terminals of the grayscale voltage generating means. A plurality of grayscale output circuits each having an operational amplifier that impedance-converts an input signal input through the output terminal of the grayscale voltage generation means, and display is performed from the output signals of the plurality of grayscale output circuits. A driving circuit of a display device, comprising: a selecting unit that selects a signal necessary for driving the device, wherein each of the plurality of grayscale output circuits comprises:
It has a storage unit that stores in advance each of the offset voltages generated in the operational amplifier according to the grayscale voltage level of the input signal, and outputs the output of the operational amplifier using the offset voltage stored in the storage unit. A control means for controlling each of the plurality of gradation output circuits for correction is included.

Further, in the drive circuit, the storage means of each of the plurality of gradation output circuits comprises a plurality of capacitors for respectively storing the offset voltage.

In the drive circuit, the control means selects one capacitor from the plurality of capacitors in the first period of one output period according to the gradation voltage level of the input signal. Each of the plurality of gradation output circuits is controlled to store the offset voltage of the operational amplifier in the selected capacitor. In the drive circuit, the control means may correct the output of the operational amplifier by using the offset voltage stored in the selected capacitor during the second period of the one output period. It is characterized in that each of the gradation output circuits is controlled.

Another drive circuit according to the present invention is provided for each of grayscale voltage generating means for generating a plurality of grayscale voltages and a plurality of output terminals of the grayscale voltage generating means, and the grayscale voltage generating means is provided. A plurality of grayscale output circuits each having an operational amplifier that impedance-converts a grayscale voltage input through the output terminal of the means, and a grayscale voltage output from the plurality of grayscale output circuits. A driving circuit for a display device, comprising: a selecting unit that selects a voltage required for driving, wherein each of the plurality of grayscale output circuits has one capacitor, The offset voltage generated in the operational amplifier is stored in the capacitor, and the stored offset voltage is used to control each of the plurality of gradation output circuits to correct the output of the operational amplifier. In each output period after one output period, control means for controlling each of the plurality of gradation output circuits to correct the output of the operational amplifier using the offset voltage stored in the capacitor in the one output period. It is characterized by including.

Still another drive circuit according to the present invention is provided for a grayscale voltage generating means for generating a plurality of grayscale voltages and a plurality of output terminals of the grayscale voltage generating means, respectively.
A plurality of grayscale output circuits each having an operational amplifier that impedance-converts an input signal input via the output terminal of the grayscale voltage generation means, and a display device of the output signals of the plurality of grayscale output circuits. A drive circuit for a display device, including a selection means for selecting a signal required for driving,
One of a pair of input terminals of the operational amplifier is connected to a circuit input terminal of the grayscale output circuit to which an input signal is supplied, and each of the plurality of grayscale output circuits includes two capacitors and the pair of grayscale output circuits. A first switch connected between the other of the input terminals of the operational amplifier and the output terminal of the operational amplifier; a second switch whose one end is connected to one of the pair of input terminals; A third switch connected between the other end and the output terminal, two capacitor selection switches respectively connected between the other end of the second switch and one end of the two capacitors, Two capacitor selection switches respectively connected between the other of the pair of input terminals and the other ends of the two capacitors, and among the two capacitors according to the polarity of the gradation voltage of the input signal. of Characterized in that it comprises a switch control means for controlling the switch of each of said plurality of tone output circuit in order to store the offset voltage of the operational amplifier to the capacitor.

According to the control method of the present invention, the gradation voltage generating means for generating a plurality of gradation voltages and the plurality of output terminals of the gradation voltage generating means are provided respectively, A plurality of grayscale output circuits each having an operational amplifier and a plurality of capacitors for impedance-converting an input signal input via an output terminal, and necessary for driving the display device from the output signals of the plurality of grayscale output circuits A method of controlling a drive circuit of a display device, comprising: selecting means for selecting an appropriate signal from among the plurality of capacitors according to a grayscale voltage level of the input signal during a first period of one output period. A first step of selecting one capacitor and controlling each of the plurality of gradation output circuits to store the offset voltage of the operational amplifier in the selected capacitor; A second step of controlling each of the plurality of grayscale output circuits to correct the output of the operational amplifier using the offset voltage stored in the selected capacitor during the second period of the output period; It is characterized by including.

Another control method according to the present invention is provided for a grayscale voltage generating means for generating a plurality of grayscale voltages and a plurality of output terminals of the grayscale voltage generating means, and the grayscale voltage generation means is provided. A plurality of gradation output circuits each having an operational amplifier for impedance-converting an input signal input via the output terminal of the means, and a signal necessary for driving the display device from among the output signals of the plurality of gradation output circuits Selecting means for selecting, and one of a pair of input terminals of the operational amplifier is connected to a circuit input terminal of the gradation output circuit to which an input signal is supplied, and each of the plurality of gradation output circuits. Is a first capacitor connected between the two capacitors and the other of the pair of input terminals and the output terminal of the operational amplifier.
Switch, a second switch having one end connected to one of the pair of input terminals, a third switch connected between the other end of the second switch and the output terminal, Two capacitor selection switches respectively connected between the other ends of the two switches and one ends of the two capacitors, and two capacitors selection switches respectively connected between the other of the pair of input terminals and the other ends of the two capacitors. A method for controlling a drive circuit of a display device having two capacitor selection switches, wherein one of the two capacitors has an offset voltage of the operational amplifier according to a polarity of a grayscale voltage of the input signal. To control the switch of each of the plurality of gradation output circuits to store.

The operation of the present invention is as follows. By storing in advance the offset voltage generated in the operational amplifier according to the grayscale voltage level of the input signal from the grayscale voltage generation means in the storage means of each grayscale output circuit, the grayscale voltage of the input signal The power consumption can be reduced as compared with the conventional technique in which the offset voltage that has already been stored is erased and a new offset voltage is stored each time the level changes.

Further, in each gradation output circuit, a plurality of capacitors are used as storage means, and one capacitor selected in accordance with the gradation voltage level of the input signal stores and holds the offset voltage. The offset voltage is used to correct the output of the operational amplifier. Therefore, the output of the operational amplifier can be corrected with high precision, and high-precision output is possible. Further, once the offset voltage is stored and held, when the next input signal having the same gradation voltage level is supplied to the gradation output circuit, the same capacitor is selected and the offset voltage held in this capacitor is held. Since the output of the operational amplifier is corrected using
There is almost no power consumption due to charge / discharge of the capacitor, and it is possible to minimize power consumption.

The gradation output circuit is provided for each of the plurality of output terminals of the gradation voltage generating means, that is, since the gradation output circuit is provided for each gradation, the number of gradations is When the number of data lines is smaller than the number of data lines, the number of output circuits can be reduced as compared with a configuration in which an output circuit is provided for each data line. Therefore, the area of the circuit can be reduced and the cost can be reduced.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of a drive circuit of a display device according to a first embodiment of the present invention.
The drive circuit shown in FIG. 1 can be applied to a drive circuit of a display device having two polarities.
It can be applied to a drive circuit of a liquid crystal display device having two polarities of positive polarity and negative polarity.

In FIG. 1, the driving circuit of the liquid crystal display device according to the first embodiment of the present invention comprises a plurality of positive gradation voltages VP1, VP2, ..., VPn (n is a positive integer),
Alternatively, a plurality of negative gradation voltages VN1, VN2, ...
.., VNn, and the grayscale voltage VP1 to VPn or VN from the grayscale voltage generation means 1.
1 to VNn amplifying gradation output circuits 100-1 to 100
-N, selection circuits (selectors) 2-1 to 2-m (m is a positive integer), a gradation voltage generation means 1 and a control means 3 for controlling each gradation output circuit.

Each of the selection circuits 2-1 to 2-m has a voltage necessary for driving the display device according to the video data signal from the gradation voltages amplified by the gradation output circuits 100-1 to 100-n. To output to the data line. The gradation output circuits 100-1 to 100-n are provided for the n output terminals of the gradation voltage generating means 1, respectively. That is, a gradation output circuit is provided for each gradation. The gradation voltage generating means 1 is composed of, for example, a resistance string in which resistance elements are connected in series, and a gradation voltage having a positive polarity or a negative polarity from the connection terminal in the resistance string to the gradation output circuits 100-1 to 100-n. Are output respectively.

It is necessary to apply an AC voltage to the liquid crystal used in the liquid crystal display device in order to prevent deterioration. As a method of AC driving the liquid crystal, there is a method of fixing a common voltage (opposite voltage) and performing AC driving. A method is known in which AC drive is performed by changing the common voltage according to the polarity. The former drive system is called the common DC drive system,
This is a method in which the common voltage is fixed and the voltage applied to the liquid crystal is alternately inverted between positive and negative with reference to the common voltage.
The latter drive method is called a common inversion drive method, and is a method in which the common voltage is changed according to the polarity and the voltage applied to the liquid crystal is alternately inverted between positive and negative with reference to the common voltage.

FIG. 2 is a diagram showing the waveform of the common voltage of one pixel and the waveform of the signal voltage with the maximum amplitude of the signal voltage applied to the liquid crystal, and FIG. 2 (a) shows each waveform by the common DC drive method. FIG. 2B is a diagram showing each waveform according to the common inversion driving method. In FIGS. 2A and 2B, the polarity inversion is performed for each frame, and the maximum voltage applied to the liquid crystal is 5V. Figure 2
Referring to (a), in the common DC driving method, the common voltage is constant at 5V. Therefore, in order to apply the maximum applied voltage of 5V to the liquid crystal on the basis of the common voltage, the signal voltage range is 0 to 10V. Becomes On the other hand, referring to FIG. 2B, in the common inversion driving method, the common voltage is changed to 0 V in one frame and 5 V in the next frame, and the maximum voltage of 5 V applied to the liquid crystal is set with reference to the common voltage. In order to apply, the signal voltage when the common voltage is 0V is 5V, the signal voltage when the common voltage is 5V is 0V, and the signal voltage range is 0 to 5V.

The drive circuit of the display device according to the first embodiment of the present invention can use the common DC drive system and the common inversion drive system. FIG. 3 is a diagram showing a configuration example of the gradation voltage generating means 1 of the drive circuit shown in FIG.
FIG. 3A is a diagram showing a configuration example of the grayscale voltage generation means 1 when the common DC drive method is used, and FIG. 3B is a diagram of the grayscale voltage generation means 1 when the common inversion drive method is used. It is a figure which shows the structural example.

Referring to FIG. 3A, in the common DC driving method, the high power supply voltage V1 is applied to one end of the resistor string, and the low power supply voltage V2 is applied to the other end of the resistor string. Positive gradation voltages VP1 to VPn and negative gradation voltages VN from the respective connection terminals
1 to VNn are generated. When the common DC drive method has a positive polarity, the switches 11-1 to 11-n are turned on and the switches 12-1 to 12-n are turned off, so that the grayscale voltages VP1 to VPn of the positive polarity are selected. And output. Further, in the case of negative polarity, the switches 11-1 to 11-1
11-n is turned off and the switches 12-1 to 12-n are turned on, so that the grayscale voltages VN1 to VNn of negative polarity are generated.
Is selected and output.

On the other hand, referring to FIG. 3B, in the case of the positive polarity in the common inversion drive system, the switch 13-
1 and 14-2 are turned on, and switches 13-2 and 14
When -1 is turned off, the high-potential power supply voltage V3 is applied to one end of the resistor string, the low-potential power supply voltage V4 is applied to the other end of the resistor string, and the positive gradation voltage VP1 is applied from each connection terminal of the resistor string. ~ VPn is generated and output. When the polarity is negative, the switch 13-1
And 14-2 are turned off, and switches 13-2 and 14-
When 1 is turned on, the low-potential power supply voltage V4 is applied to one end of the resistor string, the high-potential power supply voltage V3 is applied to the other end of the resistor string, and the gradation voltages VN1 to VN1 of negative polarity are applied from the connection terminals of the resistor string. VNn is generated and output. As described above, in the common inversion drive method, the potential difference between the common voltage and each resistor string terminal can be made equal in the positive polarity and the negative polarity by inverting the voltage applied to both ends of the resistor string according to the polarity. .

Returning to FIG. 1, the gradation output circuits 100-1 to 100-1
Each of 00-n includes a circuit input terminal 101, a circuit output terminal 102, an operational amplifier 103, and an offset correction circuit 104. The positive or negative gradation voltage output from the gradation voltage generating means 1 is input to the input terminal 101. The voltage follower operational amplifier 103 outputs a voltage equal to the positive or negative gradation voltage output from the gradation voltage generating means 1 to the output terminal 1.
Output to 02.

The offset correction circuit 104 includes a switch 1
11 to 113, two capacitors 121 and 122,
It is composed of a capacitor selecting means including switches 131 and 132 and switches 141 and 142. The switch 111 is connected between the negative phase input terminal of the operational amplifier 103 and the output terminal 102, and the switches 112 and 113 are connected.
Are connected in series between the input terminal 101 and the output terminal 102. One end of each of the two capacitors 121 and 122 is commonly connected to the connection point of the switches 112 and 113 via the switches 131 and 132, and the other end of each of the capacitors 121 and 122 is connected to the switch 14.
1, 142 are connected to the negative phase input terminal of the operational amplifier 103.

FIG. 4 is a diagram for explaining the operation of the control means 3 shown in FIG. In FIG. 4, the control means 3 controls the gradation voltage generation means 1 and each gradation output circuit based on an external signal and a polarity signal.

First, the control operation of the control means 3 with respect to the gradation voltage generation means 1 will be described with reference to FIG. 4, FIG. 1 and FIG.

In FIG. 4, the control means 3 is the control means 3
According to the external signal and the polarity signal input to
The on / off control of the switch of the gradation voltage generating means 1 as shown in (a) and (b) is performed. The above-mentioned external signal means a signal supplied from the outside of the drive circuit of FIG. 1, and is a signal that is a source of the control signal of each switch. Normally, in the case of a liquid crystal display device, a polarity signal and an external signal are supplied from a controller (not shown).

Referring to FIG. 1 and FIG. 3A, in the common DC drive type gradation voltage generating means 1, the polarity signal has a positive polarity according to an external signal and a polarity signal supplied to the control means 3 from the outside. In this case, the switches 11-1 to 11-n
Is turned on and the switches 12-1 to 12-n are turned off to generate positive gradation voltages (VP1 to VPn) and output them to each gradation output circuit. When the polarity signal has a negative polarity, the grayscale voltage generation means 1 switches the switches 11-1 to 11-1.
By turning off the switch 11-n and turning on the switches 12-1 to 12-n, the gray scale voltage of negative polarity (VN1 to VNn)
To the gradation output circuit.

Further, referring to FIGS. 1 and 3 (b),
The grayscale voltage generating means 1 of the common inversion drive system turns on the switches 13-1 and 14-2 according to the external signal and the polarity signal supplied from the outside to the control means 3 when the polarity signal is positive. By turning off 13-2 and 14-1, positive gradation voltage (VP1 to VP
n) is generated and output to each gradation output circuit. When the polarity signal has a negative polarity, the grayscale voltage generating means 1 turns off the switches 13-1 and 14-2, and switches 13-2 and 1
4-1 is turned on, so that the gradation voltage (V
N1 to VNn) are output to the gradation output circuit.

Next, the gradation output circuit 100- of the control means 3
The control operation for 1 to 100-n will be described. In FIG. 4 and FIG. 1, the control unit 3 controls ON / OFF of the switches of each gradation output circuit according to the external signal and the polarity signal input to the control unit 3. In each gradation output circuit, the operation of the capacitor selecting unit composed of the switches 131, 132 and 141, 142 operates so as to select one of the capacitors 121, 122 according to the polarity signal supplied from the outside to the control unit 3. Done. That is, the control means 3 controls the capacitors 121, 121 according to the gradation voltage level of the input signal of each gradation output circuit.
Switch 131, 132, 141, 142 of each gradation output circuit so as to select one capacitor from 122
To control. For example, the control unit 3 selects the capacitor 121 of each grayscale output circuit when the polarity signal exhibits a positive polarity, that is, when the grayscale voltage level of the input signal of each grayscale output circuit is a positive grayscale voltage. When the polarity signal has a negative polarity, that is, when the grayscale voltage level of the input signal of each grayscale output circuit is a negative grayscale voltage, the capacitor 122 of each grayscale output circuit is selected. Control accordingly. Further, the control means 3 controls the operation of each gradation output circuit by controlling the switches 111 to 113 of each gradation output circuit.

Returning to FIG. 1, each of the selection circuits 2-1 to 2-m has a gradation output circuit 100-1 according to a video data signal.
The voltage required for driving is selected from the gradation voltages current-amplified by the operational amplifiers 103 to 100-n and output to the data line.

Next, the operation of the drive circuit of the display device according to the first embodiment of the present invention will be described. FIG. 5 is a timing chart showing an operation example of each gradation output circuit of the drive circuit shown in FIG. In FIG. 5, in the case where the positive and negative polarity grayscale voltages are periodically and alternately output from each of the n output terminals of the grayscale voltage generation means 1 of FIG. 1, the positive polarity grayscale voltage is A first output period, which is an output period during which the output is performed, and a second output period, which is an output period during which a negative gradation voltage is output.
The state of the switch of each gradation output circuit in two output periods of the output period is shown. In addition, each 1 output period,
The operation amplifier 103 is composed of two periods, a first period T01 for performing an offset correction operation (offset voltage storage operation) and a second period T02 for performing a correction output operation, and the switch 111 of each gradation output circuit. ~ 113 and the switches 131, 132, 141, 142 are controlled by the control means 3.

Referring to FIGS. 5 and 1, first, in the first output period which is the positive output period, the switches 131,
The capacitor 121 is selected by turning on the switch 141 and turning off the switches 132 and 142. Also,
In the first period T01 of the first output period, the switch 1
When the switches 11 and 112 are turned on and the switch 113 is turned off, the output voltage Vout of the operational amplifier 103 becomes equal to the input voltage Vi.
It is Vin + Voff in which the offset voltage Voff is included in n. At this time, the potential of one terminal of the capacitor 121 becomes the input voltage Vin and the other terminal becomes Vout, so that the offset voltage generated in the operational amplifier 103 is generated in the capacitor 121 according to the positive gradation voltage which is the input voltage. Voff
The electric charge corresponding to is charged.

In the second period T02 of the first output period, the switches 111 and 112 are turned off and the switch 113 is turned on. When the switches 111 and 112 are turned off, the capacitor 121 is directly connected between the negative phase input terminal of the operational amplifier 103 and the output terminal 102, and the capacitor 121 holds the offset voltage Voff. By turning on the switch 113, the offset voltage Voff is applied to the negative-phase input terminal of the operational amplifier 103 with reference to the potential of the output terminal 102. As a result, in each of the gradation output circuits 100-1 to 100-n, the output voltage Vou
t becomes Vout = Vin + Voff−Voff = Vin, the offset voltage is canceled, and an output voltage equal to the input voltage Vin can be obtained.

Next, in the second output period, which is a negative output period, the switches 131 and 141 are turned off and the switches 132 and 142 are turned on, so that the capacitor 1 is turned on.
22 is selected. The first period T01 and the second period T02 of the second output period are the first period T0 of the first output period.
The switches 111 to 11 as in the first and second periods T02.
3 is controlled. As a result, the gradation output circuit 100-1
In each of 100 to 100-n, the offset voltage generated in the operational amplifier 103 in accordance with the negative gray scale voltage which is the input voltage is charged in the capacitor 122, and the offset voltage is canceled as in the first output period.

Even in each output period (not shown) after the lapse of the second output period, the offset voltage is corrected by controlling each switch according to the polarity as described above, and the output voltage equal to the input voltage can be obtained. Gradation output circuit 1
The selection circuits 2-1 to 2-m select voltages necessary for driving from the gradation voltages current-amplified by 00-1 to 100-n, and output to the data lines.

The timing chart of FIG. 5 shows the case where the switches are not delayed and the switch control by the control means 3 is performed at the same time. However, when the switches have a delay, the first period Before the switch 113 is turned off at T01, the switches 111 and 1
The switch control is performed in consideration of the delay so that the switch 12 is not turned on and the switch 113 is not turned on before the switches 111 and 112 are turned off in the second period T02.

The magnitude of the offset voltage generated in the operational amplifier 103 varies depending on the magnitude of the input voltage, but in the present embodiment, two gray scales of positive polarity and negative polarity which are the input voltages input to each gray scale output circuit. Since the two capacitors respectively associated with the voltages are provided, the offset voltage generated in the operational amplifier 103 when the positive gradation voltage is input is stored and held in the capacitor 121, and the negative gradation voltage is stored. The offset voltage generated in the operational amplifier 103 when is input can be stored and held in the capacitor 122. Once the offset voltage is stored and held in each of these two capacitors, there is no need to charge and discharge the capacitors during the output period when the grayscale voltage of the same polarity is input next time, and it is possible to avoid the capacitance coupling that occurs during switching. All that is needed is to replenish the changed charge. Therefore, the capacitor consumes almost no power due to charge / discharge.

Further, if the offset voltage is stored once in each capacitor, there is almost no power consumption due to charging / discharging. Therefore, the power consumption is increased even if the capacitance of each capacitor is increased in order to suppress the effect of capacitive coupling that occurs during switching. The output accuracy can be improved without doing so.

From the above, according to the first embodiment of the present invention, by using the gradation output circuit having low power consumption and highly accurate offset correction function, low power consumption and high precision output can be achieved. A possible driving circuit of the display device can be realized.

Further, since the number of gradations (n) is generally smaller than the number of data lines (m) in the liquid crystal display device used in the present mobile phones, it is output to m data lines respectively as shown in FIG. Compared with the configuration provided with a circuit, FIG.
The number of circuits can be reduced in the drive circuit shown in (1), and thus cost reduction can be realized. For example, 4096 colors and 12 pixels are used in current mobile phones.
In a 0 × 160 liquid crystal display device, the number of gradations is 16, the number of data lines is 360 (120 × RGB), and the number of gradations is significantly smaller than the number of data lines.

Further, when a plurality of data lines are driven by the same gray scale voltage, in the drive circuit shown in FIG. 1, the plurality of data lines are driven by the gray scale voltage amplified by the common gray scale output circuit. Therefore, the output voltage does not vary from one data line to another.

In the drive circuit shown in FIG. 1, the gradation voltage generated by the gradation voltage generating means 1 is amplified by the gradation output circuit, and the amplified voltage is selected and selected by the selection circuit. Output voltage to data line load. Therefore, depending on the selection result of the selection circuit, all the data lines may be driven by one gradation output circuit.
However, a small display having a low definition such as a mobile display has a sufficiently small data line capacity, and can be driven sufficiently even in this case.

Further, the operational amplifier used in each gradation output circuit of the drive circuit shown in FIG. 1 may be of any form.

FIG. 6 is a timing chart showing another operation example of each gradation output circuit of the drive circuit shown in FIG. In FIG. 5, the offset correction operation (offset voltage storage operation) is always performed in each output period, but in FIG. 6, the first M-th output period (M is a positive even number equal to or greater than 4) within the first output period. The difference is that the offset correction operation is performed only in the first and second output periods. It is necessary to set the predetermined M output periods to a period in which the output accuracy of the gradation output circuit does not decrease due to leakage.

The operation of each gradation output circuit according to the timing chart of FIG. 6 is controlled by the control means 3. FIG. 7 is a diagram showing the control contents of the control means 3 when operating each gradation output circuit of FIG. 1 according to the timing chart of FIG. In FIG. 7, the control means 3
Controls the grayscale voltage generation means 1 and each grayscale output circuit according to an external signal, a polarity signal and an offset correction operation signal which are externally supplied to the control means 3. In the figure, the gradation voltage generating means 1 and the switches 131, 132, 141 and 142 of each gradation output circuit are externally controlled by the control means 3.
The same control as in FIG. 4 is performed according to the polarity signal supplied to. The switches 111 to 113 of each gradation output circuit perform the operations in the first and second output periods in which the offset correction operation of FIG. 6 is performed when the offset correction operation signal is at the H (High) level, and the offset correction operation signal In the case of L (Low) level, the operation in the third to Mth output periods is performed in which only the correction voltage is output.

Referring to FIGS. 6 and 1, in the first and second output periods, the same control as the switch control in the first and second output periods of FIG. 5 is performed. Therefore, in the first output period, the offset voltage generated in the operational amplifier 103 according to the positive gradation voltage input to each gradation output circuit is charged and held in the capacitor 121, and the capacitor 121 is held.
The operational amplifier 103 using the offset voltage stored in
By correcting the output of, the output voltage equal to the input voltage can be obtained in each gradation output circuit.

Similarly, in the second output period, the operational amplifier 1 is operated according to the negative gradation voltage input to each gradation output circuit.
The offset voltage generated at 03 is charged and held in the capacitor 122, and the output of the operational amplifier 103 is corrected using the offset voltage stored in the capacitor 122, so that an output voltage equal to the input voltage is obtained in each gradation output circuit. be able to.

Next, of the third to Mth output periods, in the output period (positive output period) in which the positive grayscale voltage is input to each grayscale output circuit, the positive polarity in the first output period. Since the electric charge corresponding to the offset voltage generated in the operational amplifier 103 according to the gradation voltage is stored and held in the capacitor 121, the output of the operational amplifier 103 can be corrected without performing the offset correction operation performed in the period T01. it can.

Similarly, in the output period (negative output period) in which the negative grayscale voltage is input to each grayscale output circuit among the third to Mth output periods, the negative polarity is output in the second output period. Since the electric charge corresponding to the offset voltage generated in the operational amplifier 103 according to the gradation voltage is stored and held in the capacitor 122, the output of the operational amplifier 103 can be corrected without performing the offset correction operation performed in the period T01. it can.

By operating the drive circuit shown in FIG. 1 by the control means 3 according to the operation example of FIG. 6, the offset correction operation is performed only in the first and second output periods in the first to Mth output periods. The correction voltage can be output without performing the offset correction operation in the subsequent third to Mth output periods. Therefore, the power consumption in the first to Mth output periods can be suppressed more than the operation according to the timing chart of FIG.

As described above, by performing the operation according to the timing chart of FIG. 6, it is possible to perform highly accurate offset correction similarly to the operation according to FIG. 5, and according to FIG. Lower power consumption can be realized than in the case of operating the drive circuit shown in FIG.

The control means 3 always performs an offset correction operation by an external signal when the display device using the drive circuit shown in FIG. 1 is turned on or when the drive circuit is restarted. May be controlled as follows.

FIG. 8 shows the configuration of the drive circuit of the display device according to the second embodiment of the present invention. 8, the same parts as those in FIG. 1 are designated by the same reference numerals. Referring to FIG.
In each of the gradation output circuits 100-1 to 100-n,
Capacitors 123 and 124 are connected to the output terminal 102 via switches 151 and 152, respectively, and the other ends of the capacitors 123 and 124 are respectively connected to the high power supply voltage V.
DD, which is connected to the lower power supply voltage VSS. Other configurations are the same as those in FIG.

Next, the operation of the drive circuit of the display device according to the second embodiment of the present invention will be described with reference to the drawings. FIG. 9 is a timing chart showing the operation of each gradation output circuit of the drive circuit shown in FIG. Note that the switches 111 to 113 and the switches 131 and 1 of each gradation output circuit are
32, 141, 142, 151, 152 are control means 3
It is controlled by the control means 3 according to the external signal, the polarity signal and the offset correction operation signal input to the.

Referring to FIGS. 9 and 8, first, in the positive first output period, the switches 131 and 141 are turned on and the switches 132 and 142 are turned off.
The capacitor 121 is selected. In the first period T01 of the first output period, both the switches 151 and 152 connected to the output terminal 102 are turned off. Also, the first
In the first period T01 of the output period, the switch 11
Since the switches 1 and 112 are turned on and the switch 113 is turned off, the output voltage Vout becomes a voltage including the offset voltage Voff in the input voltage Vin. At this time, the capacitor 12
The potential of one terminal of 1 becomes the input voltage Vin, the potential of the other terminal becomes Vout, and the capacitor 121 corresponds to the offset voltage Voff generated in the operational amplifier 103 according to the positive gradation voltage which is the input voltage. The electric charge is charged.

Next, in the second period T02 of the first output period, the switches 111 and 112 are turned off and the switch 11
3 is turned on. At this time, the capacitor 121 is directly connected between the negative phase input terminal of the operational amplifier 103 and the output terminal 102, and the offset voltage Voff is applied to the capacitor 121.
Is retained. When the switch 113 is turned on, the output terminal 102 is connected to the negative phase input terminal of the operational amplifier 103.
The offset voltage Voff is applied with reference to the electric potential of Voff. As a result, the output voltage Vout is Vout = Vin + V
Since off-Voff = Vin, the offset voltage is canceled and the output voltage equal to the input voltage Vin can be obtained. Further, since the switch 151 is turned on in the second period T02 of the first output period, the capacitor 123 is charged with the corrected output voltage when the polarity is positive.

Next, in the negative second output period, the switches 131 and 141 are turned off and the switches 132 and 142 are turned on.
Is turned on, the capacitor 122 is selected. The switches 111 to 113 have the first period T01 and the second period T of the first output period even in the second output period.
It is controlled similarly to 02. Further, the switches 151 and 152 connected to the output terminal 102 are both turned off in the first period T01 of the second output period. Then, in the second period T02 of the second output period, the switch 151 is turned off and the switch 152 is turned on.

By controlling the switches as described above, even in the second output period, the offset voltage generated in the operational amplifier 103 in accordance with the negative grayscale voltage which is the input voltage is charged in the capacitor 122, and the first voltage is charged. The offset voltage is canceled as in the output period. Also, the capacitor 1
24 is charged with the corrected output voltage when the polarity is negative.

Next, in the positive third output period, the operational amplifier 1 is applied to the capacitor 121 in the first output period.
An electric charge corresponding to the offset voltage generated at 03 is stored and held. Therefore, in the third output period, it is not necessary to perform the offset correction operation (offset voltage storage operation) performed in the period T01 of the first output period, and only the same operation as in the period T02 of the first output period is performed. The output of the operational amplifier 103 can be corrected.

Further, since the capacitor 123 holds the positive output voltage charged in the first output period, the switch 151 is turned on, so that the third voltage
In the initial stage of the output period, charges are supplied from the capacitor 123 to the data line capacitance. Therefore, the voltage change of the data line is accelerated.

Next, in the negative fourth output period, the operational amplifier 1 is applied to the capacitor 122 in the second output period.
An electric charge corresponding to the offset voltage generated at 03 is stored and held. Therefore, in the fourth output period, it is not necessary to perform the offset correction operation performed in the period T01 of the second output period, and only the same operation as in the period T02 of the second output period is performed, so that the output of the operational amplifier 103 is increased. Can be corrected.

Further, since the capacitor 124 holds the negative output voltage charged in the second output period, the switch 152 is turned on, so that the fourth voltage is generated.
In the initial stage of the output period, charges are supplied from the capacitor 124 to the data line capacitance. Therefore, the voltage change of the data line is accelerated.

In the output period (not shown) after the fourth output period, the positive and negative output periods are alternately repeated, so that the operations in the third output period and the fourth output period are alternately performed depending on the polarity. As a result, the output of the operational amplifier 103 can be corrected. In addition, since the charge held in the capacitor 123 or 124 is supplied to the data line capacitance in the initial stage of each output period, the voltage change of the data line becomes faster.

As described above, in the drive circuit shown in FIG.
The switches 151, 1 are connected to the output terminal 102 of each gradation output circuit.
By connecting the capacitors 123 and 124 via 52, once the corrected output voltage is held by the capacitors 123 and 124, electric charge is supplied from the capacitor 123 or 124 to the data line in the subsequent output period. The output voltage changes faster. Therefore, the drive current of the operational amplifier 103 can be reduced to suppress the drive capability, and thus the power consumption can be reduced as compared with the drive circuit shown in FIG.

FIG. 10 is a diagram showing an output voltage waveform of each gradation output circuit of the drive circuit shown in FIG. 8 and an output voltage waveform of each gradation output circuit of the drive circuit shown in FIG. Note that FIG.
The output voltage waveform indicated by 0 is a waveform in the period T02 in which the correction voltage is output. As shown in FIG. 10, in the initial stage of the period T02, the output voltage of each gradation output circuit in FIG. 8 is supplied from the capacitor 123 or 124 to the data line, so that each gradation in FIG. It changes faster than the output voltage of the output circuit.

As described above, according to the second embodiment of the present invention, like the first embodiment of the present invention, the gradation output circuit having the low power consumption and the highly accurate offset correction function is provided. By using, it is possible to realize a drive circuit of a display device which has low power consumption and can output with high precision. Further, by connecting the capacitors 123 and 124 to the output terminal 102 of each gradation output circuit through the switches 151 and 152, once the capacitors 123 and 124 hold the corrected output voltage, the capacitors 123 and 124 hold the corrected output voltage. Since the charges are supplied from 123 or 124 to the data line, the output voltage changes faster than in the first embodiment. Therefore, the driving current of the operational amplifier 103 can be reduced to suppress the driving capability of the operational amplifier 103, and thus the power consumption can be reduced as compared with the first embodiment.

Further, since the gradation output circuit is provided for each gradation, the driving circuit according to the second embodiment of the present invention may be applied to the driving circuit of the liquid crystal display device in which the number of gradations is smaller than the number of outputs. For example, the number of output circuits can be reduced as compared with the configuration shown in FIG. 27 in which an output circuit is provided for each data line.
Therefore, the area of the circuit can be reduced and the cost can be reduced.

FIG. 11 is a diagram showing the configuration of a drive circuit of a display device according to the third embodiment of the present invention, and the same portions as those in FIG. 1 are designated by the same reference numerals. The drive circuit shown in FIG. 11 employs a common DC drive system. Figure 3 (a)
The gradation voltage generating means 1 shown in FIG.
-N and switches 12-1 to 12-n are controlled, and by controlling these switches, the gradation voltages VP1 to VPn of positive polarity or the gradation voltages VN1 to VN of negative polarity are provided.
n is the gradation output circuit 100-1 to 100-n shown in FIG.
Was output to. However, since the grayscale voltage generation means 1 shown in FIG. 11 does not have a switch, the grayscale voltages VP1 to VPn of positive polarity and the grayscale voltages VN1 to V of negative polarity are provided.
Output Nn.

Therefore, in the drive circuit shown in FIG. 11, 2n gradation output circuits 100-1 to 100-2n are provided for the positive and negative gradation voltages, respectively. Further, the gradation output circuits 100-1 to 100-2n
In each of the above, since the grayscale voltage level of the input signal input from the grayscale voltage generation means 1 shown in FIG. 11 is constant, the grayscale output circuit shown in FIG.
One capacitor 121 may be provided as a capacitor for storing the offset voltage generated at 03. Each of the selection circuits 2-1 to 2-m shown in FIG. 11 selects a signal required for driving from the output signals output from the grayscale output circuits 100-1 to 100-2n and outputs the selected data signal to the data line. Output. Note that the switches 111 to 113 of each gradation output circuit are
Are controlled by the control means 3.

Next, the operation of the drive circuit of the display device according to the third embodiment of the present invention will be described with reference to the drawings. FIG. 12 is a timing chart showing the operation of each gradation output circuit of the drive circuit shown in FIG. 12 and 1
1, first, the first period T0 of the first output period
1, the switches 111 and 112 are turned on, the switch 113 is turned off, and the output voltage V of the operational amplifier 103 is increased.
out becomes Vin + Voff in which the offset voltage Voff is included in the input voltage Vin. At this time, the potential of one terminal of the capacitor 121 becomes the input voltage Vin and the potential of the other terminal becomes Vout, so that the capacitor 121 receives the input voltage Vi.
Offset voltage V generated in the operational amplifier 103 according to n
A charge equivalent to off is charged.

In the second period T02 of the first output period, the switches 111 and 112 are turned off and the switch 113 is turned on. At this time, the capacitor 121 is the operational amplifier 1
The offset voltage Voff is held in the capacitor 121 by being directly connected between the negative phase input terminal 03 and the output terminal 102. When the switch 113 is turned on, the offset voltage Voff is applied to the negative phase input terminal of the operational amplifier 103 with the potential of the output terminal 102 as a reference. As a result, the output voltage Vout is Vout = Vin + Voff-Vof
Since f = Vin, the offset voltage is canceled out, and an output voltage equal to the input voltage Vin can be obtained.

In each grayscale output circuit, the grayscale voltage input in the first output period is the same as the grayscale voltage input in each of the second to Mth output periods, and the second to Mth grayscale voltages are the same. In each of the output periods, the electric charge corresponding to the offset voltage stored in the first output period is held in the capacitor 121. Therefore, in each of the second to Mth output periods, the output of the operational amplifier 103 can be corrected by performing the operation in the period T02 without performing the operation in the period T01.

In the third embodiment of the present invention, since the grayscale voltage input to each grayscale output circuit is constant, once the offset voltage is stored and held in the capacitor, the capacitor is stored in the output period thereafter. Need not be charged and discharged, and only the charges that have fluctuated due to the effect of capacitive coupling generated during switching need to be replenished. Therefore, the capacitor consumes almost no power due to charge / discharge.
Further, once the offset voltage is stored in the capacitor, power consumption due to charging / discharging is almost zero. Therefore, even if the capacitance of the capacitor is increased to suppress the influence of capacitive coupling that occurs during switching, the power consumption is not increased and the output accuracy is improved. Can be increased.

FIG. 13 shows an active matrix type organic EL.
It is a figure which shows the simplest pixel structure of a display device. FIG.
The drive circuit having the same configuration as the drive circuit shown in FIG. 11 can be applied to the active matrix type organic EL display device having the pixel configuration shown in FIG. In FIG. 13, by applying and holding a gradation voltage from the data line to the gate of the transistor 12 via the transistor 11, the current modulated by the gradation voltage is applied to the transistor 1
Organic light emitting diode OLED which constitutes a pixel via 2
To emit light with a light amount corresponding to the gradation voltage (current modulation method). As a drive circuit which supplies a grayscale voltage to the gate of the transistor 12 of each pixel, a drive circuit having the same configuration as the drive circuit shown in FIG. 11 can be applied.

The organic EL display does not require polarity reversal as in the liquid crystal display device. As a result, in each grayscale output circuit, the grayscale voltage level of the input signal input from the grayscale voltage generation means becomes constant as in the third embodiment of the present invention. Therefore, each gradation output circuit may be provided with one capacitor for storing the offset voltage generated in the operational amplifier, similarly to the third embodiment of the present invention.

The basic structure of the active matrix type organic EL display is SID98DIGEST No. 1
Pp. 1-14, R.S. M. A. Dawson et al., “4.2
Design of an Improved Pixel for a Polysilicon Acti
ve-Matrix Organic LED Display ”, and detailed description thereof is omitted.

As described above, according to the third embodiment of the present invention, by using the gradation output circuit having low power consumption and highly accurate offset correction function, low power consumption and high accuracy are achieved. A drive circuit of a display device capable of outputting can be realized. Further, in the third embodiment of the present invention, since the gradation output circuit is provided for each gradation, the third embodiment of the present invention is applied to the drive circuit of the liquid crystal display device in which the number of gradations is smaller than the number of outputs. When the drive circuit according to the embodiment is applied, the number of output circuits can be reduced as compared with the structure illustrated in FIG. 27 in which an output circuit is provided for each data line. Therefore, the area of the circuit can be reduced and the cost can be reduced.

In order to describe the above-described embodiments of the present invention in more detail, a drive circuit of a display device in which each gradation output circuit is configured by using a typical operational amplifier will be described with reference to the drawings.

FIG. 14 is a diagram showing the configuration of the operational amplifier 103 of each gradation output circuit of the drive circuit shown in FIG. Figure 1
In the operational amplifier 103 constituting each gradation output circuit of No. 4, the sources are commonly connected, the gates are respectively connected to the positive phase input terminal and the negative phase input terminal, and the PMOS transistors 301 and 302 forming a differential pair and the transistor 301 And 3
02, a constant current source 311 connected between a commonly connected source and a high-side power supply VDD, and a source having a low-side power supply V
It is connected to SS and the gate is NMOS transistor 304
An NMOS transistor 303 connected to the gate of and a drain connected to the drain of the transistor 301;
An NMOS transistor 304 whose source is connected to the low potential power supply VSS, whose drain and gate are connected to the drain of the transistor 302, and high potential power supply VDD
Constant current source 3 connected between the output terminal and the output terminal of the operational amplifier
12, the output of the differential pair is input to the gate, the source is connected to the lower power supply VSS, the drain is connected to the connection point between the output terminal and the constant current source 312, and the output terminal The phase compensation capacitor 321 is connected between the gate terminal of the transistor 305 and the gate terminal.

The operational amplifier 103 itself having the structure shown in FIG. 14 may generate an offset voltage due to the characteristic variation of the active elements constituting the operational amplifier 103, and cannot output an output voltage equal to the input voltage.

However, in the amplifier circuit shown in FIG. 14, the control means 3 controls the switch 13 of each gradation output circuit according to the polarity.
1, 132, 141, 142 and switches 111-11
By controlling 3, the offset voltage according to the input voltage level is stored and held in the capacitor corresponding to the input voltage in a one-to-one correspondence, and the offset voltage is corrected. Therefore, high-accuracy output is possible, and since there is almost no power consumption due to the offset correction operation, the power consumption due to the offset correction operation can be minimized.

Further, once the offset voltage is stored in the capacitor, there is almost no power consumption due to charging / discharging. Therefore, even if the capacitance of the capacitor is increased, the power consumption is not increased in order to suppress the influence of capacitive coupling that occurs during switching. The output accuracy can be improved.

FIG. 15 is a diagram showing another example of the configuration of the operational amplifier 103 of each gradation output circuit of the drive circuit shown in FIG. Operational amplifier 10 constituting each gradation output circuit of FIG.
3, a differential pair composed of NMOS transistors 201 and 202 and a differential pair composed of PMOS transistors 205 and 206 are provided as NMOS transistors 201 and 20.
2 active load PMOS transistors 203 and 2
04 and the PMOS transistors 209 and 210 having a common gate electrode, respectively, are connected in parallel to form an input stage that enables a wide input range. Further, from the potential dropped from the high potential side power supply VDD by the voltage between the drain and the source of the PMOS transistor 213, the low potential side power supply VSS changes to the NMOS transistor 21.
4 has an output range up to the potential increased by the voltage between the drain and the source, and is an output stage that enables a wide output range.

Here, the offset voltage occurs when the symmetry of the transistors forming the differential pair is broken due to variations in the threshold voltage of the transistors or in the gate width / gate length (W / L). In the operational amplifier 103 forming each gradation output circuit of FIG. 15, the element variation of the differential pair formed by the NMOS transistors 201 and 202 is caused by the PMOS transistors 203 and 204 and the PMOS transistor 20 forming a current mirror circuit.
It is fed back to the differential pair composed of the PMOS transistors 205 and 206 via 9 and 210, so that it occurs due to element variation of the two differential pairs within the input voltage range in which the two differential pairs operate together. The offset voltage is averaged. Therefore, within the input voltage range in which the two differential pairs operate together, the action of correcting the offset voltage caused by the variation in the element characteristics of the respective differential pairs works, so that the output voltage accuracy is high and the offset voltage is small. There are features.

In recent years, the demand for portable devices such as portable telephones is increasing, and low power consumption is an important performance required for portable devices. Operational amplifier 103 of FIG.
When the is used in a portable device, the power consumption of the operational amplifier can be reduced by lowering the power supply voltage of the operational amplifier. However, in the operational amplifier 103 of FIG.
The differential pair consisting of the MOS transistors 201 and 202 does not operate when the input voltage is lower than the threshold voltage of the transistor 201, and the PMOS transistor 205
The differential pair composed of 206 and 206 has a high-side power source V
It does not operate when the potential is equal to or higher than the potential which is lower than the threshold voltage of the transistor 205 by DD.

Since the off-leakage current increases when the threshold voltage of the transistor is lowered, the threshold voltage cannot be lowered even if the power supply voltage is lowered. Therefore, when operating the operational amplifier of FIG. 15 under the condition that the power supply voltage is sufficiently low, N
The input voltage range in which the differential pair including the MOS transistors 201 and 202 and the differential pair including the PMOS transistors 205 and 206 operate together is narrower than the power supply voltage range, and only one of the two differential pairs is provided. Wide input voltage range that does not work. When only one of the two differential pairs operates, an offset voltage is generated due to the characteristic variation of the active elements included in the differential pair. That is, even with the above-described operational amplifier capable of high-accuracy output, high-accuracy output becomes difficult under the condition that the power supply voltage is sufficiently low.

On the other hand, in the drive circuit shown in FIG. 15, the control means 3 controls the switch 13 of each gradation output circuit according to the polarity.
1, 132, 141, 142 and switches 111-11
By controlling 3, the offset voltage corresponding to the input voltage level is stored and held in the capacitor that is associated with the input voltage in a one-to-one correspondence, and the offset voltage is corrected.
Therefore, even when the power supply voltage is sufficiently low, the output of the operational amplifier 103 can be corrected with high accuracy, and therefore each gradation output circuit shown in FIG. 15 can output with high accuracy.

Further, there is almost no power consumption due to charge / discharge of charges by the offset correction operation, and the power consumption by the offset correction operation can be minimized. Therefore, the gradation output circuits 100-1 to 100-10 shown in FIG.
In each of 0-n, high precision output, low power consumption, and wide input / output range can be realized.

Further, once the offset voltage is stored in the capacitor, power consumption due to charging / discharging hardly occurs. Therefore, even if the capacitance of the capacitor is increased in order to suppress the influence of capacitive coupling that occurs at the time of switching, the power consumption is not increased. The output accuracy can be improved.

Furthermore, since an output circuit is provided for each gradation,
When the drive circuit shown in FIG. 15 is applied to the drive circuit of the liquid crystal display device in which the number of gradations is smaller than the number of outputs, the number of output circuits is reduced as compared with the configuration shown in FIG. 27 in which an output circuit is provided for each data line. Therefore, the area of the circuit can be reduced and the cost can be reduced.

The operational amplifier 103 having the configuration shown in FIGS. 14 and 15 is not limited to the grayscale output circuits of the drive circuit shown in FIG. 1 but also the grayscale output circuits of the drive circuit shown in FIGS. 8 and 11. Of course, it can be applied to the operational amplifier of FIG. Further, the operational amplifier of each gradation output circuit of the drive circuit shown in FIGS. 1, 8 and 11 is not limited to the operational amplifier 103 having the configuration shown in FIGS. 14 and 15, and other operational amplifiers may be used. Of course, you can do that.

FIG. 16 is a diagram showing the structure of the drive circuit of the display device according to the fourth embodiment of the present invention. In FIG. 16, each of the grayscale output circuits 100-1 to 100-n includes a circuit input terminal 101, a circuit output terminal 102, and an operational amplifier 70 having one positive phase input terminal and two negative phase input terminals. , Offset correction circuit 71. The positive or negative gradation voltage output from the gradation voltage generating means 1 is input to the input terminal 101.
The voltage follower operational amplifier 70 outputs a voltage equal to the positive or negative gradation voltage output from the gradation voltage generating means 1 to the output terminal 102.

The offset correction circuit 71 includes a switch 16
1, 162, 112 and 113 and two capacitors 1
21 and 122, and a capacitor selecting means including switches 131 and 132. Switch 1
Reference numerals 61 and 162 are connected between the two negative-phase input terminals of the operational amplifier 70 and the output terminal 102, respectively, and switches 112 and 113 are connected in series between the input terminal 101 and the output terminal 102. Further, one ends of the two capacitors 121 and 122 are commonly connected to a connection point between the switch 112 and the switch 113 via the switches 131 and 132, respectively.
The other ends of the two are respectively connected to the two negative-phase input terminals of the operational amplifier 70.

The operational amplifier 103 shown in FIG. 14 will be described below.
The drive circuit of the display device shown in FIG. 16 will be described with reference to the drawings by taking as an example the case where each gradation output circuit shown in FIG.

FIG. 17 is a diagram showing the configuration of the drive circuit of the display device when the operational amplifier having the configuration shown in FIG. 14 is applied to the operational amplifier 70 of each gradation output circuit shown in FIG. In the operational amplifier 70 having the configuration shown in FIG. 17, two PMOs are provided for the PMOS transistor (positive phase input transistor) 301 whose gate electrode corresponds to the positive phase input terminal.
S transistors (negative-phase input transistors) 332 and 3
33 are provided in parallel. Positive phase input transistor 3
The gate electrodes of the two anti-phase input transistors 332 and 333 provided in parallel with 01 correspond to the two anti-phase input terminals, respectively, and are directly connected to the capacitors 121 and 122. The drain electrodes of the two negative-phase input transistors 332 and 333 are commonly connected, and the source electrodes thereof are commonly connected via the switches 81 and 82.

Next, the operation of the drive circuit of the display device shown in FIG. 17 will be described. FIG. 18 is a timing chart showing an operation example of each gradation output circuit of the drive circuit shown in FIG. In FIG. 18, in the case where the positive and negative gradation voltages are periodically and alternately output from each of the n output terminals of the gradation voltage generating unit 1 of FIG. 17, the positive gradation voltage is The states of the switches of the respective gradation output circuits in the two output periods of the first output period for outputting and the second output period for outputting the negative gradation voltage are shown. In addition,
Switches 161, of each gradation output circuit and operational amplifier 70
162, 112, 113, 131, 132, 81 and 8
2 is controlled by the control means 3.

Referring to FIGS. 18 and 17, first, in the first output period which is the positive output period, the switch 13
The capacitor 121 is selected by controlling 1 to be on and the switch 132 to be off. Further, by controlling the switch 81 to be on and the switch 82 to be off, the transistors 301 and 332 operate as a differential pair in the input stage of the operational amplifier 70. Further, the switch 162 is controlled to be off in the first output period which is the positive output period.

In the first period T01 of the first output period, the switches 161 and 112 are turned on and the switch 11
When 3 is turned off, the output voltage Vout of the operational amplifier 70 is Vin which is the input voltage Vin including the offset voltage Voff.
It becomes + Voff. At this time, the potential of one end of the capacitor 121 becomes the input voltage Vin and the other end becomes Vout, so that the capacitor 121 corresponds to the offset voltage Voff generated in the operational amplifier 70 according to the positive gradation voltage which is the input voltage. The electric charge is charged.

In the second period T02 of the first output period, the switches 161 and 112 are turned off and the switch 113 is turned on. When the switches 161 and 112 are turned off, the offset voltage Vof is applied to the capacitor 121.
f is retained. By turning on the switch 113, one of the two negative-phase input terminals of the operational amplifier 70, which is directly connected to the capacitor 121, is connected to the output terminal 1 of the negative-phase input terminal.
The offset voltage Voff is applied with reference to the potential of 02. As a result, the gradation output circuits 100-1 to 100-n
In each of the above, the output voltage Vout is Vout = Vin +
Since Voff-Voff = Vin, the offset voltage is canceled and an output voltage equal to the input voltage Vin can be obtained.

Next, in the second output period, which is a negative output period, the switch 132 is turned on and the switch 131 is turned off, so that the capacitor 122 is selected.
Further, by controlling the switch 81 to be off and the switch 82 to be on, the transistors 301 and 333 operate as a differential pair in the input stage of the operational amplifier 70. Also,
In the second output period, which is a negative output period, the switch 1
61 is controlled off.

In the first period T01 of the second output period, the switches 162 and 112 are on, the switch 113 is off,
In the second period T02 of the second output period, the switch 16
2, 112 are turned off and the switch 113 is turned on. Even in the second output period, the gradation output circuits 100-1 to 100-1
In each of 100-n, the offset voltage generated in the operational amplifier 70 according to the negative gray scale voltage which is the input voltage is charged in the capacitor 122, and the offset voltage is canceled as in the first output period, and the input voltage Vin is input. An output voltage equal to can be obtained.

Even in each output period (not shown) after the lapse of the second output period, the offset voltage is corrected by controlling each switch according to the polarity as described above, and the output voltage equal to the input voltage can be obtained. Gradation output circuit 1
The selection circuits 2-1 to 2-m select voltages necessary for driving from the gradation voltages current-amplified by 00-1 to 100-n, and output to the data lines.

Incidentally, in the timing chart of FIG.
Although there is no delay in each switch and the switch control by the control means 3 is performed at the same time, when each switch has a delay, the switch 161 is turned off before the switch 113 is turned off in the first period T01. , 112 are not turned on, and the second period T02
In order to prevent the switch 113 from being turned on before the switches 162 and 112 are turned off, the switch control is performed in consideration of the delay.

As described above, the drive circuit shown in FIG. 17 is provided with the two capacitors respectively associated with the positive and negative gradation voltages which are the input voltages input to the gradation output circuits. Therefore, the offset voltages generated in the operational amplifier 70 when two grayscale voltages of positive polarity and negative polarity are respectively input can be stored and held in the capacitors 121 and 122, respectively. Once the offset voltage is stored and held in each of these two capacitors, there is no need to charge and discharge the capacitors during the output period when the grayscale voltage of the same polarity is input next time, and it is possible to avoid the capacitance coupling that occurs during switching. All that is needed is to replenish the changed charge. Therefore, the capacitor consumes almost no power due to charge / discharge.

Further, once the offset voltage is stored in each capacitor, power consumption due to charging / discharging hardly occurs. Therefore, the power consumption increases even if the capacitance of each capacitor is increased in order to suppress the influence of capacitive coupling that occurs during switching. The output accuracy can be improved without doing so.

FIG. 19 is a timing chart showing another operation example of each gradation output circuit of the drive circuit shown in FIG. In FIG. 18, the offset correction operation (offset voltage storage operation) is always performed in each output period.
Then, the predetermined M output periods (M is a positive even number of 4 or more)
The difference is that the offset correction operation is performed only in the first and second output periods. In addition, the switches 161, 162, 112 of each gradation output circuit and the operational amplifier 70,
113, 131, 132, 81 and 82 are controlled by the control means 3. Further, the predetermined M output periods need to be set to a period in which the output accuracy of the gradation output circuit does not decrease due to a leak.

Referring to FIG. 19, in the first first and second output periods, the same control as the switch control in the first and second output periods of FIG. 18 is performed. Therefore, in the first output period, the offset voltage generated in the operational amplifier 70 according to the positive gradation voltage input to each gradation output circuit is charged and held in the capacitor 121, and the offset voltage stored in the capacitor 121 is stored in the capacitor 121. By correcting the output of the operational amplifier 70 by using it, an output voltage equal to the input voltage can be obtained in each gradation output circuit.

Similarly, in the second output period, the operational amplifier 7 is responsive to the negative gradation voltage input to each gradation output circuit.
The offset voltage generated at 0 charges the capacitor 122,
By correcting the output of the operational amplifier 70 using the offset voltage held and stored in the capacitor 122, an output voltage equal to the input voltage can be obtained in each gradation output circuit.

Next, of the third to Mth output periods, in the output period (positive output period) in which the positive grayscale voltage is input to each grayscale output circuit, the positive polarity in the first output period. Since the electric charge corresponding to the offset voltage generated in the operational amplifier 70 according to the gradation voltage is stored and held in the capacitor 121, the output of the operational amplifier 70 can be corrected without performing the offset correction operation performed in the period T01. it can. Note that the switches 81 and 131 are turned on and the switch 8 is turned on in the positive output period of the third to Mth output periods.
2 and 132 are turned off.

Similarly, in the output period (negative output period) in which the negative grayscale voltage is input to each grayscale output circuit in the third to Mth output periods, the negative polarity is output in the second output period. Since the charge corresponding to the offset voltage generated in the operational amplifier 70 according to the gradation voltage is stored and held in the capacitor 122, the output of the operational amplifier 70 can be corrected without performing the offset correction operation performed in the period T01. it can. Note that the switches 81 and 131 are turned off and the switch 8 is turned off in the negative output period of the third to Mth output periods.
2 and 132 are turned on.

By operating the drive circuit shown in FIG. 17 by the control means 3 according to the operation example of FIG.
The offset correction operation is performed only in the first and second output periods in the first to Mth output periods, and the correction voltage can be output without performing the offset correction operation in the subsequent third to Mth output periods. Therefore, the power consumption in the first to Mth output periods can be suppressed as compared with the operation according to the timing chart of FIG.

As described above, by performing the operation according to the timing chart of FIG. 19, it is possible to perform the highly accurate offset correction as in the operation according to FIG. 18, and according to FIG. Lower power consumption can be realized than in the case of operating the drive circuit shown in FIG. The control means 3 controls by an external signal to always perform the offset correction operation when the display device using the drive circuit shown in FIG. 17 is powered on or when the drive circuit restarts. You may.

As described above, also in the drive circuit shown in FIG. 17, the same effect as that of the drive circuit shown in FIG. 1 can be obtained. That is, in the drive circuit shown in FIG. 16, it is possible to obtain the same effect as that of the drive circuit shown in FIG.

Next, the difference in performance between the drive circuit shown in FIG. 16 and the drive circuit shown in FIG. 1 will be described.

In the drive circuit shown in FIG. 1, when the polarity is inverted, the capacitor corresponding to the input voltage level after the inversion is replaced by the capacitor corresponding to the input voltage level before the inversion through switch 141 or 142. Operational amplifier 1
03 reverse-phase input terminal. Although there is a parasitic capacitance such as a gate capacitance at the negative phase input terminal, this parasitic capacitance is charged with a voltage according to the input voltage level before polarity inversion. In the third to Mth output periods in the operation example shown in FIG. 6, the output of the operational amplifier is corrected by using the offset voltage held in the capacitor in the first output period and the second output period without performing the offset correction operation. It is carried out.
In this case, the reverse phase input terminal is the switch 141 after the polarity is reversed.
Alternatively, when connected to a different capacitor via 142, the parasitic capacitance of the negative-phase input terminal is charged with a voltage according to the input voltage level before polarity reversal, so the charge held in the capacitor fluctuates, The accuracy of the corrected output voltage may decrease.

On the other hand, in the drive circuit shown in FIG. 16, since the operational amplifier 70 is provided with two negative-phase input terminals directly connected to the capacitors 121 and 122, respectively, the drive circuit shown in FIG. There is no change in the charge held in the capacitor, and the correction voltage output with higher accuracy than that of the drive circuit shown in FIG. 1 is possible.

The configuration of operational amplifier 70 shown in FIG. 16 is not limited to the configuration shown in FIG. Below, the case where each gradation output circuit shown in FIG. 16 is configured by using the operational amplifier 103 shown in FIG. 15 is taken as an example, and another configuration example of the operational amplifier 70 shown in FIG. And explain.

FIG. 20 is a diagram showing the configuration of the drive circuit of the display device when the operational amplifier having the configuration shown in FIG. 15 is applied to the operational amplifier 70 of each gradation output circuit shown in FIG. In the operational amplifier 70 having the configuration shown in FIG. 20, two NMOs are provided for the NMOS transistor (positive phase input transistor) 201 whose gate electrode corresponds to the positive phase input terminal.
S transistors (reverse phase input transistors) 232 and 2
33 are provided in parallel, and two PMOS transistors (negative-phase input transistors) 236 and 237 are provided in parallel with respect to the PMOS transistor (positive-phase input transistor) 205 whose gate electrode corresponds to the positive-phase input terminal. ing.

Two negative-phase input transistors 232 and 2 are provided in parallel with the positive-phase input transistor 201.
The gate electrodes of 33 correspond to two opposite-phase input terminals, respectively, and are directly connected to the capacitors 121 and 122. In addition, the two negative-phase input transistors 232 and 23
The drain electrodes of 3 are commonly connected, and the source electrodes thereof are commonly connected via switches 171 and 172. Similarly, the gate electrodes of the two negative-phase input transistors 236 and 237 provided in parallel with the positive-phase input transistor 205 respectively correspond to the two negative-phase input terminals and are directly connected to the capacitors 121 and 122. . Also,
The drain electrodes of the two negative-phase input transistors 236 and 237 are commonly connected, and the source electrodes thereof are commonly connected via the switches 181 and 182.

Next, the operation of the drive circuit of the display device shown in FIG. 20 will be described. FIG. 21 is a timing chart showing an operation example of each gradation output circuit of the drive circuit shown in FIG. In FIG. 21, when the grayscale voltage of the positive polarity and the negative polarity are alternately output from each of the n output terminals of the grayscale voltage generation unit 1 of FIG. The states of the switches of the respective gradation output circuits in the two output periods of the first output period for outputting and the second output period for outputting the negative gradation voltage are shown. In addition,
Switches 161, of each gradation output circuit and operational amplifier 70
162, 112, 113, 131, 132, 171, 1
72, 181, and 182 are controlled by the control means 3.

Referring to FIG. 21, in the first output period, which is the positive output period, the switches 171 and 181 are turned on and the switches 172 and 182 are turned off, so that the transistors 201 and 232 are turned on.
0 operates as one differential pair of the input stages, and transistors 205 and 236 operate as the other differential pair of the operational amplifier 70 input stages. Further, in the first output period, the switches 161, 162, 112, 113, 131 and 1
32 is controlled in the same manner as in the operation example shown in FIG. Therefore, in the first period T01 of the first output period, the capacitor 121 is charged with the electric charge corresponding to the offset voltage generated in the operational amplifier 70 according to the positive gradation voltage which is the input voltage, and the first output period In the second period T02, the offset voltage is canceled and the output voltage equal to the input voltage can be obtained.

In the second output period, which is the negative output period, the switches 171 and 181 are off, and the switch 172.
And 182 are turned on, the transistors 201 and 233 operate as one differential pair of the input stage of the operational amplifier 70, and the transistors 205 and 237 serve as the other differential pair of the input stage of the operational amplifier 70. Operate. Further, in the second output period, the switches 161, 1
62, 112, 113, 131 and 132 are controlled in the same manner as the operation example shown in FIG. Therefore, in the first period T01 of the second output period, the capacitor 122 is charged with the electric charge corresponding to the offset voltage generated in the operational amplifier 70 in accordance with the negative gradation voltage which is the input voltage, and the second output period. In the second period T02, the offset voltage is canceled and the output voltage equal to the input voltage can be obtained.

Even in each output period (not shown) after the lapse of the second output period, the offset voltage is corrected by controlling each switch according to the polarity as described above, and the output voltage equal to the input voltage can be obtained. Gradation output circuit 1
The selection circuits 2-1 to 2-m select voltages necessary for driving from the gradation voltages current-amplified by 00-1 to 100-n, and output to the data lines.

In the timing chart of FIG. 21,
Although there is no delay in each switch and the switch control by the control means 3 is performed at the same time, when each switch has a delay, the switch 161 is turned off before the switch 113 is turned off in the first period T01. , 112 are not turned on, and the second period T02
In order to prevent the switch 113 from being turned on before the switches 162 and 112 are turned off, the switch control is performed in consideration of the delay.

By operating the drive circuit shown in FIG. 20 as described above, the drive circuit shown in FIG. 20 is similar to the case where the drive circuit shown in FIG. 17 is operated according to the operation example of FIG. It is clear that the effect of is obtained.

FIG. 22 is a timing chart showing another operation example of each gradation output circuit of the drive circuit shown in FIG. In FIG. 21, the offset correction operation (offset voltage storage operation) is always performed in each output period.
Then, the predetermined M output periods (M is a positive even number of 4 or more)
The difference is that the offset correction operation is performed only in the first and second output periods. In addition, the switches 161, 162, 112 of each gradation output circuit and the operational amplifier 70,
113, 131, 132, 171, 172, 181 and 182 are controlled by the control means 3. Also, a predetermined M
It is necessary to set the individual output period to a period in which the output accuracy of the gradation output circuit does not decrease due to leakage.

Referring to FIG. 22, in the first first and second output periods, the same control as the switch control in the first and second output periods of FIG. 21 is performed. Therefore, in the first and second output periods, an output voltage equal to the input voltage can be obtained in each gradation output circuit as described above with reference to FIG.

In the output period (positive output period) in which the positive grayscale voltage is input to each grayscale output circuit among the third to Mth output periods, the positive grayscale voltage is output in the first output period. Accordingly, the electric charge corresponding to the offset voltage generated in the operational amplifier 70 is stored and held in the capacitor 121, so that the output of the operational amplifier 70 can be corrected without performing the offset correction operation performed in the period T01. In the positive output period of the third to Mth output periods,
The switches 131, 171, and 181 are turned on, and the switches 132, 172, and 182 are turned off.

Similarly, in the output period (negative output period) in which the negative grayscale voltage is input to each grayscale output circuit among the third to Mth output periods, the negative polarity is output in the second output period. Since the charge corresponding to the offset voltage generated in the operational amplifier 70 according to the gradation voltage is stored and held in the capacitor 122, the output of the operational amplifier 70 can be corrected without performing the offset correction operation performed in the period T01. it can. In the negative output period of the third to Mth output periods, the switches 131, 171 and 181 are turned off,
The switches 132, 172 and 182 are turned on.

The control means 3 uses an external signal to turn on the power of the display device using the drive circuit shown in FIG.
Alternatively, control may be performed so that the offset correction operation is always performed when the drive circuit restarts from the stopped state.

By operating the drive circuit shown in FIG. 20 as described above, the drive circuit shown in FIG. 20 is similar to the case of operating the drive circuit shown in FIG. 17 according to the operation example of FIG. It is clear that the effect of is obtained.

The structure of the operational amplifier 70 shown in FIG. 16 is not limited to the structure shown in FIGS. 17 and 20, that is, the operational amplifier applicable to the operational amplifier 70 shown in FIG. It is not limited to the operational amplifier having the configuration shown in FIG. 14 or FIG. 15, and any form of operational amplifier can be provided in FIG. 16 by providing two negative-phase input terminals as shown in FIG. 17 and FIG. Operational amplifier 7 shown
It can be used as 0.

By the way, in the drive circuits shown in FIGS. 1, 8, 11 and 16, during the period T01 in which the offset correction operation (offset voltage storage operation) is performed, both the data line load and the capacitor are driven to stabilize the output voltage. Must be set for a sufficient period of time. Therefore, a switch is provided at the output terminal 102 of each gradation output circuit, and the switch is turned off in the period T01 for performing the offset correction operation to disconnect each gradation output circuit from the load, and the period T for performing the correction voltage output.
The switch 02 is turned on to connect each gradation output circuit to the load. As a result, the data line load does not have to be driven in the period T01, and the offset voltage is simply stored in the capacitor, so that the period T01 can be shortened.

Next, a liquid crystal display device using the drive circuit of the display device according to each of the above embodiments of the present invention will be described with reference to the drawings.

FIG. 23 is a diagram showing the structure of a source driver of a liquid crystal display device using the drive circuit of the display device according to each of the above embodiments of the present invention. In the source driver shown in FIG. 23, digital signals corresponding to gradations are input, and digital signals for all outputs are sequentially stored in the register 32 in synchronization with the clock. Then, all the data is latched by the latch 33, and the digital signal is converted into an analog signal corresponding to the voltage-transmittance characteristic of the liquid crystal through the drive circuit 34 which is the drive circuit according to each of the embodiments of the present invention, and the data line is converted. Output to. By incorporating the drive circuit of the display device according to each of the embodiments of the present invention into the source driver of the liquid crystal display device, it is possible to realize a source driver with low power consumption and high precision output.

FIG. 24 is a diagram showing the structure of an active matrix drive type liquid crystal display device incorporating a source driver using the drive circuit of the display device according to each of the above embodiments of the present invention. In the active matrix drive type liquid crystal display device shown in FIG. 24, a controller 35 receives a video signal, a clock, vertical and horizontal synchronization signals, and outputs a grayscale voltage signal, and outputs a scanning signal. Control the gate driver 37. By using the source driver of FIG. 23 as the source driver 36 of the liquid crystal display device, a liquid crystal display device having low power consumption and high display quality can be realized.

Next, a portable electronic device using the drive circuit of the display device according to each of the above embodiments of the present invention will be described.

As an application of the active matrix type display device using the drive circuit of the display device according to each of the above-mentioned embodiments of the present invention, there are portable electronic equipment, in particular, a portable information terminal represented by a portable telephone. Hereinafter, a mobile phone will be described with reference to the drawings as an example of a mobile information terminal incorporating an active matrix type display device using the drive circuit of the display device according to each of the embodiments of the present invention.

FIG. 25 is a diagram showing a mobile phone incorporating an active matrix type display device using the drive circuit of the display device according to each of the above embodiments of the present invention. In FIG. 25, this mobile phone includes a housing 601 and an antenna 6
02, a voice input unit 603, a voice output unit 604, a keypad 605, and a display unit 606. In the present invention, the display device shown in FIG. 24 can be used for the display panel using the active matrix display device. The display device of FIG. 24 is a display unit 606 of a mobile phone.
When used for a mobile phone, a mobile phone having low power consumption and high display quality can be realized.

[0156]

The effect of the present invention is that low power consumption, high precision output and low cost can be realized. The reason is that the storage means of each gradation output circuit stores in advance each of the offset voltages generated in the operational amplifier in accordance with the gradation voltage level of the input signal from the gradation voltage generation means. As a result, each time the grayscale voltage level of the input signal changes, the offset voltage that has already been stored is erased and a new offset voltage is stored, thus reducing power consumption. be able to.

Further, in each gradation output circuit, a plurality of capacitors are used as storage means, and one capacitor selected in accordance with the gradation voltage level of the input signal stores and holds the offset voltage. The offset voltage is used to correct the output of the operational amplifier. Therefore, the output of the operational amplifier can be corrected with high precision, and high-precision output is possible. Further, once the offset voltage is stored and held, when the next input signal having the same gradation voltage level is supplied to the gradation output circuit, the same capacitor is selected and the offset voltage held in this capacitor is held. Since the output of the operational amplifier is corrected using
There is almost no power consumption due to charge / discharge of the capacitor, and it is possible to minimize power consumption.

Further, since the gradation output circuit is provided for each of the plurality of output terminals of the gradation voltage generating means, that is, since the gradation output circuit is provided for each gradation, the number of gradations is When the number of outputs is smaller than that of the drive circuit, the number of output circuits can be reduced as compared with the configuration in which the output circuit is provided for each data line. Therefore, the area of the circuit can be reduced and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a drive circuit of a display device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a waveform of a common voltage of one pixel and a waveform of a signal voltage having a maximum amplitude among signal voltages applied to a liquid crystal, and FIG. 2 (a) is a diagram showing each waveform by a common DC driving method. 2B is a diagram showing each waveform according to the common inversion drive method.

3 is a diagram showing a configuration example of a grayscale voltage generation means 1 of the drive circuit of FIG. 1, and FIG. 3A is a configuration example of the grayscale voltage generation means 1 in the case of using a common DC drive system. FIG. 3B is a diagram showing a configuration example of the grayscale voltage generating means 1 when the common inversion driving method is used.

FIG. 4 is a diagram for explaining the operation of the control means 3 in FIG.

5 is a timing chart showing an operation example of each gradation output circuit of the drive circuit of FIG.

6 is a timing chart showing another operation example of each gradation output circuit of the drive circuit of FIG.

7 is a diagram showing the control contents of a control means 3 when operating each gradation output circuit of FIG. 1 according to the timing chart of FIG.

FIG. 8 is a diagram showing a configuration of a drive circuit of a display device according to a second embodiment of the present invention.

9 is a timing chart showing the operation of each gradation output circuit of the drive circuit of FIG.

10 is a diagram showing an output voltage waveform of each gradation output circuit of the drive circuit of FIG. 8 and an output voltage waveform of each gradation output circuit of the drive circuit of FIG.

FIG. 11 is a diagram showing a configuration of a drive circuit of a display device according to a third embodiment of the present invention.

12 is a timing chart showing the operation of each gradation output circuit of the drive circuit of FIG.

FIG. 13 is a diagram showing the simplest pixel configuration of an active matrix organic EL display device.

14 is a diagram showing a configuration of an operational amplifier 103 of each gradation output circuit of the drive circuit of FIG.

15 is a diagram showing another configuration of the operational amplifier 103 of each gradation output circuit of the drive circuit of FIG.

FIG. 16 is a diagram showing a configuration of a drive circuit of a display device according to a fourth embodiment of the present invention.

17 is a diagram showing a configuration of a drive circuit of a display device when the operational amplifier having the configuration shown in FIG. 14 is applied to the operational amplifier 70 of each gradation output circuit of FIG.

18 is a timing chart showing an operation example of each gradation output circuit of the drive circuit of FIG.

19 is a timing chart showing another operation example of each gradation output circuit of the drive circuit of FIG.

20 is a diagram showing a configuration of a drive circuit of a display device when the operational amplifier having the configuration shown in FIG. 15 is applied to the operational amplifier 70 of each gradation output circuit of FIG.

FIG. 21 is a timing chart showing an operation example of each gradation output circuit of the drive circuit of FIG. 20.

22 is a timing chart showing another operation example of each gradation output circuit of the drive circuit of FIG. 20.

FIG. 23 is a diagram showing a configuration of a source driver of a liquid crystal display device using the drive circuit of the display device according to each of the embodiments of the present invention.

FIG. 24 is a diagram showing the configuration of an active matrix drive type liquid crystal display device incorporating a source driver using the drive circuit of the display device according to each of the embodiments of the present invention.

FIG. 25 is a diagram showing a mobile phone incorporating an active matrix type display device using the drive circuit of the display device according to each of the embodiments of the present invention.

FIG. 26 is a diagram showing a configuration of a conventional first data line drive circuit.

FIG. 27 is a diagram showing a configuration of a conventional second data line drive circuit.

FIG. 28 is a diagram showing a configuration of a conventional output circuit.

FIG. 29 is a timing chart showing the operation of the output circuit of FIG. 28.

[Explanation of symbols]

1 gradation voltage generation means 2-1 to 2-m selection circuit 3 control means 100-1 to 100-n to 100-2n gradation output circuit 101 circuit input terminal 102 circuit output terminals 70 and 103 operational amplifiers 71 and 104 offset Correction circuits 111, 112, 113, 131, 132, 141, 1
42, 151, 152, 161, 162 Switches 121, 122, 123, 124 Capacitors

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/36 G09G 3/36 H03F 3/45 H03F 3/45 A 3/68 3/68 BF term ( (Reference) 2H093 NA51 NA57 NC02 NC14 NC28 NC41 NC51 NC58 NC59 ND03 ND31 ND39 ND52 ND54 NG00 5C006 AC21 AF46 BB16 BC12 BF24 BF25 BF37 BF43 FA22 FA25 FA41 FA47 5C080 AA06 AA10 BB05 DD05 DD22 JJ05A02 JJ05 FF07 JJ07 JJ02 JJ05 FF07 JJ02 FF07 JJ02 FF07 JJ02 FF07 JJ02 FF07 JJ02 FF07 JJ02 FF07 JJ02 FF07 JJ02 FF07 JJ02 FF07 JJ02 FF07 JJ02 FF07 JJ02 FF07 JJ02 FF07 JJ02 FF07 JJ02 FF07 JJ02 FF07 FF07 FF07 FF07 FF02 FF FF07 FF07 FF07 FF07 FF07 FF07 FF07 FF07 FF07 FF07 FF07 FF07 FF07 FF07 FFWD AA47 AC13 AC36 AC78 AF18 AH10 AH17 AH19 AH25 AH29 AH38 AH44 AK02 AK05 AK09 AK67 AS08 AT01 AT02 AT06 DN01 DN14 DN22 DN23 DP01

Claims (30)

[Claims] 1. A grayscale voltage generating means for generating a plurality of grayscale voltages, and a plurality of output terminals of the grayscale voltage generating means are respectively provided to the grayscale voltage generating means via the output terminals of the grayscale voltage generating means. A plurality of gradation output circuits each having an operational amplifier that impedance-converts an input signal to be input, and a selection unit that selects a signal necessary for driving the display device from the output signals of the plurality of gradation output circuits. A drive circuit of a display device including, wherein each of the plurality of gradation output circuits has a storage unit that stores in advance each of the offset voltages generated in the operational amplifier according to the gradation voltage level of the input signal. And a control means for controlling each of the plurality of gradation output circuits to correct the output of the operational amplifier using the offset voltage stored in the storage means. The drive circuit of the location. 2. The drive circuit for a display device according to claim 1, wherein the storage means of each of the plurality of grayscale output circuits includes a plurality of capacitors that respectively store the offset voltage. 3. The control means selects one capacitor from the plurality of capacitors according to the grayscale voltage level of the input signal in the first period of one output period, and selects the selected capacitor as the selected capacitor. 3. The drive circuit of the display device according to claim 2, wherein each of the plurality of gradation output circuits is controlled to store the offset voltage of the operational amplifier. 4. The control means is configured to control the second output of the one output period.
4. Each of the plurality of grayscale output circuits is controlled to correct the output of the operational amplifier by using the offset voltage stored in the selected capacitor during the period of. Drive circuit of display device. 5. In each of the plurality of gradation output circuits, a circuit input terminal to which the input signal is supplied and one of a pair of input terminals of the operational amplifier are connected, and the control means is configured to The plurality of grayscale output circuits for connecting one end of the selected capacitor to the circuit input terminal and the other end to the other of the pair of input terminals and the output terminal of the operational amplifier during a first period. 5. The drive circuit of the display device according to claim 3, wherein the drive circuit controls each of the above. 6. The control means is configured to control the second of the one output period.
During one period, the one end is disconnected from the circuit input terminal, the other end is disconnected from the output terminal of the operational amplifier, and each of the plurality of grayscale output circuits is connected to connect the one end to the output terminal of the operational amplifier. The drive circuit of the display device according to claim 5, which is controlled. 7. The control means, during the first period, disconnects the selected capacitor in the previous one output period from the other of the pair of input terminals and the output terminal of the operational amplifier, the plurality of stages. 7. The drive circuit for a display device according to claim 6, wherein each of the adjustment output circuits is controlled. 8. The control means, when the grayscale voltage level of the input signal in the output period after the one output period is the same as the grayscale voltage level of the input signal in the one output period, 7. The drive circuit of the display device according to claim 4, wherein only the control in the second period is performed for each of the plurality of grayscale output circuits during the output period. 9. The control means has a gradation voltage level of the input signal in the output period after the one output period is the same as the gradation voltage level of the input signal in the one output period, and When the subsequent output period is an output period within a predetermined period after the one output period has elapsed, only the control in the second period is performed on each of the plurality of gradation output circuits through the subsequent output period. The driving circuit for a display device according to claim 4, wherein the driving circuit is performed for the display device. 10. Each of the plurality of gradation output circuits further includes a plurality of corrected output voltage holding capacitors which respectively hold a corrected gradation voltage of the output signal of the operational amplifier, and the control means includes: When correcting the output of the operational amplifier of each of the plurality of grayscale output circuits, the voltage held by the one corrected output voltage holding capacitor according to the grayscale voltage level of the input signal is applied to the output terminal of the operational amplifier. 10. The drive circuit of the display device according to claim 1, wherein each of the plurality of gradation output circuits is controlled to be applied to the display device. 11. A grayscale voltage generating means for generating a plurality of grayscale voltages and a plurality of output terminals of the grayscale voltage generating means are provided respectively, and through the output terminals of the grayscale voltage generating means. A plurality of gradation output circuits each having an operational amplifier that impedance-converts an input signal that is input,
A driving circuit of a display device, comprising: a selecting unit that selects a signal necessary for driving the display device from output signals of the plurality of gradation output circuits, wherein one of a pair of input terminals of the operational amplifier is input. A signal is supplied to the circuit input terminal of the gradation output circuit, each of the plurality of gradation output circuits, a plurality of capacitors, the other of the pair of input terminals and the output terminal of the operational amplifier. A first switch connected between the first switch and a second switch, one end of which is connected to one of the pair of input terminals,
A third switch connected between the other end of the second switch and the output terminal, and a plurality of plurality of switches connected between the other end of the second switch and one end of the plurality of capacitors, respectively. A capacitor selection switch, and a plurality of capacitor selection switches respectively connected between the other of the pair of input terminals and the other ends of the plurality of capacitors, and the capacitor selection switch according to the grayscale voltage level of the input signal. A drive circuit of a display device, comprising a switch control means for controlling the switch of each of the plurality of gradation output circuits to store the offset voltage of the operational amplifier in one of the plurality of capacitors. . 12. A grayscale voltage generating means for generating a plurality of grayscale voltages and a plurality of output terminals of the grayscale voltage generating means are respectively provided, and through the output terminals of the grayscale voltage generating means. A plurality of gradation output circuits each having an operational amplifier for impedance-converting the input gradation voltage;
A driving circuit of a display device, comprising: a selecting unit that selects a voltage required for driving the display device from the gradation voltages output from the plurality of gradation output circuits. Each has one capacitor, and during one output period, the offset voltage generated in the operational amplifier by the gradation voltage is stored in the capacitor, and the stored offset voltage is used to correct the output of the operational amplifier. Therefore, each of the plurality of gradation output circuits is controlled, and in each output period after the one output period, the output of the operational amplifier is corrected using the offset voltage stored in the capacitor in the one output period. A drive circuit for a display device, comprising a control means for controlling each of the plurality of gradation output circuits. 13. A grayscale voltage generating means for generating a plurality of grayscale voltages, and a plurality of output terminals of the grayscale voltage generating means are provided respectively, and through the output terminals of the grayscale voltage generating means. A plurality of gradation output circuits each having an operational amplifier that impedance-converts an input signal that is input,
A driving circuit of a display device, comprising: a selecting unit that selects a signal necessary for driving the display device from output signals of the plurality of gradation output circuits, wherein one of a pair of input terminals of the operational amplifier is input. A signal is supplied to the circuit input terminal of the gradation output circuit, and each of the plurality of gradation output circuits includes two capacitors, the other of the pair of input terminals, and the output terminal of the operational amplifier. A first switch connected between the first switch and a second switch, one end of which is connected to one of the pair of input terminals,
A third switch connected between the other end of the second switch and the output terminal, and two third switches connected between the other end of the second switch and one ends of the two capacitors, respectively. A capacitor selection switch, and two capacitor selection switches respectively connected between the other of the pair of input terminals and the other ends of the two capacitors, depending on the polarity of the gradation voltage of the input signal. Driving a display device comprising switch control means for controlling the switch of each of the plurality of grayscale output circuits to store the offset voltage of the operational amplifier in one of the two capacitors. circuit. 14. A mobile phone using the drive circuit of the display device according to claim 1. 15. A portable electronic device using the drive circuit of the display device according to claim 1. 16. A gradation voltage generating means for generating a plurality of gradation voltages, and a plurality of output terminals of the gradation voltage generating means are respectively provided to the gradation voltage generating means via an output terminal of the gradation voltage generating means. A plurality of gradation output circuits each having an operational amplifier and a plurality of capacitors for impedance-converting an input signal to be input, and a signal required for driving the display device is selected from the output signals of the plurality of gradation output circuits. A method of controlling a drive circuit of a display device, comprising: selecting means, wherein one capacitor is selected from the plurality of capacitors according to a grayscale voltage level of the input signal in a first period of one output period. A first step of controlling each of the plurality of gradation output circuits to store the offset voltage of the operational amplifier in the selected capacitor, and a second step of the one output period. And a second step of controlling each of the plurality of grayscale output circuits to correct the output of the operational amplifier using the offset voltage stored in the selected capacitor. Control method. 17. In each of the plurality of gradation output circuits, a circuit input terminal to which the input signal is supplied and one of a pair of input terminals of the operational amplifier are connected, and the first step is , The plurality of gray scales for connecting one end of the selected capacitor to the circuit input terminal and the other end to the other of the pair of input terminals and the output terminal of the operational amplifier during the first period. Controlling each of the output circuits, the second step disconnecting the one end from the circuit input terminal and the other end from the output terminal of the operational amplifier during the second period, and the one end to the operation. 17. The control method according to claim 16, wherein each of the plurality of gradation output circuits is controlled so as to be connected to the output terminal of the amplifier. 18. The first step comprises: disconnecting the selected capacitor from the other one of the pair of input terminals and the output terminal of the operational amplifier in the previous one output period in the first period. 18. The control method according to claim 17, further comprising controlling each of the gradation output circuits. 19. If the grayscale voltage level of the input signal in the output period after the one output period is the same as the grayscale voltage level of the input signal in the one output period, the grayscale voltage level is maintained throughout the subsequent output period. 18. The control method according to claim 16, wherein only the second step is performed for each of the plurality of gradation output circuits. 20. The grayscale voltage level of the input signal in the output period after the one output period is the same as the grayscale voltage level of the input signal in the one output period, and the subsequent output period is When the output period is within a predetermined period after the one output period has elapsed, only the second step is performed for each of the plurality of gradation output circuits throughout the subsequent output period. Claim 1
The control method according to 6 or 17. 21. A grayscale voltage generating means for generating a plurality of grayscale voltages and a plurality of output terminals of the grayscale voltage generating means are respectively provided, and through the output terminals of the grayscale voltage generating means. A plurality of gradation output circuits each having an operational amplifier that impedance-converts an input signal that is input,
Selecting a signal necessary for driving the display device from the output signals of the plurality of gradation output circuits, wherein one of the pair of input terminals of the operational amplifier is supplied with the input signal; Each of the plurality of grayscale output circuits is connected to a circuit input terminal of an output circuit, and each of the plurality of grayscale output circuits is connected between two capacitors and the other of the pair of input terminals and an output terminal of the operational amplifier. A first switch, a second switch having one end connected to one of the pair of input terminals, a third switch connected between the other end of the second switch and the output terminal, Two capacitor selection switches, each connected between the other end of the second switch and one end of the two capacitors, and each connected between the other of the pair of input terminals and the other end of the two capacitors. Two done A method of controlling a drive circuit of a display device having a capacitor selection switch, wherein one of the two capacitors stores an offset voltage of the operational amplifier according to a polarity of a grayscale voltage of the input signal. A control method comprising the step of controlling the switch of each of the plurality of gradation output circuits. 22. The control method according to claim 16, which is used as a control method of a drive circuit of a display device included in a mobile phone. 23. In each of the plurality of grayscale output circuits, a circuit input terminal to which the input signal is supplied and one of a pair of input terminals of the operational amplifier are connected, and the operational amplifier includes a plurality of the plurality of grayscale output circuits. A plurality of terminals each of which is connected to one end of a capacitor and can function as the other of the pair of input terminals; and the control means controls the selected capacitor among the plurality of terminals during the first period. The connected terminal is made to function as the other of the pair of input terminals, and the other end of the selected capacitor is connected to the circuit input terminal and one end thereof is connected to the output terminal of the operational amplifier.
The amplifier circuit according to claim 3, wherein each of the plurality of gradation output circuits is controlled. 24. The control means disconnects the other end of the selected capacitor from the circuit input terminal and disconnects one end from the output terminal of the operational amplifier during the second period of the one output period, and 24. The amplifier circuit according to claim 23, wherein each of the plurality of gradation output circuits is controlled to connect an end to an output terminal of the operational amplifier. 25. The control means, during the first period,
25. The amplifier circuit according to claim 24, wherein each of the plurality of gradation output circuits is controlled to disconnect the selected capacitor from the output terminal of the operational amplifier in the previous one output period. 26. In the operational amplifier, a control electrode is connected to one of the pair of input terminals to form a differential transistor pair at an input stage of the operational amplifier, and control electrodes are provided to the plurality of terminals. And a plurality of transistors each of which is capable of forming the differential transistor pair together with the first transistor, and the control means selects one of the plurality of transistors in the first period. The differential transistor pair is configured by a transistor having a control electrode connected to a capacitor via one of the plurality of terminals and the first transistor, thereby selecting the plurality of terminals from the plurality of terminals. 26. A terminal connected to a capacitor is caused to function as the other of the pair of input terminals. Amplifier circuit according. 27. A grayscale voltage generating means for generating a plurality of grayscale voltages and a plurality of output terminals of the grayscale voltage generating means are respectively provided, and through the output terminals of the grayscale voltage generating means. A plurality of gradation output circuits each having an operational amplifier that impedance-converts an input signal that is input,
A driving circuit of a display device, comprising: a selecting unit that selects a signal necessary for driving the display device from output signals of the plurality of gradation output circuits, wherein one of a pair of input terminals of the operational amplifier is input. Connected to a circuit input terminal of the gradation output circuit to which a signal is supplied,
Each of the operational amplifiers has a plurality of terminals that can function as the other of the pair of input terminals, and each of the plurality of grayscale output circuits has a plurality of capacitors each having one end connected to the plurality of terminals, A first switch having one end connected to one of the pair of input terminals; a second switch connected between the other end of the first switch and an output terminal of the operational amplifier; A plurality of capacitor selection switches respectively connected between the other end of the switch and the other ends of the plurality of capacitors,
A plurality of switches respectively connected between the plurality of terminals and an output terminal of the operational amplifier, wherein one of the plurality of capacitors is connected to one of the plurality of capacitors according to a grayscale voltage level of the input signal. In order to store the offset voltage of the operational amplifier, a terminal of the plurality of terminals connected to the one capacitor is made to function as the other of the pair of input terminals, and the switch of each of the plurality of gradation output circuits is set. An amplifier circuit comprising control means for controlling. 28. In each of the plurality of grayscale output circuits, a circuit input terminal to which the input signal is supplied and one of a pair of input terminals of the operational amplifier are connected, and the operational amplifier is configured to operate in the plurality of grayscale output circuits. A plurality of terminals each of which is connected to one end of a capacitor and can function as the other of the pair of input terminals, and wherein the first step is selected from the plurality of terminals during the first period. The plurality of terminals are connected to the capacitor to function as the other of the pair of input terminals, the other end of the selected capacitor is connected to the circuit input terminal, and the one end is connected to the output terminal of the operational amplifier. Controlling each of the gradation output circuits of
In the second period, the other end of the selected capacitor is disconnected from the circuit input terminal, the one end is disconnected from the output terminal of the operational amplifier, and the other end is connected to the output terminal of the operational amplifier in the second period. 17. The control method according to claim 16, wherein each of the plurality of gradation output circuits is controlled so as to do so. 29. In the first step, each of the plurality of grayscale output circuits is arranged to disconnect the selected capacitor in a previous one output period from an output terminal of the operational amplifier in the first period. 29. The control method according to claim 28, further comprising controlling. 30. A grayscale voltage generating means for generating a plurality of grayscale voltages and a plurality of output terminals of the grayscale voltage generating means are respectively provided, and through the output terminals of the grayscale voltage generating means. A plurality of gradation output circuits each having an operational amplifier that impedance-converts an input signal that is input;
Selecting a signal necessary for driving the display device from the output signals of the plurality of gradation output circuits, wherein one of the pair of input terminals of the operational amplifier is supplied with the input signal; The operational amplifier has two terminals each of which is connected to a circuit input terminal of the output circuit and can function as the other of the pair of input terminals. Each of the plurality of grayscale output circuits has one end having the two terminals. Two capacitors connected to each other, a first switch having one end connected to one of the pair of input terminals, and a capacitor connected between the other end of the first switch and the output terminal of the operational amplifier. A second switch, two capacitor selection switches respectively connected between the other end of the first switch and the other ends of the two capacitors, the two terminals, and the output terminal of the operational amplifier. of A method of controlling a drive circuit of a display device, comprising: two switches respectively connected to a plurality of switches, wherein one of the two capacitors is connected to one of the operational amplifiers according to a polarity of a grayscale voltage of the input signal. A step of causing one of the two terminals connected to the one capacitor to function as the other of the pair of input terminals and controlling the switch of each of the plurality of gradation output circuits so as to store an offset voltage; A control method comprising: