JP2003333410A - Imaging apparatus and method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain satisfactory focusing accuracy, and to reduce power consumption in finder operation. <P>SOLUTION: The imaging apparatus has an AF evaluation value calculation means and an image signal processing means. In this case, a pixel signal outputted from an imaging device is supplied to the AF evaluation value calculation means as it is, and the pixel signal after thin-out processing is supplied to the image signal processing means. As a result, the satisfactory focusing accuracy can be secured, and the life of a power supply in the imaging apparatus can be drastically lengthened. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup device and an image pickup method, and is particularly suitable for use in an electronic still camera having a display device for displaying pixel signals obtained via an image pickup device.

[0002]

2. Description of the Related Art Conventionally, an electronic still camera using a display device as a finder is known. The display device is, for example, a liquid crystal display element, and a moving image obtained through the image pickup element is displayed on the liquid crystal display element in real time. Thereby, the photographer can determine the shutter release timing by observing the screen of the liquid crystal display element and record a desired still image on the recording medium.

As described in Japanese Unexamined Patent Publication No. 9-93470, power consumption during finder operation is reduced by thinning out image signals output from the image pickup device for image data for finder display and then performing signal processing. Can be reduced.

[0004]

By the way, if the video signals output from the image pickup device are thinned out, the band of the video signals becomes narrow. Therefore, as described in JP-A-5-14796, when the contrast is detected from the video signal output from the image sensor to determine the in-focus position, the contrast is reduced by the thinning rate of the video signal. However, there is a problem in that good focusing accuracy cannot be obtained because the evaluation value of 1 changes.

The present invention has been made in view of the above problems, and an object of the present invention is to achieve both good focusing accuracy and reduction of power consumption during finder operation. To do.

[0006]

The image pickup apparatus of the present invention is
An image pickup apparatus having an F evaluation value calculation means and a video signal processing means, wherein a pixel signal output from an image pickup device is directly supplied to the AF evaluation value calculation means, and the pixel signal is supplied to the video signal processing means. It is characterized in that it is supplied after being thinned out. Another feature of the present invention is based on an image sensor, an A / D conversion unit for A / D converting a pixel signal output from the image sensor, and a pixel signal output from the image sensor. An AF evaluation value calculating means for evaluating the in-focus state, a video signal processing means for performing signal processing for displaying a pixel signal output from the image sensor on a display device, and an output of the A / D converting means. A thinning-out pixel signal thinning-out means,
The output of the A / D conversion means is supplied to the F evaluation value calculation means,
The video signal processing means is characterized in that the pixel signals digitized by the pixel signal thinning means are thinned by the pixel signal thinning means and then supplied. Another feature of the present invention is that it comprises a first clock generating means and a second clock generating means, and the image sensor and A / D conversion are performed by a clock signal generated by the first clock generating means. Means and the AF evaluation value calculation means are driven, and the video signal processing means is driven by the second clock generation means. Another feature of the present invention is that the frequency of the clock signal generated by the second clock generating means is slower than that of the clock signal generated by the first clock generating means. Another feature of the present invention is that the rate of the pixel signal input to the video signal processing means is lower than that of the clock signal generated by the first clock generating means.

The image pickup method of the present invention is an image pickup method having an AF evaluation value calculation step and a video signal processing step, wherein the pixel signal output from the image pickup element is directly supplied to the AF evaluation value calculation step, The video signal processing step is characterized in that the pixel signals are thinned out before being supplied. Another feature of the present invention is that an in-focus state is set based on an A / D conversion step of A / D converting a pixel signal output from an image sensor and a pixel signal output from the image sensor. AF evaluation value calculation step for evaluation, video signal processing step for performing signal processing for displaying a pixel signal output from the image sensor on a display device, and pixel signal thinning step for thinning output of the A / D conversion step And the A / D is added to the AF evaluation value calculation step.
The output of the converting step is supplied, and the pixel signal digitized in the pixel signal thinning step is thinned in the pixel signal thinning step and then supplied to the video signal processing step. Another feature of the present invention is that it includes a first clock generating step and a second clock generating step, and the image sensor, the A / D unit
The A / D conversion means in the conversion step and the AF evaluation value calculation means in the AF evaluation value calculation step are driven, and the video signal processing means in the video signal processing step is driven by the seventh clock generation step. It has a feature. In addition, other features of the present invention include:
The frequency of the clock signal generated in the second clock generating step is slower than the frequency of the clock signal generated in the first clock generating step.
Another feature of the present invention is that the first
The rate of the pixel signal input to the video signal processing step is lower than that of the clock signal generated in the clock generating step.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of an image pickup apparatus and an image pickup method of the present invention will be described with reference to the accompanying drawings.

FIG. 1 shows a focus detection circuit and an LCD according to the present invention.
It is a block diagram of an electronic still camera provided with a display circuit. As shown in FIG. 1, a light beam that has passed through an optical block 101 including a photographing lens and the like is reflected by a CCD (solid-state image sensor) 10
2 is guided to the light receiving surface. As a result, an image signal corresponding to the subject image is generated in the photodiode forming the light receiving surface of the CCD 102.

The CCD 102 is driven by the CCD driver 122. The CCD driver 122 is a CCD output from the first clock generation circuit 123 at a constant cycle.
It operates based on a clock signal. That is, the image signal is output from the CCD 102 in synchronization with the CCD clock signal output from the first clock generation circuit 123,
It is input to a CDS (correlated double sampling and hold) circuit 103. Then, the image signal is the CDS circuit 103.
In the A / D converter 104, predetermined signal processing such as removal of reset noise is performed, and sample holding is performed.
Is output to.

The A / D converter 104 performs A / D conversion according to the A / D clock signal output from the first clock generator 123. The A / D clock signal is the CCD
It has the same frequency as the clock signal and a predetermined phase relationship.

The pixel signal converted into a digital signal by the A / D converter 104 is input to the low-pass filter 105 and subjected to predetermined filter processing. The low pass filter 105 can change the filter coefficient.

The filtering process is performed for each pixel signal of the same color. When the filter coefficient is set to (0.25, 0.5, 0.25), the circuit shown in Fig. 2 calculates (output) = 0.25 * X0 + 0.5 * X2 + 0.25 * X4, and the low-pass The filter is applied.

The output of the low-pass filter 105 is thinned out in the thinning circuit 107. The thinning circuit 107 continuously outputs pixel signals of different colors as shown in FIG. 3 and sets the output valid flag to Hi, which indicates that the output data is valid.

Thereafter, a preset output prohibition period T1
No data is output during the period and the output valid flag is set to Low to indicate that the output data is invalid. When the output inhibition period T1 is set to 0, all the image data input to the thinning circuit 107 is output together with the output valid flag Hi.

In the data output from the thinning circuit 107, the data whose output valid flag is Hi is the signal processing circuit 1.
The data is input to S08 and subjected to color conversion, white balance, gamma correction, etc., and converted into YcrCb luminance and color difference signals.

The signal processing in the signal processing circuit 108 is
It is driven by the clock signal output from the second clock generator 124 and executed according to the output valid flag output from the thinning circuit 107.

The output signal of the signal processing circuit 108 is written in the memory 117, which is a volatile memory such as DRAM, via the memory controller 116. Signal processing circuit 108
Output signal of, for example, N via the LCD I / F 118.
It is converted into a TSC type analog signal and displayed on the LCD 119.

The luminance and color difference signals output from the signal processing circuit 108 and written in the memory 117 pass through the signal processing circuit 108 via the memory controller 116.
It is converted into, for example, an NTSC analog signal via the LCD I / F 118 and displayed on the LCD 119.

During the focus detection operation, the A / D converter 10
The pixel signal output from 4 is Y at the same time as the LPF 105.
It is also input to the signal generation circuit 109. Y signal generation circuit 1
09 has a configuration as shown in FIG. 4, for example,
In the figure, 60 is a subtractor for subtracting the optical black (OB) level of the CCD, 62 is an OB level register for setting the OB level of each color of the CCD,
Here, the case of four color red: R, green 1: G1, green 2: G2, and blue: B setting registers in the case of the Bayer array is shown.

This green has G1 and G2.
This means that the diagonal G of the four colors of Bayer can be set separately. Reference numeral 64 is a selector for switching the OB level register 62 for each color, and a switching signal is generated by 2 bits of the least significant bit of the horizontal counter and the least significant bit of the vertical counter to switch four colors. Reference numeral 66 is a multiplier for multiplying a white balance (WB) coefficient, 68 is a WB coefficient register for each color of a Bayer array CCD, 70 is a selector similar to the selector 64, and the WB coefficient register 6
8 is a selector for switching 8 for each color.

Reference numerals 72 to 74 form a base clip circuit for removing noise in the dark portion of the image data. Reference numeral 72 is a subtractor for subtracting a predetermined value from image data, 74 is a limiter for clipping a negative value generated by the subtractor, and 76 is a register for setting a base clip value. Reference numeral 78 is an FF for re-tapping the data from the base clip 76 with a clock.

As described above, the AF luminance signal generation circuit 40
There is no vertical delay line, and even if the number of pixels of the CCD increases, the circuit scale does not increase and the circuit scale can be relatively small. The AF evaluates the high-frequency component in the horizontal direction through a bandpass filter, and adjusts the focus so that its value becomes a peak.

Therefore, a relatively good AF evaluation value can be obtained without performing a filtering process in the vertical direction. Further, the AF is provided with a WB multiplier because it is necessary to match WB in order to match AF evaluations between a colorless subject and a colored subject. For the same reason, an OB subtraction circuit is necessary and provided. Further, it has a base clip circuit for noise removal, and constitutes a small-scale AF luminance signal generation circuit with a minimum circuit for performing AF with three circuits of OB subtraction 60, WB multiplication 66, and base clip 72. ing.

The bandpass filter (BPF) 110 includes:
The luminance signal output from the Y signal generation circuit 109 is input, and the DC component in the horizontal direction and the color carrier component of the image sensor are cut off here. The output of the BPF 110 is the integration circuit 1
11 and the peak hold circuit 112.

The gate circuit 125 is a circuit for generating an evaluation frame for AF evaluation. For example, only one frame can be generated on one screen, but three frames each in the horizontal and vertical directions, for a total of nine frames. Can be generated on one screen.

The integration circuit 111 integrates the output of the BPF 110 within the evaluation frame indicated by the gate control signal of the gate circuit 125. The integrating circuit 111 is driven by the A / D clock signal output from the first clock generator 123.

The peak hold circuit 112 inputs the output of the BPF 110 in the same evaluation frame at the same time as the integration circuit 111, and detects and holds the peak value of the signal level.
The peak hold circuit 112 is driven by the A / D clock signal output from the first clock generator 123.

The AF evaluation circuit 113 reads out the integration result and the evaluation value of the peak value from the integration circuit 111 and the peak hold circuit 112, respectively, judges the characteristics, and outputs a motor control signal to the motor control circuit 120.

FIG. 5 shows a relationship graph of changes in the focus lens position and the AF evaluation value. FIG. 7A shows a case where the AF evaluation value is obtained from the middle / high range luminance signal, and FIG. 9B) shows a low value when an LPF filter is applied in the LPF 105 and horizontal pixels are thinned out through the thinning circuit 107. The case where the evaluation value for AF is acquired from the luminance signal of the range is shown.

As can be seen from this figure, the LPF 105
In the low-frequency luminance signal obtained by applying the LPF filter and then thinning out horizontal pixels through the thinning-out circuit 107, the data accuracy for searching the in-focus position deteriorates, and at the same time the in-focusing accuracy also deteriorates. However, in the present embodiment, since the AF evaluation value is acquired from the low-frequency luminance signal without thinning out horizontal pixels, the accuracy of the data for searching the in-focus position is good, and a good in-focus state is obtained. Precision can be maintained.

The evaluation values output from the integration circuit 111 and the peak hold circuit 112 are updated every several H periods of CCD or every 1 V period. Therefore, even when the AF evaluation circuit 113 is driven by a clock slower than the A / D clock, the evaluation value can be obtained without data loss. The motor control circuit 120 drives the motor 121 according to the input motor control signal. The motor 121 moves the focus lens included in the optical block 101.

When a still image is recorded, a through operation is performed by setting the filter coefficient in the LPF 105 as shown in FIG. 6, and the thinning circuit 107 takes in data from the CCD 102 without performing horizontal thinning. After being converted into a YcrCb signal by the signal processing circuit 108 and converted into a recording format, for example, a JPEG compression format,
Recording is performed on the recording medium 115 through the I / F circuit 114.

When the CCD 112 cannot perform signal processing while taking in data as in the case of the interline type, the output of the thinning circuit 107 is once output to the MEMORY CONTROLER 1
16 to memory 117, then memory 1
After being converted from 17 to YcrCb signal by the read signal processing circuit 108 via MEMORY CONTROLER 116, and also converted into a recording format, for example, JPEG compression format.
Recording is performed on the recording medium 115 through the I / F circuit 114.

[0035]

As described above, according to the present invention, when the focus evaluation value is calculated, all the pixel signals output from the image pickup device are used and the video signal is generated. Since the signal processing is performed after the pixel signals output from the image sensor are thinned out, all pixel signals output from the optical block (image sensor) are used when calculating the focus evaluation value. Therefore, it is possible to ensure good focusing accuracy. Also, when creating a video signal,
Signal processing can be performed after the pixel signals output from the optical block (imaging element) are thinned out, and by doing so, the operating clock of the signal processing circuit can be lowered to significantly extend the life of the power supply of the imaging device. it can.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment of the present invention and illustrating a configuration example of an electronic still camera.

FIG. 2 is a block diagram showing a configuration of an arithmetic circuit in the low-pass filter according to the embodiment.

FIG. 3 is a diagram showing a timing showing an operation of a thinning circuit.

FIG. 4 is a block diagram showing an example of a Y signal generation circuit.

FIG. 5 is a characteristic diagram showing a relationship graph of a change between a focus lens position and an AF evaluation value.

FIG. 6 is a block diagram showing a configuration of an arithmetic circuit showing another example of setting filter coefficients.

[Explanation of symbols]

101 Optical block 102 CCD 103 CDS circuit 104 A / D converter 105 low-pass filter 107 thinning circuit 108 signal processing circuit 109 Y signal creation circuit 110 High-pass filter (HPF) 111 Integrator circuit 112 Peak hold circuit 113 AF evaluation circuit 114 interface (I / F) circuit 115 recording medium 120 motor control circuit 121 motor 123 First Clock Generator 124 Second Clock Generator 125 gate circuit

Front page continuation (51) Int.Cl. ⁷ identification code FI theme code (reference) H04N 5/335 G02B 7/11 D // H04N 101: 00 G03B 3/00 A (72) Inventor Yoshihiro Homma Ota, Tokyo 3-30-2, Shimomaruko, Canon Inc. F term (reference) 2H011 BA31 BB04 2H051 AA01 BA45 BA47 CE28 5C022 AA13 AB28 AB67 AC03 AC42 AC69 5C024 BX01 CY17 CY38 CY42 DX04 GX03 GY01 HX05 HX23

Claims (10)

[Claims] 1. An image pickup apparatus comprising an AF evaluation value calculation means and a video signal processing means, wherein the pixel signal output from an image pickup device is directly supplied to the AF evaluation value calculation means, and the video signal processing means. The image pickup device is characterized in that the pixel signals are thinned out before being supplied. 2. An image pickup device, an A / D conversion means for A / D converting a pixel signal output from the image pickup device, and an AF for evaluating a focusing state based on the pixel signal output from the image pickup device. An evaluation value calculation unit, a video signal processing unit that performs signal processing for displaying a pixel signal output from the image sensor on a display device, and a pixel signal thinning unit that thins out the output of the A / D conversion unit. The AF evaluation value calculation means is supplied with the output of the A / D conversion means, and the video signal processing means is supplied with the pixel signals thinned by the pixel signal thinning means after being thinned by the pixel signal thinning means. An imaging device characterized by the above. 3. A first clock generating means and a second clock generating means, wherein the image pickup device, the A / D converting means, and the AF evaluation value calculating means are driven by a clock signal generated by the first clock generating means. The image pickup apparatus according to claim 2, wherein the image signal processing means is driven by the second clock generating means. 4. The image pickup apparatus according to claim 3, wherein the frequency of the clock signal generated by the second clock generating means is slower than that of the clock signal generated by the first clock generating means. 5. The image pickup according to claim 3, wherein a rate of a pixel signal input to the video signal processing unit is lower than a clock signal generated by the first clock generating unit. apparatus. 6. An image pickup method comprising an AF evaluation value calculation step and a video signal processing step, wherein a pixel signal output from an image pickup element is directly supplied to the AF evaluation value calculation step, and the video signal processing step is performed. The image pickup method is characterized in that the pixel signals are thinned out and then supplied. 7. The pixel signal output from the image sensor is A /
A / D conversion step of D conversion, AF evaluation value calculation step of evaluating a focus state based on a pixel signal output from the image sensor, and displaying a pixel signal output from the image sensor on a display device. And a pixel signal thinning-out step of thinning out the output of the A / D converting step, and supplying the output of the A / D converting step to the AF evaluation value calculating step. The image pickup method is characterized in that the pixel signal digitized in the pixel signal thinning step is thinned in the pixel signal thinning step before being supplied to the video signal processing step. 8. A first clock generating step and a second clock generating step, wherein the image sensor and A in the A / D converting step are generated by a clock signal generated by the first clock generating step.
The D / D conversion means and the AF evaluation value calculation means in the AF evaluation value calculation step are driven, and the video signal processing means in the video signal processing step is driven by the seventh clock generation step. Item 7. The imaging method according to Item 7. 9. The imaging method according to claim 8, wherein the frequency of the clock signal generated by the second clock generating step is slower than the frequency of the clock signal generated by the first clock generating step. 10. The image pickup device according to claim 8, wherein a rate of a pixel signal input to the video signal processing step is lower than that of a clock signal generated by the first clock generating step. Method.