JP2003332906A - Pll (phase locked loop) frequency synthesizer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To precisely detect whether a PLL (phase locked loop) frequency synthesizer is in a locking state or not. <P>SOLUTION: A reference frequency-divider 104 divides a reference clock signal (CLK) output from a reference oscillator 103 and outputs a reference signal (fref0) with a predetermined frequency. A lock detecting timing signal generating circuit 105a of a lock detecting circuit 105 outputs a reference signal (fref) synchronizing with a clock signal for lock determination (CK1) and delaying only in one clock delay from the reference signal (fref0), and outputs a lock detecting timing signal (TLD) becoming an H level only during a period of more or less than one clock from the breaking timing. A lock determining circuit 105b makes a lock detecting signal (LD) be at the H level, if a falling of a divided signal (fdiv) occurs during the TDL is at the H level. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique relating to a PLL frequency synthesizer which generates a signal of an arbitrary frequency with high accuracy, and more particularly, to accurately determine that the frequency accuracy is maintained (locked state). It is related to the improvement for detecting.

[0002]

2. Description of the Related Art For example, a tuner of a television receiver,
A PLL frequency synthesizer is used to generate a signal with an arbitrary frequency and high frequency accuracy. This type of frequency synthesizer uses a PLL (Phase Lo
VCO (Voltage Controlled) in cked loop circuit
Oscillator) and a phase comparator are provided with a programmable counter so that a signal of any frequency can be generated with frequency accuracy according to a reference clock signal (CLK) using a crystal oscillator or the like. It has become.

In the frequency synthesizer as described above, in addition to requiring high frequency accuracy, it is possible to accurately determine whether or not the frequency fluctuation is in a stable state (lock state), for example, at the time of frequency switching. Detection is required. That is, for example, the frequency signal output from the PLL frequency synthesizer as described above is used as a reference for the operation of various other circuits. Therefore, in many cases, in order to operate these circuits properly, the lock signal is locked. It is necessary to operate it on condition that it is in the state.

To detect the lock state, specifically, for example, a controlled phase signal (fdiv) divided by a programmable counter and a reference clock signal (CL) are used.
K) is performed based on the signal from the phase comparator that compares the phase with the divided reference signal (fref). That is, from the phase comparator, for example, a period corresponding to the phase shift between the controlled phase signal (fdiv) and the reference signal (fref), more specifically, for example, the controlled phase signal (fdiv) or the reference signal (fref).
The phase difference signal (Sdi
f) is output. Therefore, by detecting the length of the period in which the phase difference signal is at the H level by the reference clock signal (CLK) (how many clocks), it is possible to detect whether or not the locked state. There is.

[0005]

However, the above-mentioned conventional PLL frequency synthesizer has a problem that it is difficult to detect with high detection accuracy whether or not it is in the locked state.

That is, the reference signal (fref)
Is a frequency-divided version of the reference clock signal (CLK), so that its rising edge and falling edge are synchronized with the phase of the reference clock signal (CLK). On the other hand, the controlled phase signal (fdiv) is a signal generated by a VCO that is completely different from the reference clock signal (CLK) and is divided in frequency, so that the rising edge and the falling edge and the reference clock signal (CLK) The relationship with the phase becomes indefinite.

Therefore, when the phase of the controlled phase signal (fdiv) leads the phase of the reference signal (fref), the rising edge of the phase difference signal (Sdif) is the phase of the reference clock signal (CLK). The timing becomes unrelated to, and the falling edge is synchronized with the reference clock signal (CLK). On the contrary, when the phase of the controlled phase signal (fdiv) is delayed, only the rising edge of the phase difference signal (Sdif) is synchronized with the reference clock signal (CLK).

Therefore, the length of the period in which the phase difference signal (Sdif) is at the H level is set to the reference clock signal (CL
K), the controlled phase signal (f
There may be a case where the number of clocks is different depending on whether the phase of div) is advanced or delayed, and therefore it is not possible to detect with high accuracy whether or not it is in the locked state.

As a method of detecting the locked state, for example, as disclosed in Japanese Patent Laid-Open No. 6-112817, the frequencies (cycles) of the reference signal (LDR) and the controlled phase signal (LDP) are compared. Although a method of performing detection by using the above method is also known, this causes a large increase in the circuit scale, and again, it is not always possible to perform detection with high accuracy.

In view of the above problems, an object of the present invention is to make it possible to detect with high accuracy whether or not the PLL frequency synthesizer is in a locked state.

[0011]

In order to solve the above-mentioned problems, a solution means provided by the invention of claim 1 is a PLL in which the phase of a controlled phase signal is controlled based on a reference phase signal.
A frequency synthesizer that outputs a reference clock signal and an oscillator that outputs the reference phase signal by dividing the reference clock signal and determines whether the edge of the reference phase signal is shifted by a predetermined time. A reference phase signal / determination timing signal output means for outputting a determination timing signal indicating a timing range, and an edge of the controlled phase signal based on the determination timing signal and the controlled phase signal is a range of the determination timing. And a phase difference determination signal output means for outputting a phase difference determination signal indicating whether or not it is within the range.

According to the invention of claim 1, the pulse width corresponding to the phase difference between the reference phase signal and the controlled phase signal is not detected, but only for a predetermined time with reference to the edge timing of the reference phase signal. Whether or not the phase difference between the reference phase signal and the controlled phase signal is a predetermined amount is determined depending on whether or not there is an edge of the controlled phase signal in the deviated range. Therefore, whether the PLL frequency synthesizer is in the locked state. It can be easily detected accurately.

The invention of claim 2 is the PL of claim 1.
In the L frequency synthesizer, the reference phase signal / judgment timing signal output means divides the reference clock signal and outputs a first phase signal, and a frequency divider for the first phase signal. First delay means for outputting the reference phase signal delayed by a predetermined number of clocks in a predetermined clock signal, and delaying a predetermined number of clocks in the predetermined clock signal with respect to the reference phase signal, A second delay means for outputting the second phase signal; and a decision timing signal output means for outputting the decision timing signal based on the first phase signal and the second phase signal. Is characterized by.

According to the second aspect of the present invention, the reference phase signal and the judgment timing signal as described above can be easily generated by performing the frequency division and the delay based on the reference clock signal.

The invention of claim 3 is the PL of claim 2
An L frequency synthesizer, wherein the decision timing signal output means is based on the first phase signal and the second phase signal and is at the predetermined level during the range of the decision timing. The phase difference determination signal output means outputs the phase difference determination signal according to whether or not an edge of the controlled phase signal exists while the determination timing signal is at the predetermined level. Is configured to be output.

According to the third aspect of the present invention, by detecting the level of the judgment timing signal at the edge timing of the controlled phase signal, the controlled phase signal is shifted within a range deviated from the edge of the reference phase signal by a predetermined time. It is possible to easily detect whether or not there is an edge.

The invention of claim 4 is the PL of claim 1.
The L frequency synthesizer is characterized in that the control characteristic of the phase of the controlled phase signal based on the reference phase signal is changed according to the phase difference determination signal.

According to the invention of claim 4, as described above, P
Since it is possible to accurately detect whether or not the LL frequency synthesizer is in the locked state, it is possible to easily perform appropriate control by changing the control characteristic of the controlled phase signal according to the detection result. it can.

According to a fifth aspect of the present invention, there is provided a PLL frequency synthesizer in which the phase of the controlled phase signal is controlled based on the reference phase signal, wherein the oscillator outputs the reference clock signal and the reference clock signal is divided. And a reference phase signal / judgment timing signal output means for outputting a judgment timing signal indicating a range of judgment timing deviated by a predetermined time from the edge of the reference phase signal A phase difference determination signal output means for outputting a phase difference determination signal indicating whether the edge of the controlled phase signal is within the determination timing range based on the determination timing signal and the controlled phase signal. And a phase comparator for outputting a phase difference pulse signal having a pulse width corresponding to the phase difference between the controlled phase signal and the reference phase signal, and A charge pump that outputs a phase difference voltage signal having a voltage corresponding to the pulse width of the phase difference pulse signal, a low-pass filter that removes a high frequency component in the phase difference voltage signal and outputs a frequency control voltage signal, and the frequency control A voltage controlled oscillator that outputs an output frequency signal having a frequency corresponding to the voltage signal, and a frequency divider that divides the output frequency signal and outputs the controlled phase signal are characterized.

According to the invention of claim 5, a signal having a frequency according to the frequency division ratio of the frequency divider and high frequency accuracy is obtained by the feedback control according to the phase difference between the controlled phase signal and the reference phase signal. In addition to the above, it is possible to easily accurately detect whether or not the PLL frequency synthesizer is in the locked state, as described in the first aspect.

The invention of claim 6 is the PL of claim 5
An L frequency synthesizer, wherein the frequency divider has a fixed frequency divider that divides the output frequency signal by a predetermined frequency division ratio,
And a variable frequency divider for dividing the output signal of the fixed frequency divider by a frequency division ratio according to the control signal.

According to the sixth aspect of the present invention, if a fixed frequency divider having a high response is used, a variable frequency divider having a low response can be used, so that a high frequency signal can be easily obtained. Obtainable.

The invention of claim 7 is the PL of claim 5
The L frequency synthesizer is characterized by further including an auxiliary charge pump that switches between an operating state and a stopped state according to the phase difference determination signal.

According to the invention of claim 7, as described above, P
Since it is possible to accurately detect whether or not the LL frequency synthesizer is in the locked state, by switching the operation state of the auxiliary charge pump according to the detection result, it is possible to perform appropriate feedback control and unlock. The oscillation frequency can be quickly converged in the state, and the stability can be increased in the locked state.

The invention of claim 8 is the PL of claim 5
The L frequency synthesizer is characterized in that the low-pass filter is configured so that a frequency characteristic changes in accordance with the phase difference determination signal.

According to the invention of claim 8, the PLL is also
Since it is possible to accurately detect whether or not the frequency synthesizer is in the locked state, by changing the frequency characteristic of the low pass filter according to the detection result, it is possible to perform appropriate feedback control and unlock the state. In this case, the oscillation frequency can be quickly converged, and the stability can be increased in the locked state.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(Configuration of PLL Frequency Synthesizer) FIG. 1
FIG. 1 is a block diagram showing an overall configuration of a PLL frequency synthesizer according to an embodiment of the present invention. In the figure, the VCO
The 101 (Voltage Controlled Oscillator) outputs an oscillation signal (fv) (output frequency signal) having a frequency corresponding to the frequency control signal (VT) (frequency control voltage signal). , An oscillation signal (fv) having a desired frequency can be obtained.

The comparison frequency divider 102 is a prescaler 102.
a (fixed frequency divider) and programmable counter 102b
(Variable frequency divider), and divides the oscillation signal (fv) based on the frequency division ratio data (DAT) corresponding to the frequency to be transmitted to the VCO 101, and divides the frequency division signal (fd).
iv) (controlled phase signal) is output.

The reference oscillator 103 outputs a reference clock signal (CLK) having a relatively high frequency accuracy by using, for example, a crystal oscillator.

The reference frequency divider 104 frequency-divides the reference clock signal (CLK) and outputs a reference reference signal (fref0) having a predetermined frequency.

The lock detection circuit 105 outputs a reference signal (fref) for comparing the phase with the divided signal (fdiv) based on the reference reference signal (fref0), and at the same time, the reference signal (fref). And a frequency difference between the frequency-divided signal (fdiv) and a predetermined range (locked state) is detected, and a lock detection signal (LD) (phase difference determination signal) is output. The detailed configuration of the lock detection circuit 105 will be described later.

The phase comparator 106 compares the phases of the divided signal (fdiv) and the reference signal (fref) and raises or lowers the oscillation frequency of the VCO 101 in accordance with the phase difference. Rising signal (u
p) and the drop signal (dn) (phase difference pulse signal).

The first charge pump 107 receives the VCO based on the rising signal (up) and the falling signal (dn).
Voltage signal (NF) for controlling the oscillation frequency of 101
(Phase difference voltage signal) is output. Also, the second
The charge pump 108 (auxiliary charge pump) is similar to the first charge pump 107,
Operation and stop are controlled by a lock detection signal (LD) output from the lock detection circuit 105.

The first low-pass filter 109 and the second low-pass filter 110 are the charge pump 107.
The frequency control signal (VT) from which the high frequency component is removed by smoothing the voltage signal (NF) output from 108 is output. Here, the second low-pass filter 110 has a frequency characteristic (for example, a large time constant) different from that of the first low-pass filter 109, and P
Only when the LL frequency synthesizer is not in the locked state, the charge pump 1 is connected via the analog switch 111.
It is connected to 07.108 to operate.

More specifically, the lock detection circuit 105 is, for example, as shown in FIG. 2, a lock detection timing signal generation circuit 105a (reference phase signal / determination timing signal output means) and a lock determination circuit 105b (phase difference determination signal). And an output unit). The lock detection timing signal generation circuit 105a includes three flip-flops 121 to 123 (delay means) and an AND circuit 1
24, the reference reference signal (fref0) is synchronized with the lock determination clock signal (CK1) of a predetermined frequency, and delayed by one clock before being output as the reference signal (fref). . In addition, the reference signal (fref)
Detection signal (TLD) that becomes H level for a period of about 1 clock from the falling timing of
(Determination timing signal) is output.
In addition, the lock determination circuit 105b includes a NOT circuit 126.
And a flip-flop 125, the lock detection signal (LD) that goes to H level when the divided signal (fdiv) falls while the lock detection timing signal (TLD) is at H level. It is designed to output.

Further, the first charge pump 107 is specifically, for example, as shown in FIG. 3, a NOT circuit 131.
And a P-type MOS transistor 132 and an N-type MOS transistor 133. When the rising signal (up) goes to the L level, the P-type MOS transistor 132 turns on, while the falling signal (dn) goes to the L level. When the N-type MOS transistor 133 is turned on, the voltage V
A voltage signal (NF) of CC or 0V is output.

The second charge pump 108 includes a logic circuit 134 (which outputs an L level signal when both inputs are at the L level) and a logic circuit 135 (both two inputs are at the L level). Sometimes outputs H level signal)
And a P-type MOS transistor 136 and an N-type MOS transistor 137, and the lock detection signal (LD) is L
Ascending signal (up) at level (unlocked state)
Becomes L level, the P-type MOS transistor 136 becomes O
N when the drop signal (dn) goes to L level
Type MOS transistor 137 is turned on and voltage VC
A voltage signal (NF) of C or 0V is output.

(Operation of PLL Frequency Synthesizer) Next, the operation of the PLL frequency synthesizer configured as described above will be described.

Prescaler 102a of the comparison frequency divider 102
Is the oscillation signal (fv) output from the VCO 101,
The frequency is divided by a predetermined division ratio, and further, the programmable counter 102b divides according to the division ratio data (DAT) given from the outside to generate a division signal (fd
iv) is output.

On the other hand, the reference frequency divider 104 includes the reference oscillator 1
The reference clock signal (CLK) output from the circuit 03 is divided by a predetermined division ratio to generate a reference reference signal (fref
0) is output.

Therefore, as shown in FIG. 4, the flip-flop 121 of the lock detection timing signal generation circuit 105a causes the reference reference signal (fr) at the rising timing of the lock determination clock signal (CK1).
ef0) is held and the output signal (Q1) and the inverted signal (NQ1) (first phase signal) are output, and the flip-flop 122 outputs the output signal (Q1) to the lock determination clock signal (CK1). ), And outputs as a reference signal (fref) (reference phase signal). The flip-flop 123 outputs an output signal (Q3) (second phase signal) obtained by further delaying the reference signal (fref) by one clock, and the AND circuit 124 outputs the inverted signal (NQ1). The lock detection timing signal (TLD) is output by ANDing with the signal (Q3). That is, the lock detection timing signal (TLD) is the reference signal (fre
It goes high for a period of one clock before and after the falling timing of f).

When the lock detection timing signal (TLD) is at the H level when the frequency division signal (fdiv) falls, the lock determination circuit 105b sets the lock detection signal (LD) at the H level and locks the lock signal. If the detection timing signal (TLD) is L level, the lock detection signal (LD) is set to L level. That is, within the range of about one clock of the lock determination clock signal (CK1) from the falling timing of the reference signal (fref), the frequency division signal (fdi) output from the comparison frequency divider 102.
When v) falls, it is determined to be in the locked state.

The phase comparator 106 also divides the divided signal (f
div) and the reference signal (fref) are compared in phase, and an up signal (up) and a down signal (dn) that are intermittently at the L level are output according to the phase difference. More specifically, for example, as shown in FIG. 5, the divided signal (fdi
When the phase of v) lags the phase of the reference signal (fref), the rising signal (up) becomes L level only during the delayed period (pulse width). On the other hand, when the phase of the divided signal (fdiv) is ahead,
Decrease signal (up) for only the period (pulse width) in which it is advanced
Becomes L level.

Therefore, in the first charge pump 107, while the rising signal (up) is at L level, P
Type MOS transistor 132 is turned on and the voltage signal (N
F) is controlled to be high, while the decrease signal (d
While n) is at L level, the N-type MOS transistor 133 is turned on and the voltage signal (NF) is controlled to be low. Further, the second charge pump 108, when the lock detection signal (LD) is at the H level (locked state), regardless of the level of the rising and falling signals (up, dn), the second charge pump 108 and the N-type MOS transistor 136. When both the transistors 137 are turned off and the lock detection signal (LD) is at L level (unlocked state), the same operation as the first charge pump 107 is performed. That is, in the unlocked state, the charge pumps 107 and 108 operate together to increase the loop gain, and feedback control is performed so that the oscillation frequency of the VCO 101 quickly converges and the lockup time is shortened. It will be.

The voltage signal (NF) output from the first charge pump 107 (and the second charge pump 108) is input to the first low pass filter 109. Further, when the lock detection signal (LD) is at H level (locked state), it is further input to the second low pass filter 110 via the analog switch 111.
Therefore, the frequency control signal (VT) that has been smoothed to remove the high frequency component is input to the VCO 101, and the VCO 10
The oscillation frequency of 1 is controlled to be a frequency according to the frequency division ratio data (DAT) given to the programmable counter 102b. Here, the second low-pass filter 110 has, for example, a time constant larger than that of the first low-pass filter 109, and is connected or disconnected according to the lock detection signal (LD) as described above,
The frequency characteristic of the whole changes, and the oscillation frequency of the VCO 101 quickly converges in the unlocked state, while the noise band is reduced to improve the S / N ratio and increase the stability in the locked state. Feedback controlled.

As described above, the pulse width of the phase difference signal output from the phase comparator 106 is not detected, but the edge timing of the reference signal (fref) is used as a reference for the lock determination clock signal (CK1). Depending on whether the level of the divided signal (fdiv) changes at the timing according to the cycle, the reference signal (fre
By determining whether the phase difference between f) and the divided signal (fdiv) is within a predetermined range, the locked state,
It is possible to accurately detect the unlocked state. Further, based on such a detection result, the operation of the second charge pump 108 and the second low-pass filter 110 is controlled to change the control characteristics, so that appropriate feedback control can be easily performed. .

The detection result of the locked state is not limited to controlling the operations of the second charge pump 108 and the second low-pass filter 110 as described above, but indicates, for example, the locked state or the unlocked state. Used to do
Oscillation signal output from PLL frequency synthesizer (f
It may be used for controlling a circuit using v).

The lock determination clock signal (C
K1) has a cycle corresponding to the phase difference determination period (range of detection timing), and has a reference clock signal (CL
K) in synchronization with the reference clock signal (CLK) or the reference clock signal (CL).
K) itself may be used. Also, the number of stages of the flip-flops 121 ... May be set corresponding to the phase difference determination period. Further, the flip-flop 121 may be omitted, for example, when the falling edge of the reference signal (fref0) is synchronized with the rising edge of the lock determination clock signal (CK1).

The rising and falling of each signal and the H and L levels in the above description are relative. For example, while the lock detection timing signal (TLD) is at the L level, the divided signal ( Various modifications are possible, such as detecting whether or not the rising edge of fdiv) occurs. Further, the specific circuit configuration is not limited to the above, and various circuit configurations that can obtain substantially the same action may be applied.

4 and 5, an example in which the duty ratio of the reference signal (fref) or the like is 1: 1 has been shown, but the present invention is not limited to this, and for example, a predetermined width is provided at the edge timing of each signal described above. The configuration as described above can be applied even when a signal that generates a pulse (for example, one clock of a clock signal) is used.

[0052]

As described above, according to the present invention, the PLL frequency synthesizer is locked in accordance with whether the edge timing of the divided signal is within a predetermined range based on the edge timing of the reference signal. By detecting whether or not there is, it is possible to easily perform highly accurate lock detection with a relatively small circuit scale, and it is easy to reliably reduce lockup time and improve stability in feedback control. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a PLL frequency synthesizer according to an embodiment.

FIG. 2 is a circuit diagram showing a specific configuration of a lock detection circuit 105 of the same.

FIG. 3 is a circuit diagram showing a specific configuration of charge pumps 107 and 108 of the same.

FIG. 4 is a timing chart showing the operation of the lock detection circuit 105.

FIG. 5 is a timing chart showing the operation of the phase comparator 106 of the same.

[Explanation of symbols]

CLK Reference clock signal CK1 Clock signal for lock judgment fv oscillation signal fdiv divided signal fref0 reference reference signal fref reference signal up rising signal dn drop signal NF voltage signal VT frequency control signal Q1 output signal NQ1 inverted signal Q3 output signal TLD lock detection timing signal LD lock detection signal 101 VCO 102 Comparative frequency divider 102a prescaler 102b programmable counter 103 Reference oscillator 104 Reference frequency divider 105 Lock detection circuit 105a Lock detection timing signal generation circuit 105b Lock determination circuit 106 Phase comparator 107 First charge pump 108 Second charge pump 109 First low-pass filter 110 Second low-pass filter 111 analog switch 121-123 flip-flops 124 AND circuit 125 flip flops 126 NOT circuit 131 NOT circuit 132 P-type MOS transistor 133 N-type MOS transistor 134 Logic circuit 135 Logic circuit 136 P-type MOS transistor 137 N-type MOS transistor

Claims (8)

[Claims] 1. A PLL frequency synthesizer in which the phase of a controlled phase signal is controlled based on a reference phase signal, the oscillator outputting a reference clock signal, and dividing the reference clock signal by dividing the reference phase signal. A reference phase signal / judgment timing signal output means for outputting a signal and outputting a judgment timing signal indicating a range of the judgment timing deviated by a predetermined time with respect to the edge of the reference phase signal; A phase difference determination signal output means for outputting a phase difference determination signal indicating whether or not the edge of the controlled phase signal is within the range of the determination timing based on the controlled phase signal. Featured PLL frequency synthesizer. 2. The PLL frequency synthesizer according to claim 1, wherein the reference phase signal / determination timing signal output means divides the reference clock signal and outputs a first phase signal. A first delay means for outputting the reference phase signal delayed by a predetermined number of clocks in a predetermined clock signal with respect to the first phase signal, and in the predetermined clock signal with respect to the reference phase signal. Second delay means for outputting a second phase signal delayed by a predetermined number of clocks, and a decision timing for outputting the decision timing signal based on the first phase signal and the second phase signal. A PLL frequency synthesizer comprising: a signal output unit. 3. The PLL frequency synthesizer according to claim 2, wherein the judgment timing signal output means is based on the first phase signal and the second phase signal, and is in the range of the judgment timing. The phase difference determination signal output means outputs the determination timing signal having a predetermined level, and whether the edge of the controlled phase signal exists while the determination timing signal is at the predetermined level. P is configured to output the phase difference determination signal according to
LL frequency synthesizer. 4. The PLL frequency synthesizer according to claim 1, wherein the phase control characteristic of the controlled phase signal based on the reference phase signal changes in accordance with the phase difference determination signal. A PLL frequency synthesizer characterized by: 5. A PLL frequency synthesizer in which the phase of a controlled phase signal is controlled based on a reference phase signal, the oscillator outputting a reference clock signal, and dividing the reference clock signal to obtain the reference phase. A reference phase signal / judgment timing signal output means for outputting a signal and outputting a judgment timing signal indicating a range of the judgment timing deviated by a predetermined time with respect to the edge of the reference phase signal; Phase difference determination signal output means for outputting a phase difference determination signal indicating whether or not the edge of the controlled phase signal is within the range of the determination timing based on the controlled phase signal, and the controlled phase signal And a phase comparator which outputs a phase difference pulse signal having a pulse width corresponding to the phase difference between the reference phase signal and the phase difference pulse signal A charge pump that outputs a phase difference voltage signal having a voltage according to the pulse width, a low-pass filter that removes high frequency components in the phase difference voltage signal and outputs a frequency control voltage signal, and a charge pump that responds to the frequency control voltage signal A PLL frequency synthesizer comprising: a voltage controlled oscillator that outputs an output frequency signal of a frequency; and a frequency divider that divides the output frequency signal and outputs the controlled phase signal. 6. The PLL frequency synthesizer according to claim 5, wherein said frequency divider divides said output frequency signal by a predetermined frequency division ratio, and an output signal of said fixed frequency divider. And a variable frequency divider that divides the signal at a frequency division ratio according to the control signal.
Frequency synthesizer. 7. The PLL frequency synthesizer according to claim 5, further comprising an auxiliary charge pump that switches between an operating state and a stopped state according to the phase difference determination signal. 8. The PLL frequency synthesizer according to claim 5, wherein the low-pass filter is configured to change frequency characteristics in accordance with the phase difference determination signal.