JP2003332901A - Integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress increase of power consumption by an unnecessary switching and to prevent the propagation of an unintended signal to an internal logic circuit without increasing the circuit scale, with respect to an input/output buffer which intervenes between a bidirectional external terminal and the internal logic circuit. <P>SOLUTION: An AND circuit 20 is inserted between an input/output buffer 10 and an internal logic circuit. An output signal Y0 of an input driver 11 and an enable signal EN are inputted to an input terminal of the AND circuit 20. The logic product of both the inputted signals is outputted to the internal logic circuit as an output signal Y1. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to integrated circuits.

[0002]

2. Description of the Related Art Conventionally, in a semi-custom IC such as an ASIC, a bidirectional external terminal is connected to an internal logic circuit via an input / output buffer. This input / output buffer propagates a signal to both the bidirectional external terminal and the internal logic circuit, and the input mode / output mode is switched by the connected input / output buffer enable signal. The "input mode" is a mode (state) in which a signal is propagated from the bidirectional external terminal to the internal logic circuit, and the "output mode" is a mode in which the signal is propagated from the internal logic circuit to the bidirectional external terminal. It means the mode (state) to do.

FIG. 5 is a diagram showing a logical configuration of the input / output buffer 10. According to the figure, the input / output buffer 10 is
It is composed of an input driver 11 and a 3-state output driver (hereinafter, simply referred to as “output driver”).

The bidirectional external terminal 30 and the output terminal of the output driver 12 are connected to the input terminal of the input driver 11, and the output signal Y is output from the output terminal to the internal logic circuit.

The output terminal of the output driver 12 is connected to the bidirectional external terminal 30 and the input terminal of the input driver 11, and the input signal A is input to the input terminal from the internal logic circuit. An input / output buffer enable signal (hereinafter simply referred to as “enable signal”) EN from the internal logic circuit is input to the control terminal.

The operation of the output driver 12 is controlled by the enable signal EN. In particular,
When the enable signal is L level, the output driver 12
Drive a signal. That is, the input signal A from the internal logic circuit passes through the output driver 12 and the bidirectional external terminal 3
Output to 0. On the other hand, when the enable signal EN is at H level, the output driver 12 does not drive the signal. That is, the input signal A from the internal logic circuit is not output to the bidirectional external terminal 30.

Next, the operation of the input / output buffer 10 will be described.

FIG. 6 is a diagram showing the operation in the input mode. According to the figure, when the H-level signal propagates to the enable signal EN, the input / output buffer 10 switches to the input mode.

That is, the output driver 12 is controlled by the enable signal EN of H level and does not drive the signal. Therefore, the input signal A from the internal logic circuit is not output to the bidirectional external terminal 30. Then, the input signal P1 from the bidirectional external terminal 30 is output to the internal logic circuit as the output signal Y via the input driver 11.

FIG. 7 is a diagram showing the operation in the output mode. According to the figure, when the L level signal propagates to the enable signal EN, the input / output buffer 10 switches to the output mode.

That is, the output driver 12 is controlled by the L-level enable signal EN and drives the signal. Therefore, the input signal A from the internal logic circuit is output to the bidirectional external terminal 30 as the output signal P via the output driver 12.

[0012]

However, the following problems occur in the input / output buffer 10 described above. That is, as described above, the input driver 11 does not have a control signal like the output driver 12. That is, the input driver 11, regardless of the input mode / output mode,
Always driving the signal.

Further, the output signal of the input driver 11 in the output mode is generally treated as High-Z (high impedance) or undefined, but in reality, it is CM.
Due to the structure of the OS, it is either the H level or the L level.

Therefore, in the output mode, actually, as shown in FIG. 8, a part of the output signal of the output driver 12 spills to the input side of the input driver 11 and goes to the H level via the input driver 11. Alternatively, the L level signal has been propagated to the internal logic circuit. As a result, a signal not intended by the circuit designer is propagated, and the internal logic circuit malfunctions.

And for preventing such malfunctions,
A selector circuit or a decoder circuit is often inserted in the internal logic circuit. However, considering the case of connecting a multi-bit data bus, it is necessary to insert selector circuits and decoder circuits for the number of bits, which causes a problem that the circuit scale increases.

Due to its structure, the CMOS consumes power when the signal switches to the H level or the L level. That is, even if the signal is not used in the output mode, switching is performed by the signal sneaking into the input driver 11, which causes a problem that the power consumption of the entire integrated circuit increases.

An object of the present invention is to suppress an increase in power consumption due to unnecessary switching without increasing the circuit scale in an input / output buffer which mediates between a bidirectional external terminal and an internal logic circuit, and to suppress the internal logic circuit. The problem is to prevent unintended propagation of signals to the.

[0018]

In order to solve the above problems, the invention according to claim 1 outputs a 3-state output driver (for example, the output driver 12 in FIG. 1) and an input signal to an internal circuit. An input buffer (for example, the input driver 11 in FIG. 1), and an input / output buffer (the input / output buffer 10 in FIG. 1) that switches between an output mode and an input mode according to a control signal to the 3-state output driver. In the integrated circuit, the fixing means for fixing the input signal to the low level in the output mode (for example, FIG.
AND circuit 20) is also included in the integrated circuit.

According to the first aspect of the invention, in the output mode, the input signal to the internal circuit is always fixed at the low level. Therefore, a stable low-level signal is supplied to the internal circuit, so that the CM configuring the internal circuit is
It is possible to suppress switching of the OS and suppress an increase in power consumption of the entire integrated circuit. Also,
By fixing the input signal, it is possible to prevent unintended signal propagation to the internal logic circuit.

According to a second aspect of the present invention, in the integrated circuit according to the first aspect, the fixing means inputs the control signal and the output signal of the input driver, and inputs a logical operation result to the input. It may be configured to be a logical operation gate that outputs as a signal.

According to the second aspect of the present invention, since the fixing means is realized by one logical operation gate for one input / output signal, an increase in circuit scale can be suppressed to a minimum. it can.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In the following description, the same elements as those of the conventional technique are designated by the same reference numerals, and detailed description thereof will be omitted.

FIG. 1 is a diagram showing a circuit configuration of the present embodiment. As shown in the figure, the circuit configuration of the present embodiment has a 2-input A circuit in the signal input / output stage with the input / output buffer 10.
The configuration is such that an ND circuit (hereinafter, simply referred to as “AND circuit”) 20 is added.

One of the input terminals of the AND circuit 20 is connected to the output terminal of the input driver 11 and the other is supplied with the enable signal EN, and the output terminal is connected to the internal logic circuit. Output signal Y1 is output. That is, the AND circuit 20 uses the input driver 1
A logical product of the output signal Y0 of 1 and the enable signal EN from the internal logic circuit is output as the output signal Y1 to the internal logic circuit.

Next, the operation of this embodiment will be described.

FIG. 2 is a diagram showing the operation in the input mode. According to the figure, when the H-level signal propagates to the enable signal EN, the input / output buffer 10 switches to the input mode.

That is, the input / output buffer 10 performs the same operation as in FIG. 6, and the input signal P1 from the bidirectional external terminal 30 is input.
Is output signal Y0 via the input driver 11,
It is input to one of the input terminals of the AND circuit 20.

At the same time, the enable signal EN from the internal logic circuit, that is, the H-level signal is sent to the AND circuit 20.
Input to the other input terminal of. Therefore, the AND circuit 2
0 outputs a signal of the same level as the output signal Y0 of the input driver 11 as the output signal Y1 to the internal logic circuit.

FIG. 3 is a diagram showing the operation in the output mode. According to the figure, when the L level signal propagates to the enable signal EN, the input / output buffer 10 is switched to the output mode.

That is, the input / output buffer 10 performs the same operation as in FIG. 8, and the input signal A from the internal logic circuit is output from the bidirectional external terminal 30 via the output driver 12 and the input driver From 11, some signal,
Specifically, an L level signal or an H level signal is input to one of the input terminals of the AND circuit 20 as the output signal Y0.

At the same time, the enable signal EN from the internal logic circuit, that is, the L level signal, is sent to the AND circuit 20.
Input to the other input terminal of. Therefore, the AND circuit 2
0 always outputs an L level signal as the output signal Y1 to the internal logic circuit regardless of the level of the output signal Y0 of the input driver 11.

As described above, the output signal Y1 input to the internal logic circuit is always fixed at the L level in the output mode by the AND circuit 20 provided in the signal input / output stage with the input / output buffer 10. To be done. Therefore, while preventing unintended signal propagation to the internal logic circuit,
By suppressing unnecessary switching of the CMOS constructed as an internal logic circuit, an increase in power consumption of the entire integrated circuit can be suppressed. Further, since only one AND circuit is added to the input / output signal from one bidirectional external terminal, it is possible to suppress the increase in circuit scale to the minimum.

The application of the present invention is not limited to the above-mentioned embodiment, but can be appropriately changed without departing from the spirit of the present invention.

For example, in the above embodiment, the output driver 12 is L active, but FIG.
It may be H active as shown in FIG. In this case, when the enable signal EN is at L level, it is in the input mode, and when it is at H level, it is in the output mode.

Further, the input / output buffer 10 is a fixed circuit connected to and mounted on the bidirectional external terminal 30, and it is assumed that the logic synthesis is impossible. Specifically, assuming the input / output buffer 10 provided as one package from the IC maker, the AND circuit 20 is inserted in the signal input / output stage from the input / output buffer 10 inside the internal logic circuit. As an IC specification, an AND circuit may be provided in advance inside the input / output buffer.

[0036]

According to the present invention, it is possible to suppress an increase in power consumption due to unnecessary switching and prevent an unintended signal from propagating to an internal logic circuit without increasing the circuit scale. .

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration in an embodiment.

FIG. 2 is a diagram showing an operation in “input mode”.

FIG. 3 is a diagram showing an operation in “output mode”.

FIG. 4 is a diagram showing a modified example of the embodiment.

FIG. 5 is a diagram showing a conventional circuit configuration.

FIG. 6 is a diagram showing an operation in “input mode”.

FIG. 7 is a diagram showing an operation in “output mode”.

FIG. 8 is a diagram showing a problem of the conventional technique.

[Explanation of symbols]

10 I / O buffer 11 Input driver 12 3-state output driver (output driver) 20 2-input AND circuit (AND circuit) 30 bidirectional external terminals

Claims (2)

[Claims] 1. An input / output buffer having a 3-state output driver and an input buffer for outputting an input signal to an internal circuit, wherein an input mode is switched between an output mode and an input mode by a control signal to the 3-state output driver. The integrated circuit, further comprising fixing means for fixing the input signal to a low level in the output mode. 2. The fixing means is a logic operation gate which receives the control signal and the output signal of the input driver and outputs a logic operation result as the input signal. Integrated circuit.