JP2003332888A - Filter device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve efficient filtering in a filter device, wherein the total of multiplication values respectively obtained by adding a plurality of time sequence values of an input signal to the same number of filter tap coefficients is defined as the filtered result of the input signal. <P>SOLUTION: A part of respectively continuous filter tap coefficients are assigned. Within a period of a unit time till the time sequential value of the input signal is changed-over, the time sequence values of the input signal are respectively multiplied with the whole assigned filter tap coefficients. A plurality of processing parts summing up combinations constituting the filtered result being a multiplication result concerning the time sequence values of the input signal whose number is the same as that of the assigned filter tap coefficients. The total value obtained by summing-up the total results to be the combinations which constitute the filtered result in the processing parts is defined as the filtered result of the input signal. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a filter device for filtering a signal, and more particularly to a filter device having a structure for efficiently implementing filtering of a transversal filter.

[0002]

2. Description of the Related Art In the field of communication, for example, filters such as transversal filters are used to filter communication signals. In the field of communication, for example, TDMA (Time Division Multiple Access) system and FDMA (Frequency Division Multiple Access)
There is a wireless communication system using a wireless communication system or a CDMA (Code Division Multiple Access) system. In such a wireless communication system, signals are wirelessly transmitted (transmitted or received) between a base station device and a mobile station device. To be done.

FIG. 14 shows a structural example of a general transversal filter. The transversal filter shown in the figure has (M-1) registers R (1),
R (2), ..., R (M-2), R (M-1), and M
, Multipliers J (1), J (2), ..., J (M-
1), J (M) and (M-1) adders K (1), K
(2), ..., K (M-2), and K (M-1). Here, M is a numerical value of 2 or more.

Further, a time series (input signal series) of signals to be filtered, which are input to the transversal filter, are time series sampled at a sampling period T ..., x (n-2), x (N-1), x
(N), x (n + 1), x (n + 2), ... Here, x (n) represents sample data acquired at time nT.

In addition, M multipliers J (1), J (2),
.., J (M-1), J (M), M filter tap coefficients h (1), h (2) ,.
Each of (M-1) and h (M) is given. Also,
As a result of filtering the input signal sequence by the transversal filter, the output sequence of the filter ...
y (n-2), y (n-1), y (n), y (n +
1), y (n + 2), ... Are output from the transversal filter. Here, y (n) represents output data at time nT.

[0006] Normally, a signal sequence processed in a transversal filter is often represented by a complex sequence, but since it does not relate to the essence of the present invention described later, in the present specification, for convenience of explanation. , Using simple notation.

An example of the filtering operation performed by the transversal filter will be shown. Each of the (M-1) registers R (1) to R (M-1) inputs a clock (sample clock) having a sampling cycle T of one cycle and inputs the input signal sequence x (n) with one sample clock. These registers are held for a period of time, and these (M-1) registers R (1) to R (M-1) are connected in cascade to form a (M-1) stage shift register. .
Each register R (1), R for the input signal sequence x (n)
Outputs from (2), ..., R (M-2), and R (M-1) at the same time are x (n-1) and x (n), respectively.
-2), ..., x (n-M + 2), x (n-M + 1)
It is expressed as.

M multipliers J (1), J (2), ...
., J (M-1), J (M), input signal sequence x
(N) and registers R (1), R (2), ..., R
(M-2), output from R (M-1) x (n-1), x
(N-2), ..., x (n-M + 2), x (n-M +)
1) is input to each of the input signals and each multiplier J
(1), J (2), ..., J (M−1), J (M), respectively, filter tap coefficients h (1), h
(2), ..., H (M−1), h (M) are multiplied and the multiplication result h (1) · x (n), h
(2) .x (n-1), ..., h (M-1) .x (n
-M + 2) and h (M) .x (n-M + 1) are output.

(M-1) adders K (1) to K (M-
In 1), the output h from the first-stage multiplier J (1)
(1) .multipliers J of the second and subsequent stages for x (n)
(2) -output from J (M) h (2) x (n-1)-
h (M) .x (n-M + 1) is the respective adder K
(1) to K (M-1) are gradually added, and the summation result of all of them is output data y (n) from the (M-1) th stage adder K (M-1). Is output as. Here, the output data y (n) is expressed as in Expression 1.

[0010]

[Equation 1]

[0011]

However, in the conventional transversal filter as shown in the above-mentioned conventional example, for example, the wiring area of the circuit for performing the calculation becomes very large, which causes a problem in the circuit configuration. There is a problem that the output timing of the output data y (n), which is the filtering result, changes when the design is changed such that the number of filter tap coefficients (the number of filter taps) is changed. It was

The present invention has been made in view of such conventional circumstances, and an object thereof is to provide a filter device capable of realizing efficient filtering. More specifically, the present invention provides a filtering result even when the number of filter taps is large and the wiring area can be made smaller than the conventional one, or when the number of filter taps is changed, for example. An object of the present invention is to provide a filter device capable of making the output timing of output data y (n) constant.

[0013]

In order to achieve the above object, in the filter device according to the present invention, each of the time-series values of the input signal and the same number of filter tap coefficients are multiplied by the following configuration. The sum of the values is used as the filtering result of the input signal. That is, the filter device according to the present invention is composed of a plurality of processing units, and a continuous partial filter tap coefficient is assigned to each processing unit. Each processing unit multiplies the time series value of the input signal by each of all the assigned filter tap coefficients within the unit time when the time series value of the input signal switches. Further, each processing unit sums up the multiplication results for the time-series values of the same number of input signals as the number of allocated filter tap coefficients, which are combinations forming the filtering result. Further, a value obtained by summing the summation results that are the combinations forming the filtering results for these plurality of processing units is set as the filtering result of the input signal.

Therefore, since a part of continuous filter tap coefficients is assigned to each processing unit and multiplication is performed on all the filter tap coefficients assigned to each processing unit, for example, the number of filter taps is large. However, the wiring area can be made smaller than the conventional one. Further, since a part of continuous filter tap coefficients is assigned to each processing unit, for example, even when the number of filter taps is changed, the filtering result is obtained by changing the assignment method. It is possible to make the output timing of the output data y (n) constant.

Further, since each processing unit is configured to multiply the time-series value of the input signal and each of all the assigned filter tap coefficients within a unit time when the time-series value of the input signal is switched, for example, conventional It is possible to acquire and output the filtering result from the input signal in the same processing time as compared with. As an example, when the input signal series x (n) is input to each processing unit, the input signal series x is input within one cycle of the sample clock.
It is possible to use a configuration in which only the multiplication related to (n) is performed. Even in such a configuration, in reality, for example, when a delay occurs between the processing units and time adjustment is required, etc., the processing unit performing the multiplication on the input signal sequence x (n) and other inputs. Signal sequence (for example, x (n-
1) etc.) may occur at the same time as the processing unit performing the multiplication. In addition, the filter device according to the present invention can realize filtering similar to a transversal filter, for example.

Here, the filter device according to the present invention may be applied to various fields such as wireless and wired communication fields. Various signals may be used as the input signal to be filtered, and for example, a temporally continuous signal is used. Further, as the plurality of time-series values of the input signal, for example, the values of the input signal at constant time intervals are used. As the fixed time interval, for example, a time interval of one cycle of the sample clock can be used.

Various modes may be used for allocating a continuous part of the filter tap coefficients to each processing unit. For example, a plurality of the same number of filter tap coefficients may be assigned to each processing unit. It is possible to use a mode of allocating, or a mode of allocating 1 or 2 or more filter tap coefficients to each processing unit in the same number or different numbers.

As the unit time for switching the time-series value of the input signal, for example, when the value of the input signal at a constant time interval is used, the time at the constant time interval is used. As described above, as the unit time, for example, the time of one cycle of the sample clock (time for one sample clock) can be used.

Further, in each processing unit, for example, the processing of sequentially multiplying the time series value of the input signal by each of all the assigned filter tap coefficients is performed for the time series values of the time-sequential input signal. I will go sequentially. As a specific example, the time-series value x (n) of the input signal is multiplied by the first filter tap coefficient H1 to be assigned, and the second time-series value x (n) is assigned to the time-series value x (n). The filter tap coefficient H2 is multiplied, and the time series value x (n) is assigned to the final N of the assigned values.
The second time series value x (n + 1) of the input signal is similarly multiplied by the N number of filter tap coefficients H1 to HN, and the same is applied thereafter. , The subsequent time series value of the input signal x (n +
2), x (n + 3), ... Are sequentially multiplied with N filter tap coefficients H1 to HN. In addition, it is efficient and preferable that each processing unit is configured to perform the multiplication process on all the assigned filter tap coefficients by the same multiplier.

In addition, in each processing unit, the multiplication results that are sequentially acquired are summed up of the multiplication results that are combinations forming the same filtering result. The number of multiplication results that are combinations that form the same filtering result is the same as the number of assigned filter tap coefficients. The number of processing units may be various,
A number smaller than the total number of filter tap coefficients is used. Various configurations may be used as the configurations of the respective processing units.

In addition, the summation results for the assigned filter tap coefficient portions are obtained in the respective processing units, and the summation results that are the combinations forming the filtering results for the plurality of processing units are summed,
The value of the summation result is obtained as the filtering result of the input signal. That is, when acquiring the sum of the multiplication values of the input signal and the plurality of filter tap coefficients as the filtering result, some of the filter tap coefficients are assigned to each of the plurality of processing units, and are assigned in each of the processing units. A sum total value of the multiplication values of the filter tap coefficients is acquired, and a value obtained by summing the sum total values acquired by the plurality of processing units is acquired as a filtering result of the input signal.

Next, as a concrete constitutional example of the present invention, a constitutional example as shown in a first embodiment and a second embodiment of the present invention described later will be shown. That is, in the filter device according to claim 1, M time-series values x (n) to x of the input signal.
(N-M + 1) and M filter tap coefficients h (1) to
Each multiplication value with h (M) {h (1) · x (n)}
Is a summation value of {h (M) .x (n-M + 1)} as a filtering result of the input signal, and the i-th stage has k consecutive filter tap coefficients h.
(M−i · k + 1) to h (M−i · k + k) are assigned and operated by the processing unit clock that switches k times within the unit time when the time series value of the input signal switches m = (M
/ K) processing units, and each processing unit is
The order of the filter tap coefficient h (z) is assigned to the time series value of the input signal in the order from the filter tap coefficient h (M−i · k + 1) having the smallest degree z to the maximum filter tap coefficient h (M−i · k + k). Filter tap coefficient h (M-i
.Multidot.k + 1) to h (M-i.k + k) and multiply the multiplication results obtained at each time of (k-1) processing unit clocks in order to add the assigned filter tap coefficients. The sum of the multiplication results for the time-series values of the same number of input signals as the combinations that form the filtering result is summed up, and the m processing units process the previous stage in the second and subsequent stage processing units. The summation result obtained by the processing units is added with the multiplication results obtained by the processing units of the second and subsequent stages after a time corresponding to (2k−1) processing unit clocks to obtain the filtering results for these m processing units. A filter device, wherein a value obtained by summing the summation results that form a combination is acquired as a filtering result of an input signal.

In such a configuration example, as an example, the feedback delay amount until the output from the adder provided in each processing unit and adding the multiplication results is input to the adder (same adder) Is the net (k-1) processing unit clock, and the delay amount between the adders provided in the adjacent processing units is the net (2k-1) processing unit clock.
In addition, the output signal from the adder provided in the preceding processing unit may be delayed to such an extent that the data cascaded to each processing unit (summation result of multiplication results in the preceding processing unit) can be calculated. For example, there is no particular limitation on the timing of actually passing the data between the adjacent processing units.

Next, as a concrete constitutional example of the present invention, constitutional examples as shown in third to sixth embodiments of the present invention which will be described later will be shown. That is, in the filter device according to claim 1, M time-series values x (n) to x (n of the input signal are included.
-M + 1) and M filter tap coefficients h (1) to h
Each multiplication value with (M) {h (1) · x (n)} ~
A filter device having a sum of {h (M) · x (n-M + 1)} as a filtering result of an input signal,
At the i-th stage, k consecutive filter tap coefficients h (M
-I · k + k) to h (M−i · k + 1) are assigned and operated by a processing unit clock that switches k times within a unit time when the time series value of the input signal switches m = (M /
k) number of processing units, and each processing unit includes a filter tap coefficient h (M−i · k + k) having a maximum degree z of the filter tap coefficient h (z) to a minimum filter tap coefficient h (M− i · k + 1) in the order of the time series values of the input signal and the assigned filter tap coefficient h (M−i · k)
k + k) to h (M−i · k + 1) are multiplied, and the multiplication result obtained at each time of (k + 1) processing unit clocks is sequentially added to obtain the same number as the number of assigned filter tap coefficients. Of the multiplication results of the time-series values of the input signals, which are combinations forming the filtering result, are summed,
In the processing units of the second and subsequent stages, the sum result obtained by the processing units of the previous stage is added to the multiplication result obtained by the processing units of the second and subsequent stages after the time of one processing unit clock, and these m A filter device, wherein a value obtained by summing the summation results, which is a combination forming the filtering result, is obtained as the filtering result of the input signal.

In such a configuration example, as an example, the feedback delay amount until the output from the adder provided in each processing unit and adding the multiplication results is input to the adder (same adder) Is the net (k + 1) processing unit clock, and the delay amount between the adders provided in the adjacent processing units is the net 1 processing unit clock.

A more specific configuration example of the present invention will be shown below. First, a configuration example as shown in a first embodiment of the present invention described later will be shown. That is, in the filter device according to claim 1, M time-series values x (n) to x (n of the input signal are included.
-M + 1) and M filter tap coefficients h (1) to h
Each multiplication value with (M) {h (1) · x (n)} ~
A filter device having a sum of {h (M) · x (n-M + 1)} as a filtering result of an input signal,
At the i-th stage, k consecutive filter tap coefficients h (M
-Ik + 1) to h (Mik + k) are assigned and operated by the processing unit clock that switches k times within the unit time when the time series value of the input signal switches m = (M /
k) number of processing units, and the first-stage processing unit includes a multiplier, an adder, a first delay element, a selector, and a second delay element, and a multiplier Is the time series value of the input signal and all the assigned filter tap coefficients h (Mk +
1) to h (M) are sequentially multiplied to output the multiplication result, and the adder adds the output from the multiplier and the output from the selector to output the addition result. The delay element delays the output from the adder by the (k−1) processing unit clock and outputs the delayed signal, the selector selects the output from the first delay element or a zero value and outputs the output, and the second delay element First
The output from the delay element is delayed by k processing unit clocks and output to the processing unit of the next stage, and the processing units of the i-th stage other than the first stage and the m-th stage add a multiplier and an adder. And a first delay element, a selector, and a second delay element, and the multiplier is assigned with the time series value of the input signal within a unit time when the time series value of the input signal is switched. Filter tap coefficients h (M−i · k + 1) to h (M−i · k +) of
k) are sequentially multiplied to output the multiplication result, the adder adds the output from the multiplier and the output from the selector and outputs the addition result, and the first delay element is the adder. From the first delay element or the output from the previous stage processing section, and the second delay element outputs the second delay element. Outputs the output from the first delay element to the processing section at the next stage after delaying the output by the k processing section clock, and the processing section at the mth stage is a multiplier, an adder, and a first delay element. And a selector, and the multiplier has a time series value of the input signal and all of the assigned filter tap coefficients h (1) to h (k) within a unit time at which the time series value of the input signal switches. And are sequentially multiplied to output the multiplication result, and the adder outputs the output from the multiplier. The output from the rectifier is added and the result of the addition is output, the first delay element delays the output from the adder by the (k-1) processing unit clock, and the delayed output is output by the selector. Output from the processing unit of the previous stage or the output from the processing unit of the m-th stage.
A filter device, wherein the output from the delay element is used as a filtering result of the input signal.

The filter device according to this structural example will be described in more detail. That is, the filter device according to the present configuration example has M time-series values x (n) to x (n−M) of the input signal.
+1) and M filter tap coefficients h (1) to h (M)
And respective multiplication values {h (1) · x (n)} to {h
The sum of (M) · x (n−M + 1)} is the filtering result of the input signal. Further, it is composed of m = (M / k) processing units, and the processing unit of the i-th stage (i = 1 to m) has k continuous filter tap coefficients h (M−i · k).
+1) to h (M−i · k + k) are assigned. Further, each processing unit operates by the processing unit clock that switches k times within the unit time when the time series value of the input signal switches.

The first-stage processing section is composed of a multiplier, an adder, a first delay element, a selector, and a second delay element. Here, the multiplier is used to calculate the time series value of the input signal and all the filter tap coefficients h (M−k +) assigned within the unit time when the time series value of the input signal is switched.
1) to h (M) are sequentially multiplied to output the multiplication result, and the adder adds the output from the multiplier and the output from the selector to output the addition result. The delay element delays the output from the adder by the (k−1) processing unit clock and outputs the delayed signal, the selector selects the output from the first delay element or a zero value and outputs the output, and the second delay element First
The output from the delay element is delayed by k processing unit clocks and output to the processing unit at the next stage (that is, the second stage).

The processing units of the i-th stage (that is, the second to the (m-1) th stages) other than the first and m-th stages are multipliers, adders, and It is configured by using a first delay element, a selector, and a second delay element. Here, the multiplier uses the time series values of the input signal and all the assigned filter tap coefficients h (M−i · k + 1) to h (M−i · k + k) within the unit time when the time series values of the input signal are switched. Are sequentially multiplied with each other to output the multiplication result, the adder adds the output from the multiplier and the output from the selector and outputs the addition result, and the first delay element outputs the addition result from the adder. The output is delayed by (k-1) processing unit clock and then output.
The selector selects and outputs the output from the first delay element or the output from the previous stage (that is, the (i−1) th stage) processing unit, and the second delay element outputs from the first delay element. Of the output of the k processing unit is delayed by the clock of the k processing unit, and
(+1) th stage).

The m-th stage processing section is composed of a multiplier, an adder, a first delay element, and a selector. Here, the multiplier sequentially multiplies the time series value of the input signal by each of all the assigned filter tap coefficients h (1) to h (k) within a unit time when the time series value of the input signal switches. The multiplication result is output, the adder adds the output from the multiplier and the output from the selector and outputs the addition result, and the first delay element processes the output from the adder by (k-1). The selector delays and outputs the partial clock, and the selector selects and outputs the output from the first delay element or the output from the previous stage (that is, the (m-1) th stage) processing unit. Then, the output from the first delay element of the m-th stage processing unit is set as the filtering result of the input signal.

Various numbers may be used as the number M of filter tap coefficients. Also, the number of processing units m
Is an integer, that is, a multiple of k is used as M. Note that in the superordinate concept of the present invention, M is k
A mode that is not a multiple of may be used. Further, as the processing unit clock that switches k times within the unit time when the time series value of the input signal switches, for example, when a time interval of one cycle of the sample clock (time for one sample clock) is used as the unit time. For this, a clock having a frequency k times the frequency of the sample clock can be used.

Further, when the selectors of the processing units in the first stage add the multiplication results which are the combinations forming the same filtering result by the adder, the first multiplication result of the combination is added. Since there is no target, a zero value is selected and output. On the other hand, for other multiplication results, the output from the first delay element, which is the cumulative addition result up to that point, is selected and output.

Similarly, when the selectors of the second to m-th processing units add the multiplication results which are the combinations forming the same filtering result by the adder, the first selector of the combination is added. Regarding the multiplication result, the output from the processing unit in the previous stage, which is the cumulative addition result up to that point, is selected and output, while the other multiplication results are the cumulative addition result up to that point. The output from the delay element of is selected and output.

Also, for example, the m-th stage processing section may be configured by using the second delay element similarly to the other processing sections. In this case, the m-th stage processing section may be constructed. The output from the second delay element is the filtering result of the input signal. Here, the output from the second delay element is a delayed version of the output from the first delay element, and is substantially the same as the output from the first delay element.

Further, for example, when m = 2, since there are only the first-stage processing unit and the m-th (= 2) -th processing unit,
Processing units other than the first stage and the m-th stage are not provided, and this configuration example also includes the configuration in the case where m = 2.

Next, a configuration example as shown in a second embodiment of the present invention described later will be shown. This configuration example is obtained by partially modifying the configuration example corresponding to the first embodiment of the present invention. That is, in the filter device according to claim 1, M time-series values x (n) to x (n-M +) of the input signal.
1) and each of M filter tap coefficients h (1) to h (M) multiplied by {h (1) · x (n)} to {h.
(M) .x (n-M + 1)} is a filter device that uses the sum of the values as the filtering result of the input signal,
At the stage, k consecutive filter tap coefficients h (M-i
・ K + 1) to h (M−i · k + k) are assigned,
The processing unit is composed of m = (M / k) number of processing units that are operated by a processing unit clock that is switched k times within a unit time when the time-series value of the input signal is switched. And a first delay element, a selector, and a second delay element, and the multiplier is assigned with the time series value of the input signal within a unit time when the time series value of the input signal is switched. Filter tap coefficient h (M−k + 1) of
To h (M) are sequentially multiplied to output the multiplication result, the adder adds the output from the multiplier and the output from the selector, and outputs the addition result. Outputs the output from the adder with a delay of (k-1) processing unit clock, the selector selects and outputs the output from the first delay element or a zero value, and the second delay element uses the adder. Hold the output from and output to the processing unit of the next stage,
The processing unit of the i-th stage other than the stage and the m-th stage is configured using a multiplier, an adder, a first delay element, a selector, and a second delay element, and the multiplier is All the filter tap coefficients h (M−i · k +) assigned to the time series value of the input signal within the unit time when the time series value of the input signal switches
1) to h (M−i · k + k) are sequentially multiplied to output the multiplication result, and the adder adds the output from the multiplier and the output from the selector to output the addition result. , The first delay element delays the output from the adder by the (k-1) processing unit clock and outputs the delayed signal, and the selector selects the output from the first delay element or the output from the previous processing unit. The second delay element holds the output from the adder and outputs it to the processing unit at the next stage, and the processing unit at the m-th stage is the multiplier, the adder, and the first delay unit. The multiplier is composed of an element and a selector, and the multiplier has the time series value of the input signal and all the assigned filter tap coefficients h (1) to h (k) within a unit time when the time series value of the input signal is switched. Each is sequentially multiplied by and the result of the multiplication is output, and the adder outputs the output from the multiplier and the The output from the adder is output and the addition result is output, the first delay element delays the output from the adder by the (k-1) processing unit clock, and the delayed output is output by the selector. Output from the processing unit of the previous stage is selected and output, and the output from the adder of the processing unit of the m-th stage is used as the filtering result of the input signal.
A filter device characterized by the above.

The filter device according to this structural example will be described in more detail. That is, the filter device according to the present configuration example has M time-series values x (n) to x (n−M) of the input signal.
+1) and M filter tap coefficients h (1) to h (M)
And respective multiplication values {h (1) · x (n)} to {h
The sum of (M) · x (n−M + 1)} is the filtering result of the input signal. Further, it is composed of m = (M / k) processing units, and the processing unit of the i-th stage (i = 1 to m) has k continuous filter tap coefficients h (M−i · k).
+1) to h (M−i · k + k) are assigned. Further, each processing unit operates by the processing unit clock that switches k times within the unit time when the time series value of the input signal switches.

The first-stage processing section is composed of a multiplier, an adder, a first delay element, a selector, and a second delay element. Here, the multiplier is used to calculate the time series value of the input signal and all the filter tap coefficients h (M−k +) assigned within the unit time when the time series value of the input signal is switched.
1) to h (M) are sequentially multiplied to output the multiplication result, and the adder adds the output from the multiplier and the output from the selector to output the addition result. The delay element delays the output from the adder by the (k-1) processing unit clock and outputs the delayed signal, the selector selects and outputs the output from the first delay element or a zero value, and the second delay element The output from the adder is held and output to the processing unit at the next stage.

The i-th stage processing section other than the first and m-th stages uses a multiplier, an adder, a first delay element, a selector, and a second delay element. Consists of
Here, the multiplier is a filter that includes all the filter tap coefficients h (M−i · k + 1) to h (M−i ·
k + k) are sequentially multiplied to output the multiplication result, the adder adds the output from the multiplier and the output from the selector and outputs the addition result, and the first delay element is the adder. From the first delay element or the output from the previous stage processing section, and the second delay element outputs the second delay element. Holds the output from the adder and outputs it to the processing unit at the next stage.

The m-th stage processing section is composed of a multiplier, an adder, a first delay element, and a selector. Here, the multiplier sequentially multiplies the time series value of the input signal and each of all the assigned filter tap coefficients h (1) to h (k) within a unit time when the time series value of the input signal is switched. The multiplication result is output, the adder adds the output from the multiplier and the output from the selector and outputs the addition result, and the first delay element processes the output from the adder by (k-1). The selector delays and outputs the partial clock, and the selector selects and outputs the output from the first delay element or the output from the processing unit of the previous stage. Then, the output from the adder of the m-th stage processing unit is used as the filtering result of the input signal.

Here, the second delay elements of the processing units of the first to (m-1) th stages are, for example, the timing at the time when the multiplication results of all the assigned filter tap coefficients are summed up. Holds the summation result (output from the adder) and outputs it to the processing unit at the next stage. Also,
For example, the m-th stage processing unit may be configured by using the second delay element similarly to the other processing units. In this case, the second delay element of the m-th stage processing unit is used. The output from is the filtering result of the input signal. Here, the output from the second delay element is a delayed version of the output from the adder, and is substantially the same as the output from the adder.

Next, a configuration example as shown in a third embodiment of the present invention described later will be shown. That is, in the filter device according to claim 1, M time-series values x (n) of the input signal.
~ X (n-M + 1) and M filter tap coefficients h
Each multiplication value of (1) to h (M) {h (1) · x
(N)} to {h (M) · x (n-M + 1)} is used as a filtering result of the input signal, and the i-th stage has k consecutive filter tap coefficients. h (M−i · k + k) to h (M−i · k + 1) are allocated, and m is operated by the processing unit clock that switches k times within the unit time when the time series value of the input signal switches.
= (M / k) processing units, and the first-stage processing unit is configured using a multiplier, an adder, a first delay element, a selector, and a second delay element. Then, the multiplier determines the time series value of the input signal and all the assigned filter tap coefficients h within the unit time when the time series value of the input signal switches.
(M) to h (M−k + 1) are sequentially multiplied to output the multiplication result, and the adder adds the output from the multiplier and the output from the second delay element to obtain the addition result. The first delay element delays the output from the adder by the k processing unit clock and outputs the delayed signal. The selector selects and outputs the output from the first delay element or the zero value, The delay element delays the output from the selector by one processing unit clock and outputs it, and outputs the output from the adder to the processing unit at the next stage, and the i-th stage (i = 2 to 1) other than the first stage. The processing unit of m) is configured using a multiplier, an adder, a first delay element, a selector, and a second delay element, and the multiplier has a unit time within which the time series value of the input signal switches. Input signal time series values and all assigned filter tap coefficients h (M
-I · k + k) to h (M−i · k + 1) are sequentially multiplied and the multiplication result is output, and the adder adds the output from the multiplier and the output from the second delay element. And outputs the addition result, the first delay element delays the output from the adder by k processing unit clocks, and outputs the output. The selector outputs the first delay element or the output from the previous processing unit. , The second delay element delays the output from the selector by one processing unit clock and outputs the output, and outputs the output from the adder for the processing units other than the mth stage to the next processing unit. To the output unit and the output from the adder of the m-th processing unit is used as the filtering result of the input signal.

Various numbers may be used as the number M of filter tap coefficients. Also, the number of processing units m
Is an integer, that is, a multiple of k is used as M. Note that in the superordinate concept of the present invention, M is k
A mode that is not a multiple of may be used. Further, as the processing unit clock that switches k times within the unit time when the time series value of the input signal switches, for example, when a time interval of one cycle of the sample clock (time for one sample clock) is used as the unit time. For this, a clock having a frequency k times the frequency of the sample clock can be used.

Further, when the selectors of the processing units in the first stage add the multiplication results which are the combinations forming the same filtering result by the adder, the first multiplication result relating to the combination is added. Since there is no target, a zero value is selected and output, and for other multiplication results, the output from the first delay element, which is the cumulative addition result up to that point, is selected and output.

Similarly, when the selectors of the second to m-th processing units add the multiplication results which are the combinations forming the same filtering result by the adder, the selectors corresponding to the first combination Regarding the multiplication result, the output from the processing unit in the previous stage, which is the cumulative addition result up to that point, is selected and output, while the other multiplication results are the cumulative addition result up to that point. The output from the delay element of is selected and output.

Further, for example, when m = 2, since there is only the first-stage processing unit and the m-th (= 2) -th processing unit,
Processing units other than the first stage and the m-th stage are not provided, and this configuration example also includes the configuration in the case where m = 2.

Next, a configuration example as shown in a fourth embodiment of the present invention described later will be shown. This configuration example is a modification of a part of the configuration example corresponding to the above-described third embodiment of the present invention. That is, in the filter device according to claim 1, M time-series values x (n) to x (n-M +) of the input signal.
1) and each of M filter tap coefficients h (1) to h (M) multiplied by {h (1) · x (n)} to {h.
(M) .x (n-M + 1)} is a filter device that uses the sum of the values as the filtering result of the input signal,
At the stage, k consecutive filter tap coefficients h (M-i
・ K + k) to h (M−i · k + 1) are assigned,
The processing unit is composed of m = (M / k) number of processing units that are operated by a processing unit clock that is switched k times within a unit time when the time-series value of the input signal is switched. A first delay element, a second delay element,
The multiplier is configured using a selector, and the multiplier has all the filter tap coefficients h (M) to h (M) assigned to the time series value of the input signal within a unit time when the time series value of the input signal is switched.
-K + 1) are sequentially multiplied to output the multiplication result, the adder adds the output from the multiplier and the output from the selector and outputs the addition result, and the first delay element adds The output from the output device is delayed by one processing unit clock and output, and the second delay element outputs the output from the first delay element by k.
The output is delayed by the processing unit clock, and the selector selects and outputs the output from the second delay element or the zero value.
The output from the delay element of is output to the processing unit of the next stage,
The processing units in the i-th stage other than the stage include a multiplier, an adder,
A first delay element, a second delay element, and a selector are used, and the multiplier is a time series value of the input signal and all filter taps assigned to the time series value of the input signal within a unit time. Coefficients h (M−i · k + k) to h (M−
i · k + 1) are sequentially multiplied to output the multiplication result, the adder adds the output from the multiplier and the output from the selector and outputs the addition result, and the first delay element is The output from the adder is delayed by one processing unit clock and output, the second delay element delays the output from the first delay element by k processing unit clock, and the second delay element outputs the output from the selector.
The output from the delay element or the output from the processing unit at the previous stage is selected and output, and the output from the first delay element for the processing units other than the m-th stage is output to the processing unit at the next stage, A filter device, wherein the output from the first delay element of the m-th stage processing unit is used as the filtering result of the input signal.

Next, a configuration example as shown in a fifth embodiment of the present invention described later will be shown. This configuration example is a modification of a part of the configuration example corresponding to the above-described third embodiment of the present invention. That is, in the filter device according to claim 1, M time-series values x (n) to x (n-M +) of the input signal.
1) and each of M filter tap coefficients h (1) to h (M) multiplied by {h (1) · x (n)} to {h.
(M) .x (n-M + 1)} is a filter device that uses the sum of the values as the filtering result of the input signal,
At the stage, k consecutive filter tap coefficients h (M-i
・ K + k) to h (M−i · k + 1) are assigned,
The processing unit is composed of m = (M / k) number of processing units that are operated by a processing unit clock that is switched k times within a unit time when the time-series value of the input signal is switched. A multiplier, a first delay element, and a selector, and the multiplier includes a time series value of the input signal and all assigned filter tap coefficients h (M ) To h (M−k + 1) are sequentially multiplied to output the multiplication result, and the adder adds the output from the multiplier and the output from the selector to output the addition result. Delay element delays the output from the adder by (k + 1) processing unit clock, and outputs the output. The selector selects the output from the first delay element or a zero value and outputs the output. Output to the processing unit of the second stage,
The i-th stage processing unit other than the first stage is configured by using a multiplier, an adder, a first delay element, a second delay element, and a selector, and the multiplier is for input signal All the filter tap coefficients h (M−i · k + k) to h assigned to the time series value of the input signal within the unit time when the time series value is switched
(M−i · k + 1) are sequentially multiplied to output the multiplication result, and the adder adds the output from the multiplier and the output from the selector to output the addition result. The delay element delays and outputs the output from the adder by (k + 1) processing unit clock, and the second delay element delays and outputs the output from the preceding processing unit by one processing unit clock,
The selector selects and outputs the output from the first delay element or the output from the second delay element, and outputs the output from the adder for the processing units other than the m-th stage to the processing unit in the next stage. ,
A filter device, wherein the output from the adder of the m-th processing unit is used as a filtering result of an input signal.

Here, for example, the processing unit of the first stage may also be configured by using the second delay element similarly to the other processing units, and in this case, the second delay element is zero. The value is delayed by one processing unit clock and output, and the selector selects and outputs the output from the first delay element or the output from the second delay element.

Next, a configuration example as shown in a sixth embodiment of the present invention described later will be shown. This configuration example is a modification of a part of the configuration example corresponding to the above-described third embodiment of the present invention. That is, in the filter device according to claim 1, M time-series values x (n) to x (n-M +) of the input signal.
1) and each of M filter tap coefficients h (1) to h (M) multiplied by {h (1) · x (n)} to {h.
(M) .x (n-M + 1)} is a filter device that uses the sum of the values as the filtering result of the input signal,
At the stage, k consecutive filter tap coefficients h (M-i
・ K + k) to h (M−i · k + 1) are assigned,
The processing unit is composed of m = (M / k) number of processing units that are operated by a processing unit clock that is switched k times within a unit time when the time-series value of the input signal is switched. And a first delay element, a selector, and a second delay element, and the multiplier is assigned with the time series value of the input signal within a unit time when the time series value of the input signal is switched. Filter tap coefficients h (M) to h (M
-K + 1) are sequentially multiplied to output the multiplication result, the adder adds the output from the multiplier and the output from the selector and outputs the addition result, and the first delay element adds The output from the output unit is delayed by (k + 1) processing unit clocks and output, the selector selects and outputs the output from the first delay element or the zero value, and the second delay element outputs the output from the adder. It is delayed by one processing unit clock and output to the processing unit of the next stage, and the i-th stage (i
= 2 to (m-1)), the processing unit of
The first delay element, the selector, and the second delay element are used, and the multiplier is a filter for all the filter taps assigned to the time series value of the input signal within a unit time when the time series value of the input signal is switched. Coefficients h (M−i · k + k) to h (M−
i · k + 1) are sequentially multiplied to output the multiplication result, the adder adds the output from the multiplier and the output from the selector and outputs the addition result, and the first delay element is The output from the adder is delayed by (k + 1) processing unit clocks and output, and the selector selects and outputs the output from the first delay element or the output from the processing unit of the previous stage, and the second output.
Delay element delays the output from the adder by one processing unit clock and outputs it to the processing unit at the next stage. The processing unit at the m-th stage is a multiplier, an adder, and a first delay element. And a selector, and the multiplier has a time series value of the input signal and all the assigned filter tap coefficients h (k) to h (1) within a unit time at which the time series value of the input signal switches. And are sequentially multiplied to output the multiplication result, the adder adds the output from the multiplier and the output from the selector and outputs the addition result, and the first delay element outputs the output from the adder. The (k + 1) processing unit clock is delayed and output, and the selector selects and outputs the output from the first delay element or the output from the previous processing unit, and outputs from the adder of the m-th processing unit. The output of is the filtering result of the input signal,
A filter device characterized by the above.

Note that, for example, the m-th stage processing unit may also be configured by using the second delay element similarly to the other processing units. In this case, in the m-th stage processing unit. The output from the second delay element is the filtering result of the input signal. Here, the output from the second delay element is a delayed version of the output from the adder, and is substantially the same as the output from the adder.

Next, a configuration example as shown in a seventh embodiment of the present invention described later will be shown. This configuration example is a combination of the configuration examples corresponding to the first and second embodiments of the present invention described above and the configuration examples corresponding to the third to sixth embodiments of the present invention described above. Is. That is, in the filter device according to claim 1, 2M time-series values x of the input signal
(N) to x (n-2M + 1) and 2M left-right symmetrical filter tap coefficients h (1) to h (2M) respectively multiplied values {h (1) · x (n)} to {h ( 2M) x (n-
2M + 1)} is used as a filtering result of the input signal, and k consecutive filter tap coefficients h (2M−i · k + k) to
h (2M−i · k + 1) is allocated, and is composed of 2m = (2M / k) processing units that operate by the processing unit clock that switches k times within the unit time when the time series value of the input signal switches. The processing units of the first stage to the m-th stage are configured by using the processing units constituting the filter device corresponding to the above-described first embodiment of the present invention or the above-described second embodiment of the present invention. The processing units of the (m + 1) th stage to the 2mth stage are configured by using the processing units constituting the filter device corresponding to any one of the third embodiment to the sixth embodiment of the present invention. , The first to m-th processing units and the second m-th to (m + 1) -th processing units each have a common multiplier.

Therefore, when a plurality of filter tap coefficients are symmetrical, the processing section of the i-th stage and the (2m-i +) th stage.
1) Since the multipliers are shared by the processing units (i = 1 to m) of the first stage, the number of multipliers can be reduced, and efficient filtering processing can be realized.

Here, various numbers may be used as the number 2M of filter tap coefficients, and an even number value is used. Also, 2M filter tap coefficients h (1) to h
(2M) being bilaterally symmetric means h (1) = h (2
M), h (2) = h (2M-1), ..., h (M-
1) = h (M + 2), h (M) = h (M + 1).

In the above, an example of the filter device constituted by using the processing units of various configurations has been shown, but if it is practically effective, for example, it may be configured by combining processing units of different configurations. A different filter device may be implemented,
Such a filter device is also included in the superordinate concept of the present invention.

[0056]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described with reference to the drawings. The present embodiment shows a transversal filter to which the filter device according to the present invention is applied. FIG. 1 shows an example of the overall configuration of a transversal filter according to this embodiment shown below. The transversal filter according to the present embodiment is configured by cascading the first arithmetic block B1 to the m-th arithmetic block Bm, which are m arithmetic blocks. Here, m is an arbitrary integer value, and is a numerical value of 2 or more in this embodiment.

The input signal series x (n) to be filtered is input to each of the operation blocks B1 to Bm.
Here, n represents the time, and in the present embodiment, it increases by 1 every time of one cycle of the sample clock. Then, the input signal sequence x is calculated by the operation of each of the calculation blocks B1 to Bm.
An operation with M filter tap coefficients is performed on (n) at once, and output data y (n) is output. Here, M is an arbitrary integer value, and is a numerical value of 2 or more in this embodiment.

Further, in this embodiment, each operation block B1
It is assumed that the number of filter tap coefficients (the number of filter taps) to be calculated within Bm is k. Here, k is an arbitrary integer value, and is a numerical value of 2 or more in the present embodiment. Further, it is assumed that an arithmetic clock having a frequency that is k times or more the frequency of the sample clock is input into each of the arithmetic blocks B1 to Bm, and there is a relationship of (m−1) · k <M ≦ m · k.

In the present embodiment, for convenience of explanation,
Unless otherwise specified, it is assumed that an operation clock having a frequency k times the sample clock frequency is used, and m.
Let k = M. Further, in the present embodiment, the plurality of processing blocks B1 to Bm constitute a plurality of processing units referred to in the present invention, and the arithmetic clock constitutes a processing unit clock referred to in the present invention.

First, the transversal filter according to the first embodiment will be described. FIG. 2 shows an internal configuration example of each of the operation blocks B1 to Bm that form the transversal filter of this example. In this example, each operation block B1 to
All of Bm have the same configuration as shown in the same figure, and the calculation result as shown in the above expression 1 is obtained.

Specifically, in FIG. 2, the i-th (i = 1 to 1)
m) is an example of the configuration of the operation block Bi, and in the operation block Bi, k filter tap coefficients h (M-
j-k + 1), h (M-j-k + 2), ..., h (M
-J) is calculated. Here, j = (i−1) · k, and j = 0, k, 2k, 3k, ..., (m−1) · k.
It takes a value such as.

The operation block Bi of this example includes a multiplier 1 and
It is composed of an adder 2, a delay element (first delay element) 3, a selector 4, and a delay element (second delay element) 5. Various configurations may be used as the delay element 3 and the delay element 5 as long as a desired delay can be obtained.
Specifically, shift registers and RAM (Random Access)
Memory) and the like.

An example of the operation performed by each of the processing units 1 to 5 constituting the arithmetic block Bi of this example will be shown. Multiplier 1
Is an input signal sequence x (n) and k filter tap coefficients h (M-j-k + 1) and h (M-j-k) assigned.
+2), ..., H (M−j) are multiplied one by one in the order of description of the filter tap coefficient, and the multiplication calculation result is sequentially output to the adder 2. Where 1
Each of the multiplication processes is performed every time of one cycle of the operation clock, whereby k multiplication processes are performed in the time of one cycle of the sample clock.

As an example, the first operation block B1
Assuming that k = 4 and M = 8, h
The filter tap coefficients of (5), h (6), h (7), and h (8) are sequentially given to the multiplier 1, and x (n) · h (5) and x (which are multiplication operation results. n) ・ h (6), x
(N) · h (7) and x (n) · h (8) are sequentially output to the adder 2.

The adder 2 inputs the multiplication operation result output from the multiplier 1 and the signal output from the selector 4 and sequentially adds them, and sequentially outputs the addition result to the delay element 3. Here, k filter tap coefficients h (M-j-
k + 1), h (M-j-k + 2), ..., h (M-j
-1), k addition results for h (M-j) are C
(J + k), C (j + k-1), ..., C (j +
2) and C (j + 1).

The delay element 3 delays the signal input from the adder 2 by (k-1) operation clock and outputs it as a feedback signal to the selector 4, and at the same time, the delay element 5 is connected in cascade to the delay element 5. Output as a signal.
In this example, the delayed addition result C (j + k) is used as a signal for cascade connection.

The selector 4 outputs (k-
1) The feedback signal (addition result) from the adder 2 delayed by the operation clock and input, and the cascade connection signal C (input from the (i-1) th operation block Bi-1 which is the previous stage. j) and switching is performed at a predetermined timing, and the feedback signal or the cascade connection signal C (j) is output to the adder 2. Regarding the first arithmetic block B1, since there is no preceding arithmetic block, a signal of zero value (“0”) is input to the selector 4 and switched to the feedback signal instead of the signal for cascade connection.

The delay element 5 further delays the signal C (j + k) output from the delay element 3 by one sample clock, and uses the delayed signal as a signal for cascade connection in the next stage. The data is output to the selector of the (i + 1) th operation block Bi + 1. With such a delay, timing adjustment is performed during cascade connection.

Here, the delay of one sample clock (one clock of the sample clock) corresponds to the delay of k operation clocks (k clocks of the operation clocks). For example, the delay processing is performed using the operation clocks. Can be done, and can also be done with C (j +
It is also possible to give a delay of one sample clock only to the signal of k).

Regarding the m-th arithmetic block Bm at the final stage, there is no arithmetic block at the next stage, and the signal output from the delay element 5 is the output data which is the filtering result of the input signal series x (n). y (n). Further, in the m-th arithmetic block Bm which is the final stage, it is not always necessary to delay the output signal, and therefore the delay element (second delay element) 5 may be omitted. Is.

An example of the flow of operations performed by the arithmetic block Bi of this example will be shown. The output from the adder 2 is delayed by the delay element 3 by the (k-1) operation clock and then input to the adder 2 as a feedback signal. Since the delay of k clocks in the operation clock is equal to the delay of 1 clock in the sample clock, if (k-1) delays of the operation clocks are performed, the multiplication results that are combinations that form the same filtering result are accumulated. Can be added to.

For example, C (j + 1) = C (j) + x (n ') finally calculated for the input signal sequence x (n').
When h (M-j) is fed back, in the input signal sequence x (n '+ 1) of the next sample clock, x (n' + 1) .h (M
-J-1) is added, and the addition operation result is C (j + 2) = C (j) + x (n '). H (M-j).
It becomes + x (n '+ 1) * h (M-j-1).

Input signal sequence x of next sample clock
In (n ′ + 2), further x (n ′ + 2) · h (M−j−
2) is added, and the addition result is C (j + 3) = C (j) +
x (n ′) · h (M−j) + x (n ′ + 1) · h (M−
j−1) + x (n ′ + 2) · h (M−j−2).
Similarly, after k sample clocks, the addition result C (j + k) = C (j) + x (n ′) · h (M−
j) + x (n ′ + 1) · h (M−j−1) + x (n ′ +
2) ・ h (M-j-2) + ... + x (n '+ k-1)
-H (M-j-k + 1) is passed to the next (i + 1) th operation block Bi + 1.

At this time, an input signal sequence x (n) of the same sample clock and k filter tap coefficients h (M-
j-k + 1), h (M-j-k + 2), ..., h (M
In the calculation with −j−1) and h (M−j), the signal C (j + k) for cascade connection becomes 1 by the adder 2 or the like.
It is calculated and output first. On the other hand, in the (i + 1) th arithmetic block Bi + 1, which is the next stage, the input signal sequence x (n + 1) of the next sample clock and k filter tap coefficients h (M-j-2k + 1), h (M -J-2
k + 2), ..., h (M-j-k-1), h (M-j
-K), the cascade connection signal C (j + k) from the previous stage is added last. For this reason,
As a timing for acquiring and outputting the cascade connection signal C (j + k), a delay margin corresponding to a net (2k-1) operation clock can be taken.

By performing such an operation, in the m-th operation block Bm at the final stage, for example, a filtering result similar to the filtering result obtained by the transversal filter shown in FIG. 14 can be obtained. , Output data y as shown in Equation 1 above
(N) can be output. In the configuration of the transversal filter of this example, the number of multipliers and adders can be reduced as compared with the transversal filter shown in FIG. 14, for example.

A more detailed specific example of the transversal filter of this example will be shown. FIG. 3 shows a configuration example in the case of M = 8, k = 4, and m = 2 as a specific example of the transversal filter of this example. Each calculation block B
1 and B2 include a multiplier 1, an adder 2, a delay element (first delay element) 3 and a selector 4 similar to those shown in FIG.
And a delay element (second delay element) 6 are provided. In this example, as the second delay element 6, one that delays by one sample clock based on the sample clock is used.

Further, FIG. 4 shows an example of a temporal flow of the operation performed by the transversal filter shown in FIG. Specifically, in FIG. 4, the signal of the operation clock, the signal of the input signal series x (n), and
Of the output data y (n) and the signal corresponding to each of the above. Here, the signals corresponding to each of ~ correspond to the signals flowing through the respective positions of ~ shown in FIG. In addition, in FIG. 4, the horizontal axis indicates time, and the time advances toward the right side.

As shown in FIG. 4, in the first operation block B1, the multiplication results for the plurality of assigned filter tap coefficients are accumulated in the combinations that form the same filtering result, and the second operation is performed. Block B
In 2, in addition to the accumulation result from the first operation block B1, multiplication results for a plurality of allocated filter tap coefficients are accumulated in a combination that constitutes the same filtering result, and thus the second operation is performed. Block B
Output data y which is the final filtering result from 2
(N) is output.

In the arithmetic block Bi of this example, the delay element 3 is connected to the output from the adder 2. Therefore, for example, by pipeline processing, the adder 11 itself used as the adder 2 as shown in the equalization block in FIG. Even when the actual addition result is delayed by k ′ operation clock and then output, the delay element 3 is adjusted by delaying by (k−1−k ′) operation clock. An operation similar to the example can be realized. Further, for example, the output from the selector 4 can be delayed by one operation clock, and the delay time by the delay element 3 can be reduced by that amount, that is, the net delay amount required for feedback is (k-1). It suffices if it is for the operation clock. Here, 0 ≦ k ′ <k. In this example, it is possible to configure a circuit corresponding to higher speed, and it is possible to secure a large delay margin between cascade connections.

Further, for example, when the delay elements 3, 5 and 6 are composed of memories or the like, it is possible to carry out the operation by setting the frequency of the operation clock to be at least k times the frequency of the sample clock. In such a case, for example, it is not always necessary to shift the input signal sequence x (n), and the calculation stored in the storage element after the input signal sequence x (n) is multiplied by the filter tap coefficient. Since it is possible to use a process of adding the multiplication result to a read result and storing the addition operation result in the storage element again, a DSP (Digital Signal Process) is used.
The processing block Bi itself can be replaced with a processor or the like.

As an example, k consecutive two types of address spaces A (g) and B (g) are provided (g = 1 to k), the input signal sequence x (n) is input, and the filter tap coefficient h is input.
The data of address A (g) is read from the result of multiplication with (g), the multiplication result is added to the data, and the addition result is written to address B (g-1). Is repeatedly performed while decrementing (decreasing), only the finally obtained calculation result y (n) is output, and when the next input signal sequence x (n + 1) is input, conversely from B (g) By the process of reading and writing to A (g-1), it is possible to perform an operation of cumulatively adding the multiplication results.

Here, the operation relating to the addresses A (g) and B (g) may be any operation that can obtain the same effect as the delay. As another example, using the same address space C (g), the input signal sequence x
In the calculation of (n), the data is read from the g-th address C (g), the calculation result is written in the same address C (g) after the calculation, and the next input signal sequence x (n + 1) is calculated. Data is read from the (g + 1) th address C (g + 1), and the same address C (g
It is also possible to perform an operation such as writing the calculation result to +1).

The multiplier 1, the adder 2, the memory, the shift register, etc. may be, for example, commercially available FP.
It is often incorporated in a GA (Field Programmable Gate Array) or the like, and it is possible to easily configure a transversal filter as in this example by using such an FPGA.

As described above, in the transversal filter of this example, m operation blocks (first operation block B1 to mth operation block Bm) are cascade-connected,
The calculation of each filter tap coefficient for the input signal sequence x (n) is completed within one cycle of the sample clock, and the results are sequentially delayed and added with the calculation results for other input signal sequences to obtain the final result. The addition result is used as the filter output. Further, in each of the arithmetic blocks B1 to Bm, the multiplier 1 multiplies the input signal sequence x (n) input in synchronization with the sample clock by k filter tap coefficients with a frequency equal to or more than k times the frequency of the sample clock. The arithmetic operation clock of the frequency is input, and the adder 2 inputs the output from the multiplier 1 and its own operation result delayed by (k-1) clocks and fed back or input from the operation block in the previous stage by a cascade connection. Value (“0” value at the beginning of the cascade) is added, the first delay element 3 delays the output from the adder 2 by (k−1) clocks, and the selector 4 The feedback signal and the cascade connection signal (or “0” value) are switched at a specific timing, and the second delay element 5 delays the delay between the adders 2 between the cascade input and output. There performing delay so that the net (2k-1) clock delayed by the operation clock.

Therefore, in the transversal filter of this example, one multiplier and one adder are used in each of the calculation blocks B1 to Bm to multiply a plurality of filter tap coefficients by a calculation clock faster than the sample clock. For example, even if the number of filter tap coefficients (number of filter taps) increases,
It is possible to prevent the number of wirings from increasing or not increasing so much. Further, in the transversal filter of this example, a plurality of filter tap coefficients are divided into m pieces and assigned to m pieces of operation blocks B1 to Bm. Regardless of this, the delay time required for the calculation can be made constant, and the timing of outputting the calculation result which is the filtering result can be made constant. Therefore, the transversal filter of this example is
For example, the circuit configuration can be simplified compared to the conventional one,
In addition, it is very versatile. Further, in the transversal filter of this example, for example, an LSI (Large Scale Integr
ation) is easy, and it is particularly suitable for a configuration using an FPGA having a built-in multiplier, adder, and shift register.

Next, the transversal filter according to the second embodiment will be described. FIG. 6 shows an internal configuration example of each of the operation blocks B1 to Bm that form the transversal filter of this example. In this example, each operation block B1 to
All of Bm have the same configuration as shown in the same figure, and the calculation result as shown in the above expression 1 is obtained.

Specifically, in FIG. 6, the i-th (i = 1 to 1)
m) is an example of the configuration of the operation block Bi, and in the operation block Bi, k filter tap coefficients h (M-
j-k + 1), h (M-j-k + 2), ..., h (M
-J) is calculated. Here, j = (i−1) · k, and j = 0, k, 2k, 3k, ..., (m−1) · k.
It takes a value such as.

The operation block Bi of this example is the multiplier 21.
, Adder 22, and delay element (first delay element) 23
, Selector 24, and delay element (second delay element) 25
It consists of Here, the operation block Bi of the present example
Compared with the operation block Bi shown in FIG. 2 of the first embodiment, the configuration of (1) directly outputs the signal for cascade connection from the adder 22, and the net (2k-1)
Instead of delaying by the operation clock, a delay element 25 that holds at the timing when a signal for cascade connection is output is used.

That is, as described above, the signal for cascade connection is first calculated and output from the adder 22, but is used in the (i + 1) th calculation block Bi + 1 in the next stage. Since it is the last one, it is necessary to hold the data during that time, and during that time, the operation of the next input signal sequence x (n + 1) occurs first. The two data are held, and the signal for cascade connection has a delay of substantially (2k-1) clocks.

With such a configuration, the transversal filter of this embodiment can also obtain the same filtering result as the transversal filter shown in the first embodiment, and the same effect can be obtained.
A transversal filter having a similar function may be implemented by using various configurations. For example, the output of the adder 22 may be delayed by (k−1) operation clocks and fed back to the inter-operation blocks Bi. Adder 2
The delay between the two may be given by (2k-1) operation clocks.

Next, the transversal filter according to the third embodiment will be described. FIG. 7 shows an internal configuration example of each of the operation blocks B1 to Bm that constitute the transversal filter of this example. In this example, each operation block B1 to
All of Bm have the same configuration as shown in the same figure, and the calculation result as shown in the above expression 1 is obtained.

Specifically, in FIG. 7, the i-th (i = 1 to 1)
m) is an example of the configuration of the operation block Bi, and in the operation block Bi, k filter tap coefficients h (M-
j), h (M-j-1), ..., h (M-j-k +
2), h (M-j-k + 1) is calculated. Where j
= (I−1) · k, and j = 0, k, 2k, 3k, ...
.., (m-1) .k, etc.

The operation block Bi of this example is the multiplier 31.
, Adder 32, and delay element (first delay element) 33
, Selector 34, and register (second delay element) 35
It consists of Various configurations may be used as the delay element 33 as long as a desired delay can be obtained.
ess Memory) and the like.

An example of the operation performed by each of the processing units 31 to 35 constituting the operation block Bi of this example will be shown. The multiplier 31 receives the input signal sequence x (n) and k filter tap coefficients h (M-j), h (M-j-1),
..., h (M-j-k + 2), h (M-j-k + 1)
Is calculated one by one in the order in which the filter tap coefficients are written, and the multiplication calculation result is sequentially output to the adder 32. Here, the multiplication processing one by one is performed every time of one cycle of the operation clock, whereby k multiplication processings are performed in the time of one cycle of the sample clock.

As an example, the first operation block B1
Assuming that k = 4 and M = 8, h
The filter tap coefficients of (8), h (7), h (6), and h (5) are sequentially given to the multiplier 31, and the multiplication operation result x (n) · h (8), x ( n) ・ h (7), x
(N) · h (6) and x (n) · h (5) are sequentially output to the adder 32.

The adder 32 inputs the multiplication operation result output from the multiplier 31 and the signal output from the register 35 and sequentially adds them, and sequentially outputs the addition result as a feedback signal to the delay element 33. At the same time, the addition result C (j + k) is output as a signal for cascade connection to the (i + 1) th operation block Bi + 1 which is the next stage. Here, k filter tap coefficients h (M-
j), h (M-j-1), ..., h (M-j-k +
2), k (M + j-k + 1) k addition results are C (j + 1), C (j + 2), ..., C (j + k-).
1) and C (j + k). Note that, in reality, the same C (j + 1) to C (j + k) as the feedback signal is added by the adder 3
Although it is output from No. 2, C (j + k) is used in the (i + 1) th operation block Bi + 1 which is the next stage.

The delay element 33 delays the signal input from the adder 32 by k operation clocks and selects the selector 34.
Output to. The selector 34 outputs k via the delay element 33.
The feedback signal (addition result) from the adder 32 delayed by the operation clock and input, and the (i)
-1) The cascade connection signal C (j) input from the 1st operation block Bi-1 is switched at a predetermined timing, and the feedback signal or the cascade connection signal C (j) is transferred to the register 35. Output to. Regarding the first operation block B1, since there is no previous operation block, a signal of zero value (“0”) is input to the selector 34 and switched to the feedback signal instead of the signal for cascade connection.

The register 35 further delays the signal output from the selector 34 by one operation clock,
The delayed signal is output to the adder 32. That is, from the register 35 to the adder 32, (k +
1) A feedback signal delayed by an operation clock or a cascade connection signal (or zero value) from the previous stage delayed by one operation clock is output.

Regarding the m-th arithmetic block Bm which is the final stage, there is no arithmetic block of the next stage, and the signal output from the adder 32 is the output data which is the filtering result of the input signal series x (n). y (n).

An example of the flow of operations performed by the arithmetic block Bi of this example will be shown. The output from the adder 32 is delayed by (k + 1) operation clocks by the delay element 33 and the register 35, and then input to the adder 32 as a feedback signal. K in operation clock
Since the delay of the clock is equal to the delay of one clock in the sample clock, if the delay of the (k + 1) operation clock is performed, the multiplication results which are the combinations forming the same filtering result can be cumulatively added. .

For example, C (j + 1) = C (j) + x (n ') calculated first for the input signal sequence x (n').
When h (M-j) is fed back, in the input signal sequence x (n '+ 1) of the next sample clock, x (n' + 1) .h (M
-J-1) is added, and the addition operation result is C (j + 2) = C (j) + x (n '). H (M-j).
It becomes + x (n '+ 1) * h (M-j-1).

Input signal sequence x of the next sample clock
In (n ′ + 2), further x (n ′ + 2) · h (M−j−
2) is added, and the addition result is C (j + 3) = C (j) +
x (n ′) · h (M−j) + x (n ′ + 1) · h (M−
j−1) + x (n ′ + 2) · h (M−j−2).
Similarly, after k sample clocks, the addition result C (j + k) = C (j) + x (n ′) · h (M−
j) + x (n ′ + 1) · h (M−j−1) + x (n ′ +
2) ・ h (M-j-2) + ... + x (n '+ k-1)
-H (M-j-k + 1) is passed to the next (i + 1) th operation block Bi + 1.

By performing such an operation, in the m-th operation block Bm at the final stage, for example, a filtering result similar to the filtering result obtained by the transversal filter shown in FIG. 14 can be obtained. , Output data y as shown in Equation 1 above
(N) can be output. In the configuration of the transversal filter of this example, the number of multipliers and adders can be reduced as compared with the transversal filter shown in FIG. 14, for example.

A more detailed specific example of the transversal filter of this example will be shown. FIG. 8 shows a configuration example in the case of M = 8, k = 4, and m = 2 as a specific example of the transversal filter of this example. Each calculation block B
1 and B2 have the same multiplier 31 as that shown in FIG.
An adder 32, a delay element (first delay element) 33, a selector 34, and a register (second delay element) 35 are provided.

Further, FIG. 9 shows an example of the temporal flow of the operation performed by the transversal filter shown in FIG. Specifically, in FIG. 9, the signal of the operation clock, the signal of the input signal series x (n), and
Of the output data y (n) and the signal corresponding to each of the above. Here, the signals corresponding to each of ~ correspond to the signals flowing through the respective positions of ~ shown in FIG. Further, in FIG. 9, the horizontal axis indicates time, and the time advances toward the right side.

As shown in FIG. 9, in the first operation block B1, the multiplication results for the plurality of assigned filter tap coefficients are accumulated in the combinations that form the same filtering result, and the second operation is performed. Block B
In 2, in addition to the accumulation result from the first operation block B1, multiplication results for a plurality of allocated filter tap coefficients are accumulated in a combination that constitutes the same filtering result, and thus the second operation is performed. Block B
Output data y which is the final filtering result from 2
(N) is output.

Here, for example, when the delay element 33 is composed of a memory or the like, it is possible to carry out the calculation by setting the frequency of the calculation clock to be at least k times the frequency of the sample clock. In such a case, for example, it is not always necessary to shift the input signal sequence x (n),
After multiplying the input signal sequence x (n) by the filter tap coefficient, the multiplication result is added to the read operation result stored in the storage element, and the addition operation result is stored again in the storage element. Since only processing can be used, DSP (Digital Signal Processo)
It is suitable for processing by a processor such as r), and the arithmetic block Bi itself can be replaced by a processor or the like.

As an example, k consecutive two types of address spaces A (g) and B (g) are provided (g = 1 to k), the input signal sequence x (n) is input, and the filter tap coefficient h is input.
The data at address A (g) is read from the result of multiplication with (g), the multiplication result is added to the data, and then the addition result is written to address B (g + 1), and such an operation is incremented by g. Repeatedly (increasing), only the finally obtained calculation result y (n) is output, and when the next input signal sequence x (n + 1) is input, conversely, it is read from B (g). A (g + 1)
By the processing of writing to, it is possible to perform an operation of cumulatively adding the multiplication results.

Here, the operation relating to the addresses A (g) and B (g) may be any as long as the same effect as the delay is obtained. As another example, using the same address space C (g), the input signal sequence x
In the calculation of (n), the data is read from the g-th address C (g), the calculation result is written in the same address C (g) after the calculation, and the next input signal sequence x (n + 1) is calculated. Data is read from the (g + 1) th address C (g + 1), and the same address C (g
It is also possible to perform an operation such as writing the calculation result to +1).

Further, the multiplier 31, the adder 32, the memory, the shift register, etc. are often built in, for example, a commercially available FPGA (Field Programmable Gate Array), and such an FPGA is used. As a result, it is possible to easily configure the transversal filter as in this example.

As described above, in the transversal filter of this example, m operation blocks (first operation block B1 to mth operation block Bm) are cascade-connected,
The calculation of each filter tap coefficient for the input signal sequence x (n) is completed within one cycle of the sample clock, and the results are sequentially delayed and added with the calculation results for other input signal sequences to obtain the final result. The addition result is used as the filter output. Further, in each of the operation blocks B1 to Bm, the multiplier 31 multiplies the input signal sequence x (n) input in synchronization with the sample clock by k filter tap coefficients with a frequency equal to or more than k times the frequency of the sample clock. The arithmetic operation clock of the frequency is input, and the adder 32 outputs the output from the multiplier 31 and its own operation result after being delayed by (k + 1) clocks and fed back, or is input from the operation block of the previous stage by a cascade connection. Value (0 value at the beginning of the cascade) is added to the first delay element 3
3 delays the output from the adder 32 by k clocks, and the selector 34 switches between the feedback signal and the cascade connection signal (or “0” value) at a specific timing, and the register 35 Is one operation clock so that the delay between the adders 32 between the cascade input and output is a delay of one operation clock and the delay of the feedback signal is a delay of (k + 1) clocks of the operation clock. Make a minute delay.

Therefore, in the transversal filter of this example, one multiplier and one adder are used in each of the operation blocks B1 to Bm to perform multiplication on a plurality of filter tap coefficients by an operation clock that is faster than the sample clock. For example, even if the number of filter tap coefficients (number of filter taps) increases,
It is possible to prevent the number of wirings from increasing or not increasing so much. Further, in the transversal filter of this example, a plurality of filter tap coefficients are divided into m pieces and assigned to m pieces of operation blocks B1 to Bm. Regardless of this, the delay time required for the calculation can be made constant, and the timing of outputting the calculation result which is the filtering result can be made constant. Therefore, the transversal filter of this example is
For example, the circuit configuration can be simplified compared to the conventional one,
In addition, it is very versatile. Further, in the transversal filter of this example, for example, an LSI (Large Scale Integr
ation) is easy, and it is particularly suitable for a configuration using an FPGA having a built-in multiplier, adder, and shift register.

Next, a transversal filter according to the fourth embodiment will be described. FIG. 10 shows an internal configuration example of each of the operation blocks B1 to Bm that constitute the transversal filter of this example. In this example, each operation block B1
All of Bm to Bm have the same configuration as shown in the same figure, and the calculation result as shown in the above Expression 1 is obtained.

Specifically, in FIG. 10, the i-th (i = 1)
~ M), an example of the configuration of the operation block Bi is shown. In the operation block Bi, k filter tap coefficients h (M
-J), h (M-j-1), ..., h (M-j-k +
2), h (M-j-k + 1) is calculated. Where j
= (I−1) · k, and j = 0, k, 2k, 3k, ...
.., (m-1) .k, etc.

The operation block Bi of this example is the multiplier 41.
, Adder 42, and register (first delay element) 43
, A delay element (second delay element) 44, and a selector 45.
It consists of and. Here, the calculation block B of this example
The configuration of i is such that the register 43 is arranged not in the preceding stage of the adder 42 but in the latter stage thereof, as compared with the arithmetic block Bi shown in FIG. 7 of the third embodiment. Calculation block B of this example
At i, the delay of the feedback signal to the adder 42 becomes the delay of (k + 1) operation clocks, which is the same as the case of the third embodiment. For example, the selector 45 selects and outputs the cascade connection signal C (j). The same operation as in the case of the third embodiment can be realized only by changing the timing of the operation.

With such a configuration, the transversal filter of this embodiment can also obtain the same filtering result as the transversal filter shown in the third embodiment, and the same effect can be obtained.
Note that, for example, when the delay element 44 is composed of a memory or the like, it is possible to perform the calculation by setting the frequency of the calculation clock to be at least k times the frequency of the sample clock.

Next, a transversal filter according to the fifth embodiment will be described. FIG. 11 shows an internal configuration example of each of the operation blocks B1 to Bm that form the transversal filter of this example. In this example, each operation block B1
All of Bm to Bm have the same configuration as shown in the same figure, and the calculation result as shown in the above Expression 1 is obtained.

Specifically, in FIG. 11, the i-th (i = 1)
~ M), an example of the configuration of the operation block Bi is shown. In the operation block Bi, k filter tap coefficients h (M
-J), h (M-j-1), ..., h (M-j-k +
2), h (M-j-k + 1) is calculated. Where j
= (I−1) · k, and j = 0, k, 2k, 3k, ...
.., (m-1) .k, etc.

The operation block Bi in this example is the multiplier 51.
An adder 52, a delay element (first delay element) 53 that delays by (k + 1) operation clocks, and a register (second delay element) 54 that delays by one operation clock,
And a selector 55.

Here, the structure of the arithmetic block Bi of this example is the same as that of the register 35 as shown in FIG. 7 of the third embodiment.
Therefore, compared with the operation block Bi which delays the feedback signal and delays the cascade input signal,
The delay of the feedback signal and the delay of the cascade input signal are individually performed. Specifically, the register 54 is arranged in the preceding stage of the selector 55, and the delay element 53 delays by (k + 1) operation clocks. Also in this case, the total number of delay clocks of the feedback signal is (k + 1) operation clocks, which is the same as in the third embodiment. For example, the selector 55 selects and outputs the cascade connection signal C (j). The same operation as in the case of the third embodiment can be realized only by changing the timing of the operation.

With such a configuration, the transversal filter of this example can also obtain the same filtering result as the transversal filter shown in the third embodiment, and the same effect can be obtained.
Note that the register 54 does not necessarily need to use the operation clock, and for example, the cascade connection signal C (j) is used.
A register 54 may be used to hold the signal in synchronism with the timing at which is output. Further, for example, when the delay element 53 is composed of a memory or the like, it is possible to perform the calculation by setting the frequency of the operation clock to be at least k times the frequency of the sample clock.

Next, a transversal filter according to the sixth embodiment will be described. FIG. 12 shows an internal configuration example of each of the operation blocks B1 to Bm that form the transversal filter of this example. In this example, each operation block B1
All of Bm to Bm have the same configuration as shown in the same figure, and the calculation result as shown in the above Expression 1 is obtained.

Specifically, in FIG. 12, the i-th (i = 1)
~ M), an example of the configuration of the operation block Bi is shown. In the operation block Bi, k filter tap coefficients h (M
-J), h (M-j-1), ..., h (M-j-k +
2), h (M-j-k + 1) is calculated. Where j
= (I−1) · k, and j = 0, k, 2k, 3k, ...
.., (m-1) .k, etc.

The operation block Bi in this example is the multiplier 61.
An adder 62, a delay element (first delay element) 63 that delays by (k + 1) operation clocks, and a selector 64.
And a register (second delay element) 65 for delaying one operation clock.

Here, the structure of the arithmetic block Bi of this example is the same as that of the register 35 as shown in FIG. 7 of the third embodiment.
Therefore, compared with the operation block Bi which delays the feedback signal and delays the cascade input signal,
The delay of the feedback signal and the delay of the cascade input signal are individually performed. Specifically, the register 65 is arranged between the adder 62 and the (i + 1) th operation block Bi + 1, which is the subsequent stage and the next stage, and the delay element 63 is used for (k + 1) operation clocks. It is configured to delay. Also in this case, the total number of delay clocks of the feedback signal is (k + 1) operation clocks and is the same as in the case of the third embodiment. For example, the selector 64 uses the cascade connection signal C (j).
The same operation as in the case of the third embodiment can be realized only by changing the timing of selecting and outputting.

With such a configuration, the transversal filter of this example can also obtain the same filtering result as the transversal filter shown in the third embodiment, and the same effect can be obtained.
Note that the register 65 does not necessarily need to use the operation clock. For example, the cascade connection signal C (j) is used.
A register 65 may be used to hold the signal in synchronism with the timing at which is output. Further, for example, when the delay element 63 is composed of a memory or the like, it is possible to carry out the calculation by setting the frequency of the calculation clock to be at least k times the frequency of the sample clock.

Next, the transversal filter according to the seventh embodiment will be described. FIG. 13 shows a configuration example of the transversal filter of this example. In this example, the filter tap coefficients are, for example, h (8), h (7), ...
h (2), h (1), h (1), h (2), ..., h
An example of the configuration of a transversal filter that is effective in the case of left-right symmetry as in (7) and h (8) is shown. In addition, this example shows a configuration example in the case of M = 16, k = 4, and m = 4.

The transversal filter of this example is configured by cascade-connecting four operation blocks (first operation block B1 to fourth operation block B4).
The first calculation block B1 and the second calculation block B2 are
For example, the operation block Bi shown in FIG. 2 of the first embodiment.
And has a configuration similar to that of the multiplier 71.
, An adder 72, and a delay element (first delay element) 73
, Selector 74, delay element (second delay element) 75
Is equipped with.

Further, the third operation block B3 and the fourth operation block B4 have the same configuration as the operation block Bi shown in FIG. 7 of the third embodiment, for example. 3 calculation block B3 and 4th calculation block B
As the multiplier unit of No. 4, the multiplier unit 71 of the second operation block B2 or the first operation block B1 is shared. Therefore, the third calculation block B3 and the fourth calculation block B3
The operation block B4 of the adder 81 and the delay element (first
Delay element) 82, selector 83, delay element (second
Delay element) 84.

Specifically, in the multiplier 71 of the first operation block B1, the filter tap coefficients h (5) to h (8) are used.
Is multiplied. Then, in the fourth operation block B4, the same filter tap coefficients h (5) to h (8) as those in the first operation block B1 need to be multiplied. Therefore, the multiplier 71 of the first operation block B1 is required. The multiplication result output from is input to the adder 81 to perform an operation. Similarly, the second
In the multiplier 71 of the calculation block B2, the filter tap coefficients h (1) to h (4) are multiplied. Then, in the third operation block B3, the same filter tap coefficients h (1) to h (4) as those in the second operation block B2 need to be multiplied, so that the multiplier 71 of the second operation block B2 is used. The multiplication result output from is input to the adder 81 to perform an operation.

That is, in the operation block Bi shown in FIG. 2 of the first embodiment and the operation block Bi shown in FIG. 7 of the third embodiment, the filter tap coefficient is given to the multiplier. Because the order in which they are
When bilaterally symmetrical filter tap coefficients are used as in this example, the operation blocks B1 and B2 that perform the operation of the filter tap coefficients in the first half and the operation blocks B3 and B4 that perform the operation of the filter tap coefficients in the latter half are used separately. Therefore, it is possible to reduce the number of multipliers by sharing the multipliers.

For example, instead of the configuration of the operation block Bi as shown in FIG. 2 of the first embodiment, the second block is used.
It is also possible to use the configuration of the operation block Bi as shown in FIG. 6 of the third embodiment, and FIG. 7 of the third embodiment.
Instead of the configuration of the operation block Bi as shown in FIG. 10, the configuration of the operation block Bi as shown in FIG. 10 of the fourth embodiment, FIG. 11 of the fifth embodiment and FIG. 12 of the sixth embodiment is adopted. It is also possible to use.

It is also possible to use a configuration opposite to that of the present example as the first half arithmetic block and the latter half arithmetic block. In this case, the filter tap coefficients are calculated in the reverse order of this example. It may be given to the block Bi.

Here, the structure of the filter device according to the present invention is not necessarily limited to the one described above, and various structures may be used. The present invention can also be provided as, for example, a method for executing the process according to the present invention or a program for realizing such a method. Further, the application fields of the present invention are not necessarily limited to those shown above, and the present invention can be applied to various fields.

Further, as various processings performed in the filter device according to the present invention, for example, in a hardware resource including a processor and a memory,
A configuration controlled by executing a control program stored in an OM (Read Only Memory) may be used, and, for example, each functional unit for performing the processing is configured as an independent hardware circuit. May be.
Further, the present invention is a floppy (registered trademark) disk or a CD (Compact Disc) -R storing the above control program.
It can be understood as a computer-readable recording medium such as an OM or the program (itself), and the processing according to the present invention is performed by inputting the control program into the computer from the recording medium and causing the processor to execute the control program. be able to.

[0136]

As described above, according to the filter device of the present invention, the sum of the multiplication values of a plurality of time-series values of the input signal and the same number of filter tap coefficients is used as the filtering result of the input signal. In the configuration,
Some continuous filter tap coefficients are assigned to each, and the time series value of the input signal switches.In the unit time, the time series value of the input signal is multiplied by each of the assigned filter tap coefficients. The number of filter tap coefficients is the same as the number of time-series values of the input signal, and the filter device is configured from a plurality of processing units that sum up the combinations that form the filtering result. Since the value obtained by summing the summation results, which is the combination that forms the filtering result for each part, is used as the filtering result of the input signal, efficient filtering processing can be realized. Simplification and constant output timing of filtering results It can be.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of the overall configuration of a transversal filter according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a calculation block according to the first embodiment.

FIG. 3 is a diagram showing a specific configuration example of a transversal filter according to the first embodiment.

FIG. 4 is a time chart showing an example of an operation performed by the transversal filter according to the first embodiment.

FIG. 5 is a diagram illustrating another configuration example of an adder.

FIG. 6 is a diagram showing a configuration example of a calculation block according to a second embodiment.

FIG. 7 is a diagram showing a configuration example of a calculation block according to a third embodiment.

FIG. 8 is a diagram showing a specific configuration example of a transversal filter according to the third embodiment.

FIG. 9 is a time chart diagram showing an example of an operation performed by the transversal filter according to the third embodiment.

FIG. 10 is a diagram showing a configuration example of an arithmetic block according to the fourth embodiment.

FIG. 11 is a diagram showing a configuration example of an arithmetic block according to the fifth embodiment.

FIG. 12 is a diagram showing a configuration example of an arithmetic block according to the sixth embodiment.

FIG. 13 is a diagram showing a configuration example of an arithmetic block according to the seventh embodiment.

FIG. 14 is a diagram showing a configuration example of a transversal filter according to a conventional example.

[Explanation of symbols]

B1 to Bm ... Operation block, 1, 21, 31, 41, 51, 61, 71 ... Multiplier, 2, 11, 22, 32, 42, 52, 62, 72, 81
..Adders, 3, 5, 6, 23, 25, 33, 44, 53, 63, 7
3, 75, 82 ... delay element, 4, 24, 34, 45, 55, 64, 74, 83 ... selector, 12 ... addition function, 13 ... delay function, 43, 54, 65, 84 ... register,

Claims (3)

[Claims] 1. A filter device using a sum of multiplication values of a plurality of time-series values of an input signal and the same number of filter tap coefficients as a filtering result of the input signal. When the coefficient is assigned and the time series value of the input signal switches, the time series value of the input signal is multiplied by each of all the assigned filter tap coefficients within the unit time, and the same number as the number of assigned filter tap coefficients The result of multiplication of the time-series values of the input signal is composed of a plurality of processing units that sum up the combinations that form the filtering result, and the summation result that forms the combination that forms the filtering result of these plurality of processing units. The filter device is characterized in that the sum of the values is used as the filtering result of the input signal. 2. The filter device according to claim 1, wherein M time-series values x (n) to x (n-M + 1) of the input signal.
And M filter tap coefficients h (1) to h (M) respectively multiplied values {h (1) · x (n)} to {h (M) ·
x (n-M + 1)} is used as a filtering result of the input signal, and k consecutive filter tap coefficients h (M
-Ik + 1) to h (Mik + k) are assigned and operated by the processing unit clock that switches k times within the unit time when the time series value of the input signal switches m = (M /
k) processing units, and each processing unit has a filter tap coefficient h (M−i · k + 1) with a minimum degree z of the filter tap coefficient h (z).
To the maximum filter tap coefficient h (M−i · k + k) in order from the input signal time series values and the assigned filter tap coefficients h (M−i · k + 1) to h (M−i · k +).
k), and (k-1) time-series values of the input signal as many as the number of assigned filter tap coefficients by sequentially adding the multiplication results obtained at each processing unit clock time. The summation of the multiplication results for the combinations of the filtering results is performed, and in the m processing units, the summation result obtained by the processing units in the second and subsequent stages is (2k− 1) After the time corresponding to the processing unit clocks, the summation results that are the combinations forming the filtering result for these m processing units are summed up by being added to the multiplication results obtained in the second and subsequent processing units. A filter device, wherein a value is obtained as a filtering result of an input signal. 3. The filter device according to claim 1, wherein the M time-series values x (n) to x (n-M + 1) of the input signal.
And M filter tap coefficients h (1) to h (M) respectively multiplied values {h (1) · x (n)} to {h (M) ·
x (n-M + 1)} is used as a filtering result of the input signal, and k consecutive filter tap coefficients h (M
-I · k + k) to h (M−i · k + 1) are assigned and operated by a processing unit clock that switches k times within a unit time when the time series value of the input signal switches m = (M /
k) number of processing units, and each processing unit has a filter tap coefficient h (M−i · k + k) with a maximum degree z of the filter tap coefficient h (z).
To the smallest filter tap coefficient h (M−i · k + 1) and the time series values of the input signal and the assigned filter tap coefficients h (M−i · k + k) to h (M−i · k +).
By multiplying each of 1) and sequentially adding the multiplication results obtained every time of (k + 1) processing unit clocks, the number of filter tap coefficients assigned is the same as the number of input signal time series values. The sums of the multiplication results that are the combinations that form the filtering result are summed, and in the m processing units, the summation result obtained by the processing units of the second and subsequent processing units corresponds to one processing unit clock. Is added to the multiplication results obtained by the processing units of the second and subsequent stages after the time of, the summation value of the summation results forming the filtering result for these m processing units is added to the input signal for filtering. A filter device, which is obtained as a result.