JP2003332525A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2003332525A JP2003332525A JP2002134392A JP2002134392A JP2003332525A JP 2003332525 A JP2003332525 A JP 2003332525A JP 2002134392 A JP2002134392 A JP 2002134392A JP 2002134392 A JP2002134392 A JP 2002134392A JP 2003332525 A JP2003332525 A JP 2003332525A
- Authority
- JP
- Japan
- Prior art keywords
- external connection
- plug
- semiconductor device
- short
- semiconductor elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Power Conversion In General (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、スイッチング素子
としてモータ制御等に使用される半導体素子を備えた電
力用半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device having a semiconductor element used as a switching element for motor control or the like.
【０００２】[0002]
【従来の技術】図１２は従来の電力用半導体装置を示し
ており、絶縁基板（セラミックス基板）５２の表主面に
複数のＣｕパターン電極５４が形成されている。Ｃｕパ
ターン電極５４の一つに接合された半導体素子５６はＡ
ｌワイヤ５８を介して他のＣｕパターン電極５４に接続
されており、各Ｃｕパターン電極５４には、コレクタ端
子６０、ゲート端子６２あるいはエミッタ端子６４がそ
れぞれ接続されている。2. Description of the Related Art FIG. 12 shows a conventional power semiconductor device, in which a plurality of Cu pattern electrodes 54 are formed on a front main surface of an insulating substrate (ceramic substrate) 52. The semiconductor element 56 bonded to one of the Cu pattern electrodes 54 is A
It is connected to another Cu pattern electrode 54 via the 1-wire 58, and a collector terminal 60, a gate terminal 62 or an emitter terminal 64 is connected to each Cu pattern electrode 54.
【０００３】また、図１３は、複数の半導体素子５６が
並列接続された従来の電力用半導体装置を示しており、
素子間がＡｌワイヤ５８により接続されている。FIG. 13 shows a conventional power semiconductor device in which a plurality of semiconductor elements 56 are connected in parallel.
The elements are connected by an Al wire 58.
【０００４】[0004]
【発明が解決しようとする課題】図１２の構成の電力用
半導体装置にあっては、ゲート端子６２及びエミッタ端
子６４間がオープン状態のため、製造時の静電気、過電
圧等によるＭＯＳ系半導体素子の絶縁ゲート破壊を招く
という問題があった。In the power semiconductor device having the structure shown in FIG. 12, since the gate terminal 62 and the emitter terminal 64 are in an open state, the MOS semiconductor device is not manufactured due to static electricity, overvoltage or the like during manufacturing. There was a problem of causing the breakdown of the insulated gate.
【０００５】この問題に鑑み、特開平１−２６８１６０
号公報、特開平８−３２０２２号公報あるいは実開平７
−２９８５４号公報には、静電気による絶縁ゲート破壊
を防止するようにしたパワーモジュール、コネクタある
いはＩＧＢＴが開示されているが、取り扱いが容易で、
複数の半導体素子を並列接続した電力用半導体装置にお
いても簡素な構成で絶縁ゲート破壊を防止できる構造の
ものはなかった。In view of this problem, Japanese Patent Laid-Open No. 1-268160
Japanese Patent Laid-Open Publication No. 8-32022 or Japanese Utility Model Publication No.
No. 29854 discloses a power module, a connector or an IGBT which is designed to prevent the breakdown of an insulated gate due to static electricity, but it is easy to handle,
Even in a power semiconductor device in which a plurality of semiconductor elements are connected in parallel, there is no structure that can prevent the breakdown of the insulated gate with a simple structure.
【０００６】また、図１３の構成の電力用半導体装置に
あっては、素子間がＡｌワイヤ５８により接続されてい
るため、複数の半導体素子５６の個別の特性検査ができ
ず、複数の半導体素子５６のいずれかが破壊した場合で
も、その検出は容易ではなかった。Further, in the power semiconductor device having the structure shown in FIG. 13, since the elements are connected by the Al wires 58, it is not possible to individually inspect the characteristics of the plurality of semiconductor elements 56, and the plurality of semiconductor elements are not able to be inspected. If any of the 56 broke, its detection was not easy.
【０００７】本発明は、従来技術の有するこのような問
題点に鑑みてなされたものであり、並列接続された複数
の半導体素子を有する電力用半導体装置において、簡素
な構成で、半導体素子の並列接続と絶縁ゲート破壊の防
止を達成できるとともに、破壊された素子を容易に検出
することができ、ゲート抵抗のバランス取りを容易に行
うことのできる電力用半導体装置を提供することを目的
としている。The present invention has been made in view of the above problems of the prior art. In a power semiconductor device having a plurality of semiconductor elements connected in parallel, the semiconductor elements are arranged in parallel with a simple structure. An object of the present invention is to provide a power semiconductor device which can achieve connection and insulation gate breakdown prevention, can easily detect a destroyed element, and can easily balance gate resistance.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するため
に、本発明のうちで請求項１に記載の発明は、ケース内
に収納された電力用絶縁基板の表主面上に形成された主
回路パターン上に複数の絶縁ゲート型スイッチング半導
体素子を実装して並列に接続する電力用半導体装置にお
いて、前記複数の絶縁ゲート型スイッチング半導体素子
の各々のゲート駆動回路をそれぞれ短絡する複数のソケ
ットと、該複数のソケットに挿入され短絡を解除すると
同時に、前記複数の絶縁ゲート型スイッチング半導体素
子を並列に接続するプラグ式外部接続部材とを備えたこ
とを特徴とする。In order to achieve the above object, the invention according to claim 1 of the present invention is formed on the front main surface of an insulating substrate for electric power housed in a case. In a power semiconductor device in which a plurality of insulated gate type switching semiconductor elements are mounted on a main circuit pattern and connected in parallel, a plurality of sockets for short-circuiting the gate drive circuits of the plurality of insulated gate type switching semiconductor elements, respectively. And a plug-type external connection member that is inserted into the plurality of sockets to release the short circuit and at the same time connects the plurality of insulated gate type switching semiconductor elements in parallel.
【０００９】また、請求項２に記載の発明は、前記プラ
グ式外部接続部材を、絶縁性支持体と、該絶縁性支持体
と一体成形された二つの外部接続用端子とにより形成
し、前記絶縁性支持体に複数の短絡解除片を形成すると
ともに、該複数の短絡解除片の各々の両側に前記二つの
外部接続用端子の分岐端を配置したことを特徴とする。According to a second aspect of the present invention, the plug-type external connection member is formed by an insulating support and two external connection terminals integrally formed with the insulating support. A plurality of short-circuit release pieces are formed on the insulating support, and branch ends of the two external connection terminals are arranged on both sides of each of the plurality of short-circuit release pieces.
【００１０】さらに、請求項３に記載の発明は、前記プ
ラグ式外部接続部材の外部接続用端子を支持する絶縁性
支持体内に凹部を形成し、前記外部接続用端子を前記凹
部内に突出させたことを特徴とする。Further, the invention according to claim 3 is characterized in that a recess is formed in an insulating support for supporting the external connection terminal of the plug-type external connection member, and the external connection terminal is projected into the recess. It is characterized by that.
【００１１】また、請求項４に記載の発明は、ケース内
に収納された電力用絶縁基板の表主面上に形成された主
回路パターン上に複数の絶縁ゲート型スイッチング半導
体素子を実装して並列に接続する電力用半導体装置にお
いて、前記複数の絶縁ゲート型スイッチング半導体素子
の各々のゲート駆動回路をそれぞれ短絡する複数のソケ
ットと、該複数のソケットに挿入され短絡を個々に解除
すると同時に、前記複数の絶縁ゲート型スイッチング半
導体素子を個々に外部接続可能とするプラグ式外部接続
部材とを備えたことを特徴とする。According to a fourth aspect of the present invention, a plurality of insulated gate type switching semiconductor elements are mounted on a main circuit pattern formed on the front main surface of the power insulating substrate housed in the case. In a power semiconductor device connected in parallel, a plurality of sockets respectively short-circuiting the gate drive circuit of each of the plurality of insulated gate switching semiconductor elements, and at the same time to individually release the short circuit inserted into the plurality of sockets, at the same time, And a plug-type external connection member capable of individually externally connecting a plurality of insulated gate switching semiconductor elements.
【００１２】また、請求項５に記載の発明は、前記プラ
グ式外部接続部材を、絶縁性支持体と、該絶縁性支持体
と一体成形された複数対の外部接続用端子とにより形成
し、前記絶縁性支持体に複数の短絡解除片を形成すると
ともに、該複数の短絡解除片の各々の両側に前記複数対
の外部接続用端子のうちの一対をそれぞれ配置したこと
を特徴とする。According to a fifth aspect of the present invention, the plug-type external connection member is formed of an insulating support and a plurality of pairs of external connection terminals integrally formed with the insulating support, A plurality of short-circuit release pieces are formed on the insulating support, and a pair of the plurality of pairs of external connection terminals is arranged on both sides of each of the plurality of short-circuit release pieces.
【００１３】また、請求項６に記載の発明は、前記プラ
グ式外部接続部材に、前記絶縁ゲート型スイッチング半
導体素子の各々のゲート駆動回路に接続される抵抗体を
装着できるようにしたことを特徴とする。According to a sixth aspect of the present invention, the plug-type external connection member can be equipped with a resistor connected to a gate drive circuit of each of the insulated gate type switching semiconductor elements. And
【００１４】[0014]
【発明の実施の形態】以下、本発明の実施の形態につい
て、図面を参照しながら説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.
【００１５】実施の形態１．図１は、本発明の実施の形
態１にかかる電力用半導体装置を示しており、ケース
（図示せず）内に収納された電力用絶縁基板（セラミッ
クス基板）２の表主面上に主回路パターン（例えば、Ｃ
ｕパターン）による複数の電極４が形成されている。ま
た、主回路パターンに実装される絶縁ゲート型スイッチ
ング半導体素子等の半導体素子６は、複数の電極４の一
つに接合されるとともに、Ａｌワイヤ８を介して他の電
極４に接続されており、各電極４には、コレクタ端子１
０、ゲート端子１２あるいはエミッタ端子１４がそれぞ
れ接続されている。Embodiment 1. First Embodiment FIG. 1 shows a power semiconductor device according to a first embodiment of the present invention, in which a main circuit is provided on a front main surface of a power insulating substrate (ceramic substrate) 2 housed in a case (not shown). Pattern (eg C
A plurality of electrodes 4 having a u pattern) are formed. A semiconductor element 6 such as an insulated gate switching semiconductor element mounted on the main circuit pattern is bonded to one of the plurality of electrodes 4 and is connected to another electrode 4 via an Al wire 8. , Each electrode 4 has a collector terminal 1
0, the gate terminal 12 or the emitter terminal 14 are connected to each other.
【００１６】図２に示されるように、ゲート端子１２あ
るいはエミッタ端子１４が接続された二つの電極４には
ソケット１６が取り付けられており、ソケット１６は、
内部に凹部１８ａが形成された樹脂製の絶縁性支持体１
８と、絶縁性支持体１８と一体成形された隣接する二つ
の電極２０とを備えている。各電極２０は中間部で折曲
され、その先端は円弧状に形成される一方、その基端は
電極４にはんだ付けにより接合されている。製造時に
は、二つの電極２０の先端部は、円弧状形状により弾性
のある状態で互いに当接しており、静電気、過電圧等に
より絶縁ゲート破壊が発生する虞はない。As shown in FIG. 2, a socket 16 is attached to the two electrodes 4 to which the gate terminal 12 or the emitter terminal 14 is connected.
A resin-made insulating support 1 having a recess 18a formed therein
8 and two adjacent electrodes 20 integrally formed with the insulating support 18. Each electrode 20 is bent in the middle part, and its tip end is formed in an arc shape, while its base end is joined to the electrode 4 by soldering. At the time of manufacturing, the tips of the two electrodes 20 are in contact with each other in an elastic state due to the arc shape, and there is no possibility that the insulation gate is broken due to static electricity, overvoltage, or the like.
【００１７】一方、上述した構成の電力用半導体装置を
製造後、絶縁性材料により形成されたプラグ（短絡解除
部材）２２がソケット１６に差し込まれるが、このプラ
グ２２は、その下面中央部より下方に延びる短絡解除片
２２ａと、下面両端部より下方に延びソケット１６に係
止される係止片２２ｂとを有している。On the other hand, after the power semiconductor device having the above-described structure is manufactured, a plug (short-circuit releasing member) 22 made of an insulating material is inserted into the socket 16. The plug 22 is located below the central portion of the lower surface thereof. And a locking piece 22b that extends downward from both ends of the lower surface and is locked to the socket 16.
【００１８】電力用半導体装置の製造後、図３に示され
るように、プラグ２２の短絡解除片２２ａを、互いに当
接している二つの電極２０の先端部に差し込むと、ゲー
ト端子１２とエミッタ端子１４とが短絡状態からオープ
ン状態になり、ゲート駆動回路（図示せず）の短絡が解
除される。この時、プラグ２２の係止片２２ｂがソケッ
ト１６の絶縁性支持体１８の長手方向両端部に形成され
た係止部１８ｂに係止され、プラグ２２はソケット１６
に一体的に保持される。After the power semiconductor device is manufactured, as shown in FIG. 3, the short-circuit release piece 22a of the plug 22 is inserted into the tips of the two electrodes 20 which are in contact with each other. 14 is changed from the short-circuited state to the open state, and the short-circuiting of the gate drive circuit (not shown) is released. At this time, the locking pieces 22b of the plug 22 are locked to the locking portions 18b formed at both ends of the insulating support 18 of the socket 16 in the longitudinal direction, and the plug 22 is locked by the socket 16.
Is held integrally with the.
【００１９】実施の形態２．図４乃至図６は、本発明の
実施の形態２にかかる電力用半導体装置を示しており、
上述した実施の形態１において、電極４に接合されたゲ
ート端子１２及びエミッタ端子１４をプラグ（プラグ式
外部接続部材）２２Ａに設けた点にある。Embodiment 2. 4 to 6 show a power semiconductor device according to a second embodiment of the present invention,
In the first embodiment described above, the gate terminal 12 and the emitter terminal 14 joined to the electrode 4 are provided on the plug (plug-type external connection member) 22A.
【００２０】すなわち、図４及び図５に示されるよう
に、二つの外部接続用端子（ゲート端子及びエミッタ端
子）１２，１４は、ケース２４内に取り付けられた電極
４には設けられておらず、プラグ２２Ａに一体的に形成
されている。That is, as shown in FIGS. 4 and 5, the two external connection terminals (gate terminal and emitter terminal) 12, 14 are not provided on the electrode 4 mounted in the case 24. , 22A are integrally formed with the plug 22A.
【００２１】図６に示されるように、プラグ２２Ａは、
絶縁性支持体２６と、絶縁性支持体２６と一体成形され
互いに離間したゲート端子１２及びエミッタ端子１４と
を有するとともに、その下面中央部より下方に延びる短
絡解除片２２ａと、下面両端部より下方に延びソケット
１６に係止される係止片２２ｂとを有している。また、
ゲート端子１２及びエミッタ端子１４は、絶縁性支持体
２６の内部で折曲され、その下部は短絡解除片２２ａの
両側に配置されている。As shown in FIG. 6, the plug 22A is
It has an insulating support 26, a gate terminal 12 and an emitter terminal 14 which are integrally formed with the insulating support 26 and are spaced apart from each other, and a short-circuit release piece 22a extending downward from the central portion of the lower surface thereof and below both end portions of the lower surface. And a locking piece 22b that is locked to the socket 16 and extends. Also,
The gate terminal 12 and the emitter terminal 14 are bent inside the insulating support 26, and the lower portions thereof are arranged on both sides of the short-circuit release piece 22a.
【００２２】電力用半導体装置の製造後、図５及び図６
に示されるように、プラグ２２Ａの短絡解除片２２ａ
を、互いに当接している二つの電極２０の先端部に差し
込むと、二つの電極２０は短絡状態からオープン状態に
なるとともに、ゲート端子１２及びエミッタ端子１４は
対応する電極２０と接触する。この時、プラグ２２Ａの
係止片２２ｂがソケット１６の絶縁性支持体１８の長手
方向両端部に形成された係止部１８ｂに係止され、プラ
グ２２Ａはソケット１６に一体的に保持される。After the manufacture of the power semiconductor device, FIGS.
As shown in FIG.
Is inserted into the tips of the two electrodes 20 that are in contact with each other, the two electrodes 20 are changed from the short-circuited state to the open state, and the gate terminal 12 and the emitter terminal 14 are brought into contact with the corresponding electrodes 20. At this time, the locking pieces 22b of the plug 22A are locked to the locking portions 18b formed at both ends of the insulating support 18 of the socket 16 in the longitudinal direction, and the plug 22A is integrally held by the socket 16.
【００２３】上記構成は、従来電極４に接合されていた
端子が不要になるので、パッケージを小型化することが
できる。In the above structure, the terminal which has been conventionally joined to the electrode 4 is not required, so that the package can be downsized.
【００２４】また、図７に示されるように、プラグ２２
Ａ’に凹部２２ｃを形成し、この凹部２２ｃ内にゲート
端子１２及びエミッタ端子１４を突出させるとともに、
凹部２２ｃ内でゲート端子１２及びエミッタ端子１４を
対応するリード線２３と接続することもできる。Further, as shown in FIG. 7, the plug 22
A recess 22c is formed in A ', and the gate terminal 12 and the emitter terminal 14 are projected into the recess 22c.
It is also possible to connect the gate terminal 12 and the emitter terminal 14 to the corresponding lead wire 23 in the recess 22c.
【００２５】ソケット１６にプラグ２２Ａ’を挿入する
と半導体素子が静電破壊する虞があるが、ゲート端子１
２及びエミッタ端子１４の先端を絶縁性支持体２６の外
部に突出させないようにすることで、はんだ付け前に格
別の注意を要することなく静電破壊を防止することがで
き、取り扱い上極めて至便で、静電破壊の確率を著しく
低減できる。When the plug 22A 'is inserted into the socket 16, the semiconductor element may be electrostatically damaged.
2 and the tips of the emitter terminals 14 do not project outside the insulating support 26, electrostatic breakdown can be prevented without special precautions before soldering, and it is extremely convenient to handle. The probability of electrostatic breakdown can be significantly reduced.
【００２６】実施の形態３．図８は、本発明の実施の形
態３にかかる電力用半導体装置を示しており、隣接配置
された複数（例えば、三つ）の半導体素子６の各々は、
Ａｌワイヤ８により対応するソケット１６に個別に接続
されている。Embodiment 3. FIG. 8 shows a power semiconductor device according to a third embodiment of the present invention, in which each of a plurality (for example, three) of semiconductor elements 6 arranged adjacent to each other is
It is individually connected to the corresponding socket 16 by the Al wire 8.
【００２７】また、プラグ（プラグ式外部接続部材）２
２Ｂは、絶縁性支持体２６と、絶縁性支持体２６と一体
成形され互いに離間したゲート端子１２及びエミッタ端
子１４とを有するとともに、その下面より下方に延びる
複数の短絡解除片２２ａと、下面両端部より下方に延び
ソケット１６に係止される係止片２２ｂとを有してい
る。また、ゲート端子１２及びエミッタ端子１４は、絶
縁性支持体２６の内部で折曲され、その下部は三つに分
岐して、各分岐端はそれぞれ短絡解除片２２ａの両側に
配置されている。A plug (plug-type external connection member) 2
2B has an insulating support 26, a gate terminal 12 and an emitter terminal 14 which are integrally formed with the insulating support 26 and are separated from each other, and have a plurality of short-circuit release pieces 22a extending downward from the lower surface thereof and both end surfaces of the lower surface. And a locking piece 22b which extends downward from the portion and is locked to the socket 16. Further, the gate terminal 12 and the emitter terminal 14 are bent inside the insulating support 26, the lower part thereof branches into three parts, and the respective branch ends are arranged on both sides of the short-circuit release piece 22a.
【００２８】電力用半導体装置の製造後、プラグ２２Ｂ
の短絡解除片２２ａを、対応するソケット１６の互いに
当接している二つの電極２０の先端部に差し込むと、二
つの電極２０はすべてのソケット１６において同時に短
絡状態からオープン状態になるとともに、ゲート端子１
２及びエミッタ端子１４は対応する電極２０と接触し、
複数の半導体素子６は並列に接続される。この時、プラ
グ２２Ｂの係止片２２ｂがソケット１６の絶縁性支持体
１８の長手方向両端部に形成された係止部１８ｂに係止
され、プラグ２２Ｂはソケット１６に一体的に保持され
る。After manufacturing the power semiconductor device, the plug 22B is formed.
When the short-circuit release piece 22a is inserted into the tips of the two electrodes 20 of the corresponding socket 16 that are in contact with each other, the two electrodes 20 simultaneously change from the short-circuited state to the open state in all the sockets 16 and the gate terminals. 1
2 and the emitter terminal 14 contact the corresponding electrode 20,
The plurality of semiconductor elements 6 are connected in parallel. At this time, the locking pieces 22b of the plug 22B are locked to the locking portions 18b formed at both ends of the insulating support 18 of the socket 16 in the longitudinal direction, and the plug 22B is integrally held by the socket 16.
【００２９】図１３の従来構成は、複数の半導体素子５
６が互いにＡｌワイヤ５８により接続されており、個別
の特性検査が不可能であったが、上記構成においてはプ
ラグ２２Ｂを使用していることから、複数の半導体素子
６の各々に対し独立した特性検査を行うことができ、製
造途中の工程であっても素子交換が可能で、生産性が向
上する。The conventional configuration shown in FIG. 13 has a plurality of semiconductor elements 5.
6 are connected to each other by the Al wire 58, and individual characteristic inspection is impossible. However, since the plug 22B is used in the above configuration, independent characteristics for each of the plurality of semiconductor elements 6 are obtained. The inspection can be performed, and the element can be replaced even during the manufacturing process, and the productivity is improved.
【００３０】なお、図８に示されるプラグ２２Ｂには、
外部接続用端子としてゲート端子１２及びエミッタ端子
１４がそれぞれ一つ設けられているが、複数のソケット
１６の各々に対応してゲート端子１２及びエミッタ端子
１４をそれぞれ一つ設ける構成も考えられる。The plug 22B shown in FIG.
Although one gate terminal 12 and one emitter terminal 14 are provided as external connection terminals, a configuration in which one gate terminal 12 and one emitter terminal 14 are provided corresponding to each of the plurality of sockets 16 is also conceivable.
【００３１】この場合、並列接続されて使用される絶縁
ゲート型スイッチング半導体素子等の半導体素子のいず
れかが破壊しても、破壊した半導体素子の検出を容易に
行うことができる。In this case, even if any one of the semiconductor elements such as the insulated gate switching semiconductor elements used in parallel connection is broken, the broken semiconductor element can be easily detected.
【００３２】また、図７に示される形状を図８に示され
るプラグ２２Ｂに採用し、ゲート端子１２及びエミッタ
端子１４を凹部内で対応するリード線と接続するように
してもよい。The shape shown in FIG. 7 may be adopted for the plug 22B shown in FIG. 8 so that the gate terminal 12 and the emitter terminal 14 are connected to the corresponding lead wires in the recess.
【００３３】実施の形態４．図９は、本発明の実施の形
態４にかかる電力用半導体装置に設けられるプラグアセ
ンブリ（プラグ式外部接続部材）２２Ｃを示しており、
図８に示されるプラグ２２Ｂを二つに分離し、分離した
プラグ２２Ｃ１，２２Ｃ２を互いに電気的に接続したも
のである。Fourth Embodiment FIG. 9 shows a plug assembly (plug type external connection member) 22C provided in the power semiconductor device according to the fourth embodiment of the present invention.
The plug 22B shown in FIG. 8 is divided into two, and the separated plugs 22C 1 and 22C 2 are electrically connected to each other.
【００３４】また、各プラグ２２Ｃ１，２２Ｃ２の絶縁
性支持体２６には、二つの矩形開口部２６ａが所定の間
隔で形成されており、この開口部２６ａに抵抗体２８の
両端を挿入することにより抵抗体２８はゲート端子１２
に直列に接続される。In addition, two rectangular openings 26a are formed in the insulating support 26 of each of the plugs 22C 1 and 22C 2 at predetermined intervals, and both ends of the resistor 28 are inserted into the openings 26a. As a result, the resistor 28 becomes the gate terminal 12
Are connected in series.
【００３５】この構成によれば、様々なＩＧＢＴ素子特
性に対応して開口部２６ａに挿入される抵抗体２８を適
宜選定することにより最適な内部ゲート抵抗値を設定で
きる。According to this structure, the optimum internal gate resistance value can be set by appropriately selecting the resistor 28 to be inserted into the opening 26a corresponding to various IGBT element characteristics.
【００３６】例えば、ＰＫＧとＩＩＧＢＴとの組み合わ
せにおいて、抵抗値を任意に設定することにより電流変
化率を変更でき、ＰＫＧ内部インダクタンスの影響によ
り発生するコレクタ・エミッタ間のサージ電圧を抑制す
ることが可能となる。For example, in a combination of PKG and IIGBT, it is possible to change the current change rate by arbitrarily setting the resistance value, and it is possible to suppress the surge voltage between the collector and the emitter which is generated by the influence of the PKG internal inductance. Becomes
【００３７】また、複数個の半導体素子の場合、信号か
ら一番遠い側と近い側とでは配線インダクタンスの違い
により立ち上がり電流がアンバランスとなるため、抵抗
値を任意に設定することにより配線インダクタンスを調
整することが可能となる。Further, in the case of a plurality of semiconductor elements, the rising current becomes unbalanced on the side farthest from the signal and on the side closest to the signal due to the difference in wiring inductance. Therefore, the wiring inductance can be set by arbitrarily setting the resistance value. It becomes possible to adjust.
【００３８】さらに、並列接続以外に、実施の形態２の
ような単体でも有効である。Further, besides the parallel connection, the single unit as in the second embodiment is also effective.
【００３９】実施の形態５．図１０は、本発明の実施の
形態５にかかる電力用半導体装置に設けられるプラグア
センブリ（プラグ式外部接続部材）２２Ｄを示してお
り、各プラグ２２Ｄ１，２２Ｄ２間をシールド・ツイス
ト線３０で接続したものである。シールド・ツイスト線
３０を使用することで、サージ電圧を抑制したり、誘導
ノイズから回避できる効果がある。Embodiment 5. FIG. 10 shows a plug assembly (plug-type external connection member) 22D provided in the power semiconductor device according to the fifth embodiment of the present invention, in which a shield / twist wire 30 is provided between the plugs 22D 1 and 22D 2. It is connected. The use of the shield / twisted wire 30 has the effect of suppressing the surge voltage and avoiding induced noise.
【００４０】また、各プラグ２２Ｄ１，２２Ｄ２の表面
をアルミニウム等の金属板で被覆すると、誘導ノイズか
ら効果的に回避することができる。If the surface of each of the plugs 22D 1 and 22D 2 is covered with a metal plate such as aluminum, it is possible to effectively avoid induced noise.
【００４１】実施の形態６．図１１は、本発明の実施の
形態６にかかる電力用半導体装置に設けられる電極４を
示しており、絶縁メタライズ基板２の上に接合された電
極４に、短絡用電極片４ａを一体的に形成したものであ
る。Sixth Embodiment FIG. 11 shows an electrode 4 provided in a power semiconductor device according to a sixth embodiment of the present invention, in which an electrode piece 4a for short circuit is integrally formed with the electrode 4 bonded on an insulating metallized substrate 2. It was formed.
【００４２】この構成は、図１に示されるソケット１６
の絶縁性支持体１８が不要となり、パッケージを小型化
できるとともに、部品点数が減少することで安価な電力
用半導体装置を提供することができる。This structure has the socket 16 shown in FIG.
The need for the insulating support 18 is eliminated, the package can be downsized, and the number of parts can be reduced, so that an inexpensive power semiconductor device can be provided.
【００４３】[0043]
【発明の効果】本発明は、以上説明したように構成され
ているので、以下に記載されるような効果を奏する。Since the present invention is constructed as described above, it has the following effects.
【００４４】本発明のうちで請求項１に記載の発明によ
れば、複数の絶縁ゲート型スイッチング半導体素子の各
々のゲート駆動回路をそれぞれ短絡する複数のソケット
と、これら複数のソケットに挿入され短絡を解除すると
同時に、複数の絶縁ゲート型スイッチング半導体素子を
並列に接続するプラグ式外部接続部材とを設けたので、
短絡解除の操作と半導体素子の並列接続を簡単かつ確実
に行うことができるとともに、絶縁ゲート破壊を防止す
ることができる。According to the first aspect of the present invention, a plurality of sockets respectively short-circuiting the gate drive circuits of the plurality of insulated gate switching semiconductor elements, and a short circuit inserted into the plurality of sockets are provided. At the same time, the plug-type external connection member for connecting a plurality of insulated gate switching semiconductor elements in parallel is provided.
The operation of releasing the short circuit and the parallel connection of the semiconductor elements can be easily and surely performed, and the breakdown of the insulated gate can be prevented.
【００４５】また、請求項２に記載の発明によれば、プ
ラグ式外部接続部材の絶縁性支持体に複数の短絡解除片
を形成するとともに、これら複数の短絡解除片の各々の
両側に二つの外部接続用端子の分岐端を配置したので、
簡素な構成で、半導体素子の並列接続と絶縁ゲート破壊
の防止を同時に達成できる。According to the second aspect of the invention, a plurality of short-circuit release pieces are formed on the insulating support of the plug-type external connection member, and two short-circuit release pieces are provided on both sides of each of the plurality of short-circuit release pieces. Since the branch end of the external connection terminal is arranged,
With a simple structure, it is possible to simultaneously achieve parallel connection of semiconductor elements and prevention of breakdown of the insulated gate.
【００４６】さらに、請求項３に記載の発明によれば、
プラグ式外部接続部材の外部接続用端子を支持する絶縁
性支持体内に凹部を形成し、外部接続用端子を凹部内に
突出させたので、複数の半導体素子をプラグ式外部接続
部材で並列接続する時あるいは並列接続した後も、半導
体素子の静電破壊を防止することができ、取り扱いに格
別な注意を払う必要がなく、取り扱いの容易な電力用半
導体装置を提供することができる。Further, according to the invention of claim 3,
Since the recess is formed in the insulating support body that supports the external connection terminal of the plug-type external connection member and the external connection terminal is projected into the recess, a plurality of semiconductor elements are connected in parallel by the plug-type external connection member. It is possible to prevent electrostatic breakdown of the semiconductor element even at the time or after the parallel connection, and it is possible to provide a power semiconductor device which is easy to handle without requiring special care in handling.
【００４７】また、請求項４に記載の発明によれば、記
複数の絶縁ゲート型スイッチング半導体素子の各々のゲ
ート駆動回路をそれぞれ短絡する複数のソケットと、こ
れら複数のソケットに挿入され短絡を個々に解除すると
同時に、複数の絶縁ゲート型スイッチング半導体素子を
個々に外部接続可能とするプラグ式外部接続部材とを設
けたので、短絡解除を簡単かつ確実に行うことができる
とともに、絶縁ゲート破壊を防止することができる。ま
た、並列接続されて使用される絶縁ゲート型スイッチン
グ素子のいずれかが破壊した場合の検出を容易に行うこ
とができる。Further, according to the invention described in claim 4, a plurality of sockets respectively short-circuiting the gate drive circuits of the plurality of insulated gate type switching semiconductor elements, and short-circuits which are respectively inserted into the plurality of sockets are provided. Since a plug-type external connection member that enables external connection of multiple insulated gate switching semiconductor devices individually is provided at the same time, the short circuit can be released easily and reliably and the insulation gate is prevented from being destroyed. can do. Further, it is possible to easily detect when any one of the insulated gate switching elements used in parallel connection is broken.
【００４８】また、請求項５に記載の発明によれば、プ
ラグ式外部接続部材の絶縁性支持体に複数の短絡解除片
を形成するとともに、短絡解除片の各々の両側に複数対
の外部接続用端子のうちの一対をそれぞれ配置したの
で、簡素な構成で、絶縁ゲート破壊を防止することがで
きる。According to the invention of claim 5, a plurality of short-circuit release pieces are formed on the insulating support of the plug-type external connection member, and a plurality of pairs of external connections are provided on both sides of each short-circuit release piece. Since the pair of terminals for use are respectively arranged, it is possible to prevent the breakdown of the insulated gate with a simple configuration.
【００４９】また、請求項６に記載の発明によれば、プ
ラグ式外部接続部材に、絶縁ゲート型スイッチング半導
体素子の各々のゲート駆動回路に接続される抵抗体を装
着できるようにしたので、並列接続される複数の絶縁ゲ
ート型スイッチング素子のゲート抵抗のバランス化を容
易に行うことができる。According to the invention described in claim 6, since the plug type external connecting member can be equipped with the resistors connected to the respective gate drive circuits of the insulated gate type switching semiconductor element, the parallel type is realized. It is possible to easily balance the gate resistances of the plurality of connected insulated gate switching elements.
【図１】 本発明の実施の形態１にかかる電力用半導体
装置の斜視図である。FIG. 1 is a perspective view of a power semiconductor device according to a first embodiment of the present invention.
【図２】 図１の電力用半導体装置において、二つの電
極を有するソケットにプラグを挿入して電極の短絡を解
除する場合の動作を示すソケットとプラグの正面図であ
る。FIG. 2 is a front view of the socket and the plug showing the operation in the case of inserting the plug into the socket having two electrodes and releasing the short circuit between the electrodes in the power semiconductor device of FIG.
【図３】 ソケットにプラグをセットして電極の短絡を
解除した状態を示すソケットとプラグの正面図である。FIG. 3 is a front view of the socket and the plug showing a state where the plug is set in the socket and the short circuit of the electrodes is released.
【図４】 本発明の実施の形態２にかかる電力用半導体
装置の斜視図である。FIG. 4 is a perspective view of a power semiconductor device according to a second embodiment of the present invention.
【図５】 図４の電力用半導体装置において、二つの電
極を有するソケットにプラグをセットして電極の短絡を
解除した状態を示すソケットとプラグの斜視図である。FIG. 5 is a perspective view of the socket and the plug in the power semiconductor device of FIG. 4, showing a state in which the plug is set in the socket having two electrodes and the short circuit of the electrodes is released.
【図６】 図５のソケットとプラグの正面図である。FIG. 6 is a front view of the socket and plug of FIG.
【図７】 図５のプラグの変形例を示す部分断面正面図
である。7 is a partial cross-sectional front view showing a modified example of the plug of FIG.
【図８】 本発明の実施の形態３にかかる電力用半導体
装置の斜視図である。FIG. 8 is a perspective view of a power semiconductor device according to a third embodiment of the present invention.
【図９】 本発明の実施の形態４にかかる電力用半導体
装置に設けられるプラグアセンブリの斜視図である。FIG. 9 is a perspective view of a plug assembly provided in a power semiconductor device according to a fourth embodiment of the present invention.
【図１０】 本発明の実施の形態５にかかる電力用半導
体装置に設けられるプラグアセンブリの斜視図である。FIG. 10 is a perspective view of a plug assembly provided in a power semiconductor device according to a fifth embodiment of the present invention.
【図１１】 本発明の実施の形態６にかかる電力用半導
体装置に設けられる電極の斜視図である。FIG. 11 is a perspective view of electrodes provided in a power semiconductor device according to a sixth embodiment of the present invention.
【図１２】 従来の電力用半導体装置の斜視図である。FIG. 12 is a perspective view of a conventional power semiconductor device.
【図１３】 従来の別の電力用半導体装置の斜視図であ
る。FIG. 13 is a perspective view of another conventional power semiconductor device.
２ 絶縁基板、 ４ 電極、 ６ 半導体素子、 ８
ワイヤ、１０ コレクタ端子、 １２ ゲート端子、
１４ エミッタ端子、１６ ソケット、 １８ 絶縁性
支持体、 １８ａ 凹部、 １８ｂ 係止部、２０ 電
極、 ２２ プラグ、 ２２ａ 短絡解除片、 ２２ｂ
係止片、２２ｃ 凹部、 ２３ リード線、２２Ａ，
２２Ａ’，２２Ｂ，２２Ｃ，２２Ｄ プラグ式外部接続
部材、２４ ケース、２６ 絶縁性支持体、 ２８ 抵
抗体、３０ シールド・ツイスト線。2 insulating substrates, 4 electrodes, 6 semiconductor elements, 8
Wire, 10 collector terminal, 12 gate terminal,
14 emitter terminals, 16 sockets, 18 insulating supports, 18a recesses, 18b locking parts, 20 electrodes, 22 plugs, 22a short-circuit release pieces, 22b
Locking piece, 22c recess, 23 lead wire, 22A,
22A ′, 22B, 22C, 22D Plug type external connection member, 24 case, 26 insulating support, 28 resistor, 30 shielded twisted wire.
Claims (6)
表主面上に形成された主回路パターン上に複数の絶縁ゲ
ート型スイッチング半導体素子を実装して並列に接続す
る電力用半導体装置において、 前記複数の絶縁ゲート型スイッチング半導体素子の各々
のゲート駆動回路をそれぞれ短絡する複数のソケット
と、該複数のソケットに挿入され短絡を解除すると同時
に、前記複数の絶縁ゲート型スイッチング半導体素子を
並列に接続するプラグ式外部接続部材とを備えたことを
特徴とする電力用半導体装置。1. A power semiconductor device in which a plurality of insulated gate switching semiconductor elements are mounted on a main circuit pattern formed on a front main surface of a power insulating substrate housed in a case and connected in parallel. A plurality of sockets respectively short-circuiting the gate drive circuits of the plurality of insulated gate switching semiconductor elements, and a plurality of sockets inserted in the plurality of sockets to release the short circuit and at the same time the plurality of insulated gate switching semiconductor elements are arranged in parallel. A power semiconductor device comprising a plug-type external connection member for connection.
持体と、該絶縁性支持体と一体成形された二つの外部接
続用端子とにより形成し、前記絶縁性支持体に複数の短
絡解除片を形成するとともに、該複数の短絡解除片の各
々の両側に前記二つの外部接続用端子の分岐端を配置し
たことを特徴とする請求項１に記載の電力用半導体装
置。2. The plug-type external connection member is formed by an insulating support and two external connection terminals integrally formed with the insulating support, and a plurality of short-circuit releasing members are provided on the insulating support. 2. The power semiconductor device according to claim 1, wherein a plurality of short-circuit release pieces are formed, and branch ends of the two external connection terminals are arranged on both sides of each of the plurality of short-circuit release pieces.
端子を支持する絶縁性支持体内に凹部を形成し、前記外
部接続用端子を前記凹部内に突出させたことを特徴とす
る請求項１に記載の電力用半導体装置。3. A recess is formed in an insulating support for supporting the external connection terminal of the plug-type external connection member, and the external connection terminal is projected into the recess. The power semiconductor device according to item 1.
表主面上に形成された主回路パターン上に複数の絶縁ゲ
ート型スイッチング半導体素子を実装して並列に接続す
る電力用半導体装置において、 前記複数の絶縁ゲート型スイッチング半導体素子の各々
のゲート駆動回路をそれぞれ短絡する複数のソケット
と、該複数のソケットに挿入され短絡を個々に解除する
と同時に、前記複数の絶縁ゲート型スイッチング半導体
素子を個々に外部接続可能とするプラグ式外部接続部材
とを備えたことを特徴とする電力用半導体装置。4. A power semiconductor device in which a plurality of insulated gate switching semiconductor elements are mounted on a main circuit pattern formed on the front main surface of a power insulating substrate housed in a case and connected in parallel. A plurality of sockets respectively short-circuiting the gate drive circuits of the plurality of insulated gate switching semiconductor elements, and the plurality of insulated gate switching semiconductor elements inserted into the plurality of sockets to individually release the short circuit, A power semiconductor device, comprising: a plug-type external connection member that enables external connection individually.
持体と、該絶縁性支持体と一体成形された複数対の外部
接続用端子とにより形成し、前記絶縁性支持体に複数の
短絡解除片を形成するとともに、該複数の短絡解除片の
各々の両側に前記複数対の外部接続用端子のうちの一対
をそれぞれ配置したことを特徴とする請求項４に記載の
電力用半導体装置。5. The plug-type external connection member is formed by an insulating support and a plurality of pairs of external connection terminals integrally formed with the insulating support, and the insulating support is provided with a plurality of short circuits. The power semiconductor device according to claim 4, wherein a release piece is formed, and a pair of the plurality of pairs of external connection terminals is arranged on both sides of each of the plurality of short-circuit release pieces.
ゲート型スイッチング半導体素子の各々のゲート駆動回
路に接続される抵抗体を装着できるようにしたことを特
徴とする請求項１乃至５のいずれか１項に記載の電力用
半導体装置。6. The plug-type external connection member can be provided with a resistor connected to a gate drive circuit of each of the insulated gate type switching semiconductor elements, according to any one of claims 1 to 5. 2. The power semiconductor device according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002134392A JP3911192B2 (en) | 2002-05-09 | 2002-05-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002134392A JP3911192B2 (en) | 2002-05-09 | 2002-05-09 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003332525A true JP2003332525A (en) | 2003-11-21 |
| JP3911192B2 JP3911192B2 (en) | 2007-05-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002134392A Expired - Fee Related JP3911192B2 (en) | 2002-05-09 | 2002-05-09 | Semiconductor device |
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| Country | Link |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011108980A (en) * | 2009-11-20 | 2011-06-02 | Mitsubishi Electric Corp | Semiconductor switching device |
| JP2015026724A (en) * | 2013-07-26 | 2015-02-05 | 住友電気工業株式会社 | Semiconductor module |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10128625B2 (en) | 2014-11-18 | 2018-11-13 | General Electric Company | Bus bar and power electronic device with current shaping terminal connector and method of making a terminal connector |
-
2002
- 2002-05-09 JP JP2002134392A patent/JP3911192B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011108980A (en) * | 2009-11-20 | 2011-06-02 | Mitsubishi Electric Corp | Semiconductor switching device |
| JP2015026724A (en) * | 2013-07-26 | 2015-02-05 | 住友電気工業株式会社 | Semiconductor module |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3911192B2 (en) | 2007-05-09 |
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