JP2003332420A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device wherein irregularity of depth of a wiring trench and a connection hole is restrained, the wiring trench and the connection hole can be formed without damaging a lower layer wiring, and a stable dual damascene structure can be formed. <P>SOLUTION: An insulating film 15 for forming the connection hole, a stopper layer 16 of etching, an insulating film 17 for forming the wiring trench, and a mask layer 18 are formed on the lower layer wiring W1. Elimination by etching is performed as far as a middle point of the insulating film 15, and an aperture C turning to a pattern of the connection hole is formed. An aperture is formed on the mask layer 18 so as to become a pattern of the wiring trench, and the insulating film 17 and the insulating film 15 are eliminated by etching using the mask layer 18 as a mask, until the stopper layer 16 is exposed. The wiring trench is formed on the insulating film 17, and the connection hole reaching the lower layer wiring is formed on the insulating film 15. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a dual damascene process in which a wiring groove and a connection hole are filled with a conductive material to simultaneously form a wiring and a contact.

[0002]

2. Description of the Related Art With the progress of miniaturization of LSI, the influence of wiring resistance and wiring capacitance on the LSI performance is becoming a non-negligible value. In the wiring structure in which aluminum (Al) is used as the wiring material and silicon oxide (SiO ₂ ) is used as the interlayer insulating film, the proportion of the wiring delay in the whole is 0.18 μm.
It will increase rapidly after the mth generation.

A material having a lower dielectric constant than that of conventional silicon oxide is used as the insulating material in order to reduce the capacitance between wirings and the wiring resistance while suppressing the reduction of the space between adjacent wirings and the increase of the facing area between the wirings. An LSI using copper (Cu) as a wiring material instead of aluminum is under development. Since copper has a lower specific resistance and a higher melting point than aluminum, copper is expected to reduce wiring delay and greatly improve reliability.

To process a fine wiring pattern, a metal layer made of aluminum has been formed over the entire surface, a mask having etching resistance is covered therewith, and unnecessary metal regions are removed by etching to obtain a desired wiring structure. Had formed.

However, in the case of copper wiring, it is practically difficult to form a fine structure by dry etching. Therefore, a method of forming a wiring groove in the insulating film in advance by etching the insulating film and burying copper in the wiring groove is used. The so-called damascene method is used. In particular, the development of a dual damascene method, in which a connection hole for connecting upper and lower wirings and a wiring groove for an upper layer wiring are formed in advance and then copper is embedded in a lump, is the center of development.

As a conventional dual damascene process,
For example, there is a technique described in Japanese Patent Laid-Open No. 10-229122. The technique described in the above publication forms an interlayer insulating film on the lower layer wiring, forms a mask layer that opens in the pattern of the wiring groove for forming the upper layer wiring on the interlayer insulating film, and on the mask layer, A resist mask that opens in the pattern of connection holes is formed, the connection holes are partially formed by half-etching the interlayer insulating film using the resist mask as an etching mask, and after removing the resist mask, the mask layer is used as an etching mask. As a result, the interlayer insulating film is further etched to form a wiring groove and a connection hole reaching the lower wiring.

[0007]

However, in the conventional technique typified by the above publication, when the wiring groove is formed by etching, variations in etching depth occur in the substrate surface, and the etching depth varies later. This causes variations in the film thickness of the wiring formed in the wiring groove, which causes a problem of large variations in wiring resistance and inter-wiring capacitance.

As described above, one of the tasks for improving the performance of copper wiring using the dual damascene process is to etch deep wiring trenches and connection holes in the insulating film at a uniform depth within the substrate surface. Therefore, there is a need for a technique for keeping the film thickness of the wiring formed later uniform.

In recent years, two layers of an insulating film for forming a wiring groove and an insulating film for forming a connection hole are provided, and an etching stopper layer is inserted between the upper and lower insulating films to first remove the two insulating films. By forming a connection hole in the stopper layer and then forming a wiring groove only in the wiring formation insulating film, the wiring groove and the connection hole can be formed to the desired depth in the wiring groove formation insulating film and the connection hole formation insulating film, respectively. The technology for forming is also being developed.

However, ashing for removing the resist mask used for forming the pattern, and
Etching or the like for forming the wiring groove in the wiring groove forming insulating film may damage the wiring or the insulating film in the wiring layer in the lower layer through the connection hole formed in front of the wiring hole. This may cause a defect such as an open, a short circuit, or a defective wiring resistance value.

The present invention has been made in view of the above circumstances, and an object thereof is to suppress variations in the depths of wiring trenches and connection holes and to prevent damage to lower wirings and wiring trenches and connections. It is an object of the present invention to provide a method of manufacturing a semiconductor device that can form holes and can form a stable dual damascene structure.

[0012]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming an insulating film for forming a connection hole on a lower wiring, and the insulating film for forming a connection hole. A step of forming an etching stopper layer on the top,
Forming a wiring groove forming insulating film on the stopper layer; forming a mask layer serving as an etching mask for forming the wiring groove on the wiring groove forming insulating film; A step of removing the insulating film for forming the wiring groove and the stopper layer by etching, and a part of the insulating film for forming the connecting hole by etching to form an opening to be a pattern of the connecting hole; and a wiring groove pattern So as to form an opening in the mask layer, and using the mask layer as a mask, the wiring groove forming insulating film and the connection hole forming insulating film are removed by etching until the stopper layer is exposed. Forming a wiring groove in the wiring groove forming insulating film and forming a connection hole reaching the lower layer wiring in the connecting hole forming insulating film; and removing the mask layer. It has a that step, and a step of embedding the wiring groove and the connection hole with a conductive material.

The mask layer, the insulating film for forming the wiring groove,
In the step of forming an opening to be a pattern of a connection hole in the stopper layer and the connection hole forming insulating film, the remaining thickness of the connection hole forming insulating film is thinner than the thickness of the wiring groove forming insulating film. To remove.

The mask layer, the insulating film for forming the wiring groove,
The step of forming an opening serving as a pattern of the connection hole in the stopper layer and the insulating film for forming the connection hole includes a step of forming a first resist mask having an opening in the pattern of the connection hole on the mask layer; Using the first resist mask as an etching mask, the mask layer, the wiring groove forming insulating film, and the stopper layer are removed by etching, and the connection hole forming insulating film is partially removed by etching; And a step of removing the first resist mask.

The step of forming an opening in the mask layer so as to have the pattern of the wiring groove includes a step of forming a second resist mask having an opening in the pattern of the wiring groove on the mask layer, and the second resist. Using the mask as an etching mask, the mask layer is removed by etching,
The method has a step of forming the opening to be a pattern of the wiring groove in the mask layer, and a step of removing the second resist mask.

In the step of filling the wiring groove and the connection hole with a conductive material, a step of depositing a conductive material on the wiring groove forming insulating film so as to fill the wiring groove and the connection hole; And removing the conductive material deposited on the wiring groove forming insulating film by polishing while leaving the conductive material buried in the connection hole.

In the step of filling the wiring groove and the connection hole with a conductive material, a conductive material containing copper is embedded.

Before the step of depositing a conductive material on the wiring groove forming insulating film, the inner wall surfaces of the wiring groove and the connection hole are covered to diffuse copper on the wiring groove forming insulating film. The method further comprises the step of forming a barrier film to prevent the conductive material from being deposited in the step of depositing the conductive material, the conductive material containing copper being deposited on the barrier film so as to fill the wiring groove and the connection hole. In the step of removing the material by polishing, the barrier film and the conductive material deposited on the insulating film for forming the wiring groove are removed while leaving the barrier film and the conductive material buried in the wiring groove and the connection hole. Remove by polishing.

In the above-described method for manufacturing a semiconductor device of the present invention, since the etching stopper layer is formed between the wiring groove forming insulating film and the connection hole forming insulating film, the wiring groove is formed using the mask layer as a mask. When the formation insulating film is removed by etching to form the wiring groove, the etching is stopped by the stopper layer, so that variations in the depth of the wiring groove due to variations in etching are prevented. In addition, an opening that serves as a pattern of the connection hole is formed up to the middle of the connection hole forming insulating film, and a part of the connection hole forming insulating film on the lower layer wiring is left. Since the connection hole is formed so as to reach the lower layer wiring, the lower layer wiring is not exposed until the wiring groove is formed, and the influence on the lower layer wiring is reduced.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing an example of a semiconductor device having a dual damascene structure manufactured by the method for manufacturing a semiconductor device according to this embodiment. A first insulating film 11 made of, for example, silicon oxide is formed on a semiconductor substrate 10 on which MOS transistors and other semiconductor elements are formed, and an opening reaching the semiconductor substrate 10 is formed in the first insulating film 11. And Ta, Ti, TaN, TiN that covers the inner wall surface of the opening to prevent the diffusion of copper.
A barrier metal 12 made of, for example, is formed, and a conductive layer 13 made of, for example, copper is embedded in the barrier metal 12, and the first insulating film 11 is formed.
The barrier metal 12 and the conductive layer 13 embedded in the first layer wiring W1 which is a lower layer wiring is formed. Although not shown, the first layer wiring W1 is connected to a semiconductor element or the like formed on the semiconductor substrate via a first layer contact.

On the first insulating film 11 and the first layer wiring W1, a copper diffusion preventing film 14 made of, for example, silicon nitride or the like is formed.
Is formed, a connection hole forming insulating film 15 made of, for example, silicon oxide is formed on the diffusion preventing film 14, and an etching stopper film 16 made of silicon nitride is formed on the connecting hole forming insulating film 15. A wiring groove forming insulating film 17 made of silicon oxide is formed on the etching stopper film 16.

A wiring groove 17a is formed in the wiring groove forming insulating film 17 and the etching stopper film 16, and further penetrates the connection hole forming insulating film 15 and the diffusion preventing film 14 to form the first layer. A connection hole 15a exposing the upper surface of the wiring W1 is formed so as to communicate with the wiring groove 17a.

Connecting hole 15a and wiring groove 17a communicating with each other
Coating the inner wall surface of, for example, T to prevent the diffusion of copper
Barrier metal 19 made of a, Ti, TaN, TiN, etc.
Is formed, and a conductive layer 20 made of, for example, copper is embedded therein. The barrier metal 19 and the conductive layer 20 embedded in the wiring groove 17a form a second layer wiring W2, and the barrier metal 19 and the conductive layer 20 embedded in the connection hole 15a form a second layer contact C2. There is. In the above structure, the second layer wiring W2 is connected to the first layer wiring W1 which is the lower layer wiring via the second layer contact C2.

Next, a method of manufacturing the semiconductor device having the above structure will be described with reference to FIGS.

First, the steps up to FIG. 2A will be described. On a semiconductor substrate 10 in which MOS transistors and other semiconductor elements are formed and contacts (not shown) are embedded in an insulating film, for example, CVD (Ch
A first insulating film 11 is formed by depositing silicon oxide by an emical vapor deposition method or the like. Then, the first
An opening for embedding a wiring is formed in the insulating film 11, a material such as Ta, Ti, TaN, TiN is formed in the opening to form a barrier metal 12, and a conductive layer 13 made of copper is further formed. The excess barrier metal 12 and the conductive layer 13 formed on the first insulating film 11 are deposited by CMP (Chemical Mecha
2A, a first layer wiring W1 made of a conductive layer 13 and a barrier metal 12 embedded in the first insulating film 11 is formed by removing and planarizing by a nical polishing method. .

Next, as shown in FIG. 2B, a diffusion prevention film for preventing the diffusion of copper by depositing silicon nitride on the first insulating film 11 and the first layer wiring W1 by, for example, the CVD method. 14 is formed, and further, silicon oxide is deposited on the diffusion prevention film 14 by, for example, the CVD method to form the insulating film 15 for forming a connection hole. At this time, the total thickness of the connection hole forming insulating film 15 and the diffusion preventing film 14 is formed to be the height of the contact to be formed later.

Next, as shown in FIG. 3C, an etching stopper film 16 is formed on the insulating film 15 for forming a contact hole by depositing silicon nitride by, for example, a CVD method, and further, for example, on the insulating stopper film 16. A silicon oxide film is deposited by the CVD method to form the wiring groove forming insulating film 17, and a silicon nitride film is further deposited thereon by, for example, the CVD method to form a mask layer 18. At this time, the total film thickness of the wiring groove forming insulating film 17 and the etching stopper film 16 is formed so as to be the wiring film thickness to be formed later.

Next, as shown in FIG. 3D, a resist is applied on the mask layer 18, and a resist mask R1 having a pattern of connection holes is formed on the mask layer 18 by patterning, for example, by a photolithography process. To do.

Next, as shown in FIG. 4E, etching such as RIE is performed using the resist mask R1 as an etching mask to form the mask layer 18 and the wiring groove forming insulating film 1.
7 and the etching stopper film 16 are sequentially patterned to form an opening C having a pattern of connection holes in the mask layer 18, the wiring groove forming insulating film 17, and the etching stopper film 16. At this time, the etching conditions for etching the mask layer 18 made of silicon nitride, the wiring groove forming insulating film 17 made of silicon oxide, and the etching stopper film 16 are changed.

Next, as shown in FIG. 4F, the opening C is opened by half-etching the connection hole forming insulating film 15 by RIE or the like using the resist mask R1 as a mask. Is formed by stretching halfway. At this time, the remaining thickness t1 below the opening C in the connection hole forming insulating film 15 is a film thickness to be etched during the subsequent etching of the wiring groove, that is, the wiring groove forming insulating film 1.
It is made thinner than the film thickness t2 of 7. This is because if the remaining thickness t1 is larger than the film thickness t2 of the wiring forming insulating film 17, the connection hole reaching the lower layer is not formed during etching for forming the wiring groove.

Next, as shown in FIG. 5G, the resist mask R1 having an opening in the pattern of the connection holes is removed.

Next, as shown in FIG. 5 (h), a resist is applied again on the mask layer 18, and a resist mask R2 for opening a wiring groove pattern is formed on the mask layer 18 by, for example, a photolithography process. Patterning is formed.

Next, as shown in FIG. 6 (i), the mask layer 18 made of silicon nitride is etched using the resist mask R2 as an etching mask to form openings 18a of the wiring groove pattern in the mask layer 18. To do.

Next, as shown in FIG. 6J, the resist mask R2 having an opening in the wiring groove pattern is removed.

Next, as shown in FIG. 7K, the wiring groove forming insulating film 17 and the connection hole forming insulating film 15 are etched using the mask layer 18 having the openings 18a in the wiring groove pattern as an etching mask. By doing so, the wiring groove 17a 'is formed in the wiring groove forming insulating film 17, and the connection hole 15a' which is connected to the bottom of the wiring groove 17a 'and exposes the diffusion prevention film 14 is formed. At this time, the connection hole forming insulating film 15 and the wiring groove forming insulating film 17 made of silicon oxide can be selectively removed by etching from the etching stopper film 16 and the diffusion preventing film 14 made of silicon nitride. By performing the etching under the conditions, the etching stopper film 16 and the diffusion prevention film 14 function as an etching stopper and are prevented from being etched more than necessary.

Next, as shown in FIG. 7L, the wiring groove 1
The etching stopper film 16 made of silicon nitride exposed in 7a ′ and the diffusion prevention film 14 made of silicon nitride exposed in the connection hole 15a ′ are removed by etching to connect to the bottom of the wiring groove 17a to form the first layer. The connection hole 15a exposing the wiring W1 is formed. At this time, the mask layer 18 made of silicon nitride is also removed at the same time.

Next, as shown in FIG. 8 (m), the connection hole 1
5a and the inner wall surface of the wiring groove 17a are covered, for example, Ta, Ti, TaN, TiN for preventing diffusion of copper.
The barrier metal 19 is formed by depositing such materials as a sputtering method.

Next, as shown in FIG. 8N, for example, copper is formed on the barrier metal 19 by sputtering, CVD, or plating until the insides of the connection holes 15a and the wiring grooves 17a are filled. A conductive layer 20 is deposited. When the conductive layer 20 is deposited by electrolytic plating, the conductive layer 20 is formed by the sputtering method.
This is performed after forming a seed film (not shown) with the same material as the above.

In the subsequent steps, the excess conductive layer 20 and the barrier metal 19 on the wiring groove forming insulating film 17 are removed by C.
By removing and planarizing by the MP method and leaving the conductive layer 20 and the barrier metal 19 only in the connection hole 15a and the wiring groove 17a, a second layer formed of the barrier metal 19 and the conductive layer 20 embedded in the wiring groove 17a is formed. Barrier metal 1 in which the layer wiring W2 is formed and embedded in the connection hole 15a
A second layer contact C2 consisting of 9 and the conductive layer 20 is formed.

When forming the third and subsequent wiring layers, the multilayer wiring is formed by repeating the steps of FIGS. 2 (b) to 8 (n). As described above, the semiconductor device having the dual damascene structure shown in FIG. 1 is manufactured.

According to the method of manufacturing a semiconductor device of the present embodiment described above, since the etching stopper film 16 is provided between the wiring groove forming insulating film 17 and the connection hole forming insulating film 15, the wiring groove is formed. It is possible to prevent the formation insulating film 17 from being etched more than necessary, and to suppress the variation in the depth of the wiring groove 17a in the surface of the substrate. Therefore, the film thickness of the wiring to be formed later can be made uniform. It is possible to improve the sex.

Further, before forming the wiring trench, the connection hole is not formed so as to penetrate the connection hole forming insulating film 15, and
As shown in (f), since the connection hole forming insulating film 15 is half-etched to leave the film thickness t1, only the lower layer wiring which is the lower layer wiring is removed when the resist masks R1 and R2 are removed by ashing or the like thereafter. It is possible to prevent the layer wiring W1 from being damaged, and it is possible to prevent the wiring from being opened, shorted, or having a defective wiring resistance value.

As described above, the remaining thickness t1 of the insulating film 15 for forming a contact hole after half-etching is determined by the following wiring groove 1
It is necessary to form the film thickness to be etched when forming 7a, that is, the film thickness t2 of the wiring groove forming insulating film 17, but on the connecting hole forming insulating film 15, etching of different film types is performed. Since the stopper film 16 is present, as shown in FIG. 4E, the etching stopper film 16 is sequentially removed by etching, and then the insulating film 15 for forming a contact hole made of silicon oxide shown in FIG. 4F is formed. It is sufficient to control only the half etching, and the remaining film thickness t1 can be easily controlled.

As described above, according to the method of manufacturing the semiconductor device of this embodiment, the variation in the depth of the wiring groove and the connection hole is suppressed, and the wiring groove and the connection are not damaged to the lower wiring. Holes can be formed and a stable dual damascene structure can be formed.

The method of manufacturing the semiconductor device of the present invention is not limited to the above description of the embodiment. For example, in the present embodiment, an example in which silicon oxide is used for the connection hole forming insulating film 15 and the wiring groove forming insulating film 17 has been described, but the present invention is not limited to this, and the dielectric constant is 3.0 or less. It is also possible to use a low dielectric constant material such as xerogel.

Further, although the example in which the silicon nitride film is used as the mask layer 18 has been described, a film capable of suppressing reflection from the lower layer may be used as necessary when forming a fine pattern.

In the present embodiment, the barrier metal 1
Although an example of the materials 2 and 19 has been described, the material is not limited to this, and various materials having a function as a barrier metal can be used, and the conductive layers 13 and 20 can be used.
It is also possible to use a material other than copper.

Further, in this embodiment, the diffusion prevention film 14 made of an insulating film for preventing the diffusion of copper is inserted between the wiring layers, and the diffusion prevention film 14 is also used as a stopper layer for etching when the connection hole 15a is formed. Although the dual-purpose example has been described, only the exposed surface of copper may be selectively electroless-plated with a material such as CoWP to form a barrier metal that prevents diffusion of copper. Besides, various modifications can be made without departing from the scope of the present invention.

[0050]

According to the method of manufacturing a semiconductor device of the present invention, variations in the depths of wiring trenches and connection holes are suppressed, and
A wiring groove and a connection hole can be formed without damaging the lower layer wiring, and a stable dual damascene structure can be formed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an example of a semiconductor device having a dual damascene structure manufactured by a method of manufacturing a semiconductor device according to this embodiment.

FIG. 2 is a plan view of a semiconductor device manufacturing method according to the present embodiment.
It is sectional drawing after formation of the insulating film for connection hole formation.

FIG. 3 is a diagram illustrating a method of manufacturing a semiconductor device according to the present embodiment.
FIG. 6 is a cross-sectional view after forming a resist mask having a pattern of connection holes on the mask layer.

FIG. 4 is a plan view of the semiconductor device manufacturing method according to the present embodiment.
It is sectional drawing after the half etching of the insulating film for connection hole formation.

FIG. 5 is a view showing manufacturing of the semiconductor device according to the present embodiment.
FIG. 6 is a cross-sectional view after forming a resist mask having openings in a wiring groove pattern on a mask layer.

FIG. 6 is a view showing manufacturing of the semiconductor device according to the present embodiment.
FIG. 6 is a cross-sectional view after forming an opening of a wiring groove pattern in a mask layer.

FIG. 7 is a view showing manufacturing of the semiconductor device according to the present embodiment.
It is sectional drawing after the formation of a wiring groove and a connection hole.

FIG. 8 is a view showing a method of manufacturing the semiconductor device according to the present embodiment.
FIG. 6 is a cross-sectional view after depositing a barrier metal and a conductive layer on a wiring groove and a connection hole.

[Explanation of symbols]

10 ... Semiconductor substrate, 11 ... First insulating film, 12 ... Barrier metal, 13 ... Conductive layer, 14 ... Diffusion preventive film, 15 ... Connection hole forming insulating film, 15a, 15a '... Connection hole, 16 ... Etching stopper film , 17 ... Insulating film for forming wiring groove, 17
a, 17a '... Wiring groove, 18 ... Mask layer, 18a ... Opening, 19 ... Barrier metal, 20 ... Conductive layer, W1 ... First layer wiring, W2 ... Second layer wiring, C2 ... Second layer contact, R
1, R2 ... Resist mask, t1 ... Remaining thickness of connection hole forming insulating film, t2 ... Thickness of wiring groove forming insulating film, C ... Opening.

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F004 BA04 DB03 EA23 EA28 EA37                       EB01 EB03 EB08                 5F033 HH11 HH15 HH18 HH21 HH32                       HH33 JJ01 JJ11 JJ18 JJ21                       JJ32 JJ33 KK01 KK11 KK15                       KK18 KK21 KK32 KK33 MM01                       MM02 MM12 MM13 NN06 NN07                       PP06 PP15 PP27 PP28 PP33                       QQ03 QQ04 QQ09 QQ10 QQ13                       QQ21 QQ25 QQ28 QQ37 QQ48                       RR04 RR06 SS11 TT02 XX01                       XX03 XX28 XX31

Claims (7)

[Claims] 1. A step of forming a connection hole forming insulating film on a lower layer wiring, a step of forming an etching stopper layer on the connection hole forming insulating film, and a wiring groove forming insulating film on the stopper layer. A step of forming a film; a step of forming a mask layer serving as an etching mask for forming a wiring groove on the wiring groove forming insulating film; the mask layer, the wiring groove forming insulating film, and the stopper layer By etching, and forming a connection hole pattern opening by etching the connection hole formation insulating film halfway, and forming an opening in the mask layer so as to form a wiring groove pattern. And a step of forming the wiring layer forming insulating film and the connection hole forming insulating film by etching until the stopper layer is exposed using the mask layer as a mask. Forming a wiring groove in the insulating film for forming a wiring groove, and forming a connection hole reaching the lower layer wiring in the insulating film for forming a connection hole; removing the mask layer; And a step of filling the connection hole with a conductive material. 2. The mask layer, the insulating film for forming the wiring groove,
In the step of forming an opening to be a pattern of a connection hole in the stopper layer and the connection hole forming insulating film, the remaining thickness of the connection hole forming insulating film is thinner than the thickness of the wiring groove forming insulating film. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is removed so that 3. The mask layer, the insulating film for forming the wiring groove,
The step of forming an opening serving as a pattern of the connection hole in the stopper layer and the insulating film for forming the connection hole includes forming an opening in the pattern of the connection hole on the mask layer
Forming a resist mask; etching the mask layer, the wiring groove forming insulating film, and the stopper layer using the first resist mask as an etching mask, and in the middle of the connecting hole forming insulating film. The method of manufacturing a semiconductor device according to claim 1, further comprising: a step of removing by etching, and a step of removing the first resist mask. 4. The step of forming an opening in the mask layer so as to form the pattern of the wiring groove includes a step of forming an opening in the pattern of the wiring groove on the mask layer.
A step of forming a resist mask; a step of removing the mask layer by etching using the second resist mask as an etching mask to form the opening to be a pattern of the wiring groove in the mask layer; The method of manufacturing a semiconductor device according to claim 1, further comprising the step of removing the resist mask. 5. The step of filling the wiring groove and the connection hole with a conductive material, the step of depositing a conductive material on the wiring groove forming insulating film so as to fill the wiring groove and the connection hole, and the wiring. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of removing the conductive material deposited on the wiring groove forming insulating film by polishing while leaving the conductive material buried in the groove and the connection hole. 6. The method of manufacturing a semiconductor device according to claim 5, wherein in the step of filling the wiring groove and the connection hole with a conductive material, a conductive material containing copper is embedded. 7. Before the step of depositing a conductive material on the wiring groove forming insulating film, the inner wall surfaces of the wiring groove and the connection hole are covered with copper on the wiring groove forming insulating film. The method further comprises the step of forming a barrier film for preventing diffusion, and in the step of depositing the conductive material, depositing the conductive material containing copper on the barrier film so as to fill the wiring trench and the connection hole, In the step of removing the conductive material by polishing, the barrier film and the conductive film deposited on the wiring groove forming insulating film while leaving the barrier film and the conductive material buried in the wiring groove and the connection hole. The method of manufacturing a semiconductor device according to claim 6, wherein the material is removed by polishing.