JP2003330444A - Picture/voice processing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a picture/voice processing circuit which can lighten a load of a CPU. <P>SOLUTION: An analog voice signal outputted from a microphone is applied to an analog input processing circuit 26. The analog input processing circuit 26 converts an analog voice signal to a digital signal, next, processing (e.g. maximum amplitude detection) previously decided in data after conversion is performed, and a sprite attribute table 25 is rewritten conforming to the processing result. Thereby, display sprite attribute (e.g. magnitude) is changed, and sprite display of a LCD monitor 14 is changed. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image / voice processing circuit which is a circuit mainly used in an interactive game machine or the like, and which controls a display image, a musical sound, and a voice based on a voice input from a microphone. .

[0002]

2. Description of the Related Art In recent years, interactive game machines such as pachinko machines have been developed. In this interactive game machine, a microphone is provided in the front corner of the game machine, and when the player speaks into the microphone, the game machine replies from the speaker or the image display section on the front of the game machine. The displayed image changes according to the words of the player.

FIG. 10 is a block diagram showing the structure of the main part of an electric circuit of a conventional interactive game machine of this type. In this figure, reference numeral 1 is a microphone, and 2 is a voice processing LSI.
(Integrated circuit) 3, CPU (central processing unit), 4 CP
ROM (read only memory) in which the U3 program is stored, 5 RAM (random access memory) for temporary data storage, 6 image processing LSI, 7 LCD (liquid crystal) monitor, 8 sound source LSI, 9 speaker Is.

In such a configuration, when the player speaks into the microphone 1, the voice processing LSI 2 recognizes the voice input from the microphone 1 and outputs the result to the CPU 3. CPU3 is voice processing LSI2
In response to the recognition result, the display change instruction is output to the image processing LSI 6, and the tone change instruction is output to the tone generator LSI 8. As a result, the image display changes according to the voice input from the microphone 1, and the generated musical sound or voice changes.

[0005]

By the way, in the above-mentioned conventional interactive game machine, the CPU 3 controls the image display and the tone / voice generation based on the output of the voice processing LSI 2. There was a problem of increasing the load on the. The present invention has been made in view of such circumstances, and an object thereof is to provide an image / sound processing circuit capable of reducing the load on the CPU.

[0006]

The present invention has been made to solve the above-mentioned problems, and the invention according to claim 1 is to control image display or sound generation based on data in a specific storage section. In the image / audio processing circuit for performing the above, an input terminal to which an analog audio signal output from a microphone is applied, A / D conversion means for converting the analog audio signal input from the input terminal into a digital signal, and the A An image / sound processing circuit comprising: a data processing unit that performs a predetermined process on the output of the D / D conversion unit; and a rewriting unit that rewrites the data in the storage unit by the output of the data processing unit. Is.

The invention described in claim 2 is the same as claim 1
In the image / sound processing circuit described in the above item 3, the data processing means performs processing for detecting a difference between the maximum value and the minimum value of the output of the A / D conversion means. Also,
According to a third aspect of the present invention, in the image / audio processing circuit according to the first or second aspect, the storage unit stores attribute data for controlling an attribute of a display sprite, and the rewriting unit. Is characterized in that the attribute data is rewritten by the output of the data processing means.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an image processing circuit 11 according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a configuration of a main part of an interactive game machine using the image processing circuit 11. . In FIG. 2, reference numeral 12 is a microphone, and its output (analog signal) is supplied to the image processing circuit 11 and the sound source circuit 13. Reference numeral 14 is an LCD (liquid crystal) monitor driven by the output of the image processing circuit 11, and 15 is a speaker to which the output of the sound source circuit 13 is applied. 16 is an image processing circuit 1
CPU for controlling each part of the interactive game machine while controlling 1 and the tone generator circuit 13, 17 is a ROM in which the program of the CPU 16 is stored, and 18 is an RA for temporarily storing data
It is M.

Next, details of the image processing circuit 11 will be described with reference to FIG. In FIG. 1, 21 is a ROM I / F
It is an (interface) and outputs compressed character data for displaying a sprite (display character) supplied from the ROM 17 via the CPU to the decompression engine 22. The decompression engine 22 decompresses the character data and writes it in the sprite buffer 23. Also, C
The PUI / F 24 rewrites the data in the sprite attribute table 25 according to an instruction from the CPU 16.

As shown in FIG. 3, the sprite attribute table 25 is a table in which the attributes such as the display position and the enlargement / reduction ratio of each sprite are stored. The analog input processing circuit 26 is a circuit that rewrites the sprite attribute table 25 based on the analog signal output from the microphone 12 (FIG. 1), and the details will be described later. Drawing engine 2
Reference numeral 8 indicates the character data of each sprite read from the sprite buffer 23, the read character data is changed according to the attribute data in the sprite attribute table 25, and the changed data is framed according to the data indicating the display position in the sprite attribute table 25. Write in the buffer 29.

The LCD control circuit 30 generates a timing signal for driving the LCD monitor 14 based on the clock pulse and outputs it to the display I / F 31. Display I /
The F31 reads the data in the frame buffer 29 according to the timing signal output from the LCD control circuit 30, and outputs it to the LCD monitor 14. As a result, the sprite character data stored in the sprite buffer 23 is changed by the attribute data in the sprite attribute table 25 and displayed on the LCD monitor 14.

Next, the analog input processing circuit 26 will be described with reference to FIG. In FIG. 3, reference numeral 35 is an analog input terminal to which the output of the microphone 12 is input. 36 is an A / D (analog / digital) conversion circuit for converting the analog signal obtained at the analog input terminal 35 into a digital signal, and 37 is the maximum amplitude of the analog signal at the input terminal 35 based on the output of the A / D conversion circuit 36. It is a maximum amplitude value detection circuit for detecting a value.

FIG. 4 is a block diagram showing the configuration of the maximum amplitude value detection circuit 37. In this figure, 38 and 39 are shown.
Is a comparison / selection circuit, 40 is max-reg (maximum value register), 41 is min-reg (minimum value register), 42
Is a subtraction circuit, and 43 is a LAT (latch). Figure 5
6 is a flowchart showing the operation of the maximum amplitude value detection circuit 37. First, ST which is periodically generated at fixed time intervals.
When the ART pulse rises to "1" (step S1 is "YES"), the output of the subtraction circuit 42 is latched by the LAT 43, and then max-reg 40, min-reg
Input data IN (output of the A / D conversion circuit 36) is written in 41. After that, the input data I is output every time the clock pulse is output until the START pulse rises again.
N and the output of max-reg 40 and the output of min-reg 41 are compared in the comparison and selection circuits 38 and 39 (steps S3 and S4), and the input data IN is max-reg4.
If the output is greater than 0, the input data IN is max.
-Reg40 is written (step S5), and if the input data IN is smaller than the output of min-reg 41, the input data IN is written to min-reg 41 (step S6).

When the START pulse rises again, the output of max-reg 40 changes to min-reg 4
The result obtained by subtracting the output of 1 in the subtraction circuit 42, that is, the maximum amplitude value from the START pulse to the next START pulse is read into the LAT 43, and then the input data IN is written into the max-reg 40 and the min-reg 41 again. Be done. FIG. 6 is a timing chart of the above-mentioned operation. In this figure, (a) shows a clock pulse, (b) shows a START pulse, and (c).
Is the input data IN, (d) is the output of max-reg 40, (e) is the output of min-reg 41, (f) is the output of the subtraction circuit 42, and (t) is the output of LAT 43. There is.

This figure also shows a START pulse SP1.
This is a case where the maximum data of the input data IN is D2 and the minimum data is D96 between the period from to the START pulse SP2. The input data IN becomes D2 at the timing of the symbol A1 in the figure, and therefore the data D2 is written to the max-reg 40 at the next timing. In addition, at the timing of the symbol A2 in the figure, the input data IN
Becomes D96, and therefore the data D96 is written to the min-reg 41 at the next timing. Then, at the trailing edge of the START pulse SP2, the data (D2-D96) is written in the LAT 43.

Next, returning to FIG. 3, reference numeral 46 denotes a multiplication circuit, which multiplies the coefficient preset in the register by the output of the maximum amplitude value detection circuit 37 and outputs the result to the addition circuit 47. To do. The adder circuit 47 adds the output of the multiplier circuit 46 to the basic enlargement / reduction rate preset in the register and outputs it. Reference numerals 48 to 50 denote selectors, which output the adder circuit 47 when the rewrite timing signal is "1".
The rewrite attribute table address and the analog input WE (write enable) signal preset in the register are output to the sprite attribute table 25, respectively, and when the rewrite timing signal is "0", output from the CPU 16. The data CPUDT, the address CPUAD output from the CPU 16 and the write enable signal CPUWE output from the CPU 16 are output to the sprite attribute table 25, respectively. Here, the rewrite timing signal is a signal which becomes "1" in a constant cycle, and as shown in FIG. 7, is a signal which rises to "1" for a short time immediately after the START pulse. Further, the writing of each of the registers described above is performed via the CPU 16.

Next, the operation of the circuits shown in FIGS. 3 and 4 will be described. First, when a START pulse is generated, the previous S
The maximum amplitude value of the input analog signal between the TART pulse and the current START pulse is read by the LAT 43 and output to the multiplication circuit 46. The multiplication circuit 46 multiplies the output of the LAT 43 by a coefficient and outputs the result to the addition circuit 47. The adder circuit 47 uses the basic enlargement / reduction rate to multiply the multiplication circuit 46.
The outputs of the above are added and output to the selector 48. Here, when the rewrite timing signal rises, the output of the adder circuit 47 is written in the storage position of the sprite attribute table 25 indicated by the rewrite attribute table address. In this case,
The scaling rate is rewritten. That is, the enlargement / reduction ratio is rewritten by the data corresponding to the maximum value of the voice input from the microphone 12, whereby the LCD
As shown in FIG. 8, the sprite display on the monitor 14 is displayed small when the voice input is small (see FIG. 8A) and is displayed large when the voice input is large (FIG. 8).
(See (b)).

FIG. 9 is a flow chart showing the process of the display process of the LCD monitor 14 described above. When the microphone 12 is turned on (step Sa2) while the image display (step Sa1) is being performed, the above-mentioned process is performed. Voice analysis (detection of maximum voice) is performed (step Sa
3) At the rewrite timing of the sprite attribute table 25 (step Sa4), a rewrite timing signal is generated and the sprite attribute table 25 is rewritten (step Sa5). Then, step Sa1
Returning to, the image display is performed based on the rewritten sprite attribute table 25.

In the above description, only the image processing circuit 11 has been described, but the sound source circuit 13 is also provided with a similar configuration, and is generated from the speaker 15 according to the volume of the sound input from the microphone 12. The music to be played is controlled.

[0020]

As described above, according to the first aspect of the invention, the sound signal can be directly processed without controlling the CPU to control the image and the sound (tone), so that the load on the CPU can be reduced. The effect that can be obtained is obtained. Further, according to the invention of claim 2, since the data processing means performs the processing of detecting the difference between the maximum value and the minimum value of the output of the A / D conversion means, the data processing means is adapted to the magnitude of the input audio signal. Display / sound control can be performed. Further, according to the invention of claim 3, the storage unit stores the attribute data for controlling the attributes of the display sprite, and the rewriting means rewrites the attribute data by the output of the data processing means. Can be changed according to the voice.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an image processing circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an interactive game machine using the image processing circuit.

FIG. 3 is a block diagram showing configurations of an analog input processing circuit 26 and a sprite attribute table 25 in the image processing circuit.

4 is a block diagram showing a configuration of a maximum amplitude value detection circuit 37 in FIG.

FIG. 5 is a flowchart for explaining the operation of the maximum amplitude value detection circuit 37.

FIG. 6 is a timing chart for explaining the operation of the maximum amplitude value detection circuit 37.

FIG. 7 is a waveform diagram of the START pulse in FIGS. 4 and 5 and the rewriting timing signal in FIG.

FIG. 8 is a diagram for explaining the operation of the analog input processing circuit 26 shown in FIG.

9 is a flowchart for explaining the operation of the analog input processing circuit 26 shown in FIG.

FIG. 10 is a block diagram showing a configuration of a conventional interactive game machine.

[Explanation of symbols]

11 ... Image processing circuit, 12 ... Microphone, 13 ... Sound source circuit, 14 ... LCD monitor, 15 ... Speaker, 25 ...
Sprite attribute table, 26 ... Analog input processing circuit, 35 ... Analog input terminal, 36 ... A / D converter, 3
7 ... Maximum amplitude value detection circuit, 46 ... Multiplication circuit, 47 ... Addition circuit.

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 2C001 BA06 BA07 BC05 BC06 CA07                       CB01 CB02                 2C088 AA36 AA51 BC25 CA13 EB78                 5C082 AA06 AA21 BA02 BA12 BA26                       BB13 BB42 BD09 CA82 CB05                       DA22 DA53 DA73 DA86 MM05                 5D045 AB11

Claims (3)

[Claims] 1. An image / sound processing circuit for controlling image display or sound generation based on data in a specific storage section, wherein an input terminal to which an analog sound signal output from a microphone is applied, and the input terminal A / D conversion means for converting the input analog audio signal into a digital signal, data processing means for performing a predetermined process on the output of the A / D conversion means, and the output of the data processing means An image / sound processing circuit, comprising: 2. The image / audio processing circuit according to claim 1, wherein the data processing unit performs a process of detecting a difference between the maximum value and the minimum value of the output of the A / D conversion unit. 3. The storage unit stores attribute data for controlling an attribute of a display sprite, and the rewriting unit rewrites the attribute data according to an output of the data processing unit. Alternatively, the image / sound processing circuit according to claim 2.