JP2003329608A - Inspection condition judgement program, inspection apparatus and inspection system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To judge whether the inspection condition of an inspection apparatus is appropriate or not by using a computer equipped in the inspection apparatus and an inspection system of products which forms and manufactures a plurality of products such as a semiconductor integrated circuit on a substrate at the same time. <P>SOLUTION: A defect coordinate data are input by a defect coordinate data input process 11. A conditional branch 12 with the number of defects and a first threshold value is performed. When the number of defects is larger than the first threshold value, a conditional branch 15 is performed with a dispersion and a second threshold value after performing a defect number calculation process 13 according to areas in a chip and a dispersion calculation process 14. When the dispersion is larger than the second threshold value, a warning process 16 is performed. On the other hand, a warning process 17 is performed when the number of defects is the first threshold value or below. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is carried out by a computer provided in an inspection system or inspection system for products that simultaneously manufactures a plurality of products such as semiconductor integrated circuits on a single substrate.
The present invention relates to an inspection condition determination program for determining whether or not inspection conditions of an inspection device are appropriate.

[0002]

2. Description of the Related Art The prior art will be described below by taking the manufacture of a semiconductor integrated circuit as an example. A semiconductor integrated circuit is generally divided into a pre-process for manufacturing a plurality of chips by layering layers such as a circuit pattern on a silicon wafer and a post-process for separating each chip to complete a product.

In the pre-process, disconnection or short circuit of the circuit pattern occurs due to foreign matters or pattern defects (generally referred to as defects) generated during manufacturing. A foreign material inspection device and a visual inspection device are used for the purpose of monitoring defects. In general, a foreign matter inspection apparatus is an apparatus that irradiates a wafer with laser light obliquely from above and detects scattered light thereof, and is sometimes called a dark field inspection apparatus. The visual inspection device is a device that picks up an image of a circuit pattern and detects an abnormal portion by image processing, and a bright field inspection device or S
There is an EM type inspection device. These are described in the article "Inspection System Supporting Improvement of Semiconductor Yield" published in the October 1999 issue of the magazine "Hitachi Kenroku". However, the foreign matter inspection device and the appearance inspection device have no clear distinction other than the difference in the detection principle, and are collectively referred to as a defect inspection device hereinafter in this document.

It is important for the defect inspection apparatus to detect a defect on a circuit pattern formed on a wafer to be inspected with high sensitivity. Therefore, in order to utilize the defect inspection apparatus, it is necessary to set appropriate inspection conditions according to the film formation state on the wafer and the circuit pattern formation state. Generally, a defect inspection apparatus can roughly execute two types of inspection programs by presetting two inspection conditions. These are circuit pattern conditions and optical / image processing conditions.

The circuit pattern conditions are parameters such as size and arrangement information of chips formed on the wafer, and area information in each chip according to the inspection algorithm of the inspection apparatus. The optical and image processing conditions are parameters such as laser irradiation amount according to film forming conditions and wiring materials, contrast conditions of the image captured by the detector, threshold value information during image processing, and detection sensitivity. Is what determines.
The circuit pattern condition and the optical / image processing condition are closely related to each other.

Generally, the optical and image processing conditions are set by inspecting an actual product wafer several times with an inspection device and adjusting the detection result to an appropriate state. Here, the appropriate state is a state in which defects as small as possible can be detected, but false alarms are not detected as much as possible. The false information is color irregularity of the circuit pattern that is not actually a defect, fine unevenness on the circuit pattern, irregular reflection due to a defect in illumination, etc., and is not related to the quality of the integrated circuit. False alarms are sometimes called pseudo defects.

Conventionally, whether or not the optical / image processing conditions are appropriate has been determined by any one of the following methods or a combination of a plurality of methods. (1) The defect candidates detected by the inspection device are observed one by one with a microscope, and it is determined whether they are defects or false reports. (2) It is determined whether or not there are a large number of defect candidate chip coordinates detected by the inspection device at substantially the same position. This method is
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"ecognition".

[0008]

In the above-mentioned method for determining whether the optical / image processing conditions are in an appropriate state, the method is set so that false alarms are minimized and defects are detected as many as possible. Especially the focus is on. However, we have found that the following phenomena occur depending on the optical and image processing conditions.

FIG. 2A shows the inspection result under the optical / image processing conditions which are determined to be appropriate by the above method. The figure shows the coordinate distribution of detected defects in the chip. The black circles represent the coordinates of the detected defects. (B)
Shows the result of inspection with slight changes in optical and image processing conditions. In (b), the number of detected defects is smaller than that in (a), but the coordinates at which the defects are detected are distributed more dispersively than in (a). As a result of observing the defects one by one with a microscope in both (a) and (b), none of them were false alarms and were true defects. (C) is a circuit layout to be inspected. Squares in the chip represent circuit blocks. The circuit block is a group for each function of the circuit, and in this example, 31 and 3
2 is an SRAM circuit block, 33 is a microcomputer core circuit block, 34 is a ROM circuit block, and 35 is a logic circuit block. In order to compare (a) and (b) with (c), (a) and (c) are displayed in a superposed manner, which is (d). Further, (e) is a display in which (b) and (c) are superimposed. In (d), many defects were detected in the portions not included in the circuit blocks 31 to 35, but only 41 and 42 defects were detected in the circuit block. (E) is the circuit block 3
Although the number of defects detected was smaller than that in (d) in the portions not included in 1 to 35, a larger number of defects were detected in (a) in the circuit block. Of the defects in the circuit blocks 51 to 60, only the defects 56 and 58 could be detected as 41 and 42 in (d), but the others were detected in (e), but were detected in (d). It wasn't done. According to the conventional idea of detecting as few defects as possible and detecting as many defects as possible, the detection result of (a) (the number of defects 29
The number of defects is better than the result of (b) (21 defects). However, when it comes to whether or not the defect that the integrated circuit is a defective product can be detected, the defect in the circuit block can be detected in (b), which is a good optical / image processing condition.

Therefore, in determining whether or not the optical / image processing conditions are optimal, a mechanism for determining that (b) is better is necessary.

[0011]

In order to solve the above-mentioned problems, the present invention provides a program that is executed to determine whether or not the optical / image processing conditions are in an appropriate state. The program of the present invention is stored in the secondary storage device of the defect inspection apparatus, read out to the main storage apparatus, and also executed in the embodiment, and stored in the secondary storage apparatus of a computer different from the defect inspection apparatus. An embodiment may be used in which the main storage device is read and executed, and the output file is downloaded to the defect inspection device via a network or a removable storage medium and utilized.

Specifically, in a program executed to manage the inspection conditions of an inspection device for detecting the position of a foreign substance or pattern defect that the inspection target has, the inspection device has the foreign substance or pattern that the inspection target has. Coordinate input processing for inputting coordinate data of what is detected as a defect, and in-chip defect density distribution calculation processing for quantifying variation in defect density in the chip from the coordinate data input by the coordinate input processing, Inspection condition determination characterized by performing a defect determination process of comparing the quantified value with a predetermined threshold value and determining whether the inspection condition of the inspection device is good or bad in the defect density distribution calculation process in a chip. Offer the program.

Further, there is provided an inspection device or inspection system having the above-mentioned program.

More specifically, it is configured as described in the claims.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is an example showing a processing procedure for determining whether or not the optical / image processing conditions are appropriate in the present invention. In step 11, the wafer to be inspected is inspected by the inspection device, and the coordinate data of the detected defect is input. Here, the defect coordinate data is data as shown in FIG. 3, and includes a defect number for identifying the detected defect and a chip X for identifying which chip in the wafer surface has the defect. , Y, and in-chip coordinates X, Y indicating the position of the defect in the chip. Depending on the inspection device, the coordinates of the defect may be set to the chip X, Y
There is also a device that does not express the combination of the in-chip coordinates X and Y, but simply provides the coordinates X and Y by providing one coordinate system in the wafer surface. In any case, the defect is information on the existing position on the wafer surface. FIG. 4 is an illustration so that FIG. 3 can be visually recognized. It is generally called a wafer map or defect map. The circular outer frame represents the outer circumference of the wafer, and the V-shaped recess is
It is a notch that represents the orientation of the wafer. A large number of open squares represent integrated circuit chips formed in the wafer.
In FIG. 3, defect number 1 is black circle 21, defect number 2 is black circle 22, defect number 3 is black circle 23, defect number 4 is black circle 24,
The defect number 5 corresponds to the black circle 25, the defect number 6 corresponds to the black circle 26, the defect number 7 corresponds to the black circle 27, and the defect number 8 corresponds to the black circle 28.

In FIG. 1, in step 12, the number of defects is compared with a predetermined threshold value to perform conditional branching. When the number of defects is extremely small, that is, when the number of defects is smaller than the threshold value, the number of defects is not small, and the sensitivity is not sufficient to detect defects due to a mistake in setting inspection conditions in many cases. Therefore, the conditional branching proceeds in the direction of No, and in step 17, a warning is issued to promote the sensitivity improvement. Here, the warning means, for example, notifying the operator in charge of the inspection apparatus by e-mail or displaying the status on the control screen of the inspection apparatus.

In step 13, the number of defects in each in-chip area is calculated from the input defect coordinate data. Figure 5
FIG. 4 shows the coordinate distribution in the chip. A square frame represents a chip, and a plurality of black circles represent the in-chip coordinates X and Y of the defect coordinate data shown in FIG. Defect number 1 is black circle 41, defect number 2 is black circle 42, defect number 3 is black circle 43, defect number 4 is black circle 44, defect number 5 is black circle 45, defect number 6 is black circle 46, defect number 7 is black circle 47, defect The number 8 corresponds to the black circle 48. FIG. 6 is a diagram in which the in-chip coordinate distribution of FIG. 5 is divided into regions in a matrix. In this example, the chip is divided into four parts horizontally and four parts vertically, and the number of defects existing in each divided region is Z.
It is expressed as one (x, y). Where x is 1 to 4
And y is an integer of 1 to 4. For example, Zone
Since (3, 2) has two defects, the value is calculated as 2. This calculation is performed for each area to calculate Zone (x, y). The value of Zone (x, y) becomes the defect density for each area. The defect density is the number of defects per unit area.

In step 14, Zone (x, y) calculated in step 13, (x = 1 to 4 is an integer, y = 1 to 1)
The variance is calculated from (an integer of 4). That is, Equation 1 is calculated.

[0020]

[Equation 1]

As shown in FIG. 7, this variance represents the variation in the histogram when the defect density is plotted on the horizontal axis and the frequency of Zone (x, y) is plotted on the vertical axis. In FIG.
There are nine areas in which the value of Zone (x, y) is zero, which is 61 in FIG. 7. There are six areas in which the value of Zone (x, y) is 1, which is 62 in FIG. 7. Zone
There is one area where the value of (x, y) is 2, which is 6 in FIG.
It is 3. When the values of Zone (x, y) are completely different from each other, the value of this dispersion becomes large and the defect coordinate distribution in the chip is biased.

In step 15, the obtained variance is compared with a predetermined threshold value to perform conditional branching. The threshold used here is different from the threshold used in step 12. If the dispersion is larger than the threshold value, the defect coordinate distribution in the chip is biased, and it cannot be said that the inspection condition is appropriate. Therefore, the process proceeds to step 16 and a warning is given.

The threshold used in step 15 is not limited to a fixed value. For example, the number of defects detected varies for each wafer to be inspected or for each inspection process. FIG. 13 shows the number of defects detected from the inspected object, which is 2
It is the graph which compared the standard deviation which took the square root of the calculated | required dispersion | variation. Each black circle is a dot obtained by calculating a pair of the number of defects and the standard deviation for each inspected object. From this graph, it can be seen that the standard deviation increases as the number of defects increases. In order to deal with such a phenomenon, a regression line 91 is obtained from the hitting point of the result when the inspection conditions are appropriately determined, and the straight line 9 is drawn at a position slightly apart from the regression line.
If a result such as the hit point 90 occurs with 2 as the threshold value, it may be determined as an inappropriate inspection condition. In this case, the threshold value is variable according to the number of defects.

In this example, for convenience of explanation, the inside of the chip is vertically
Although the area is defined by dividing the area into four areas horizontally, it is not necessary to follow this and it is better to divide the area more finely. Further, the number of divisions may be changed according to the number of defects on the wafer. Further, in the above formula 1, the variances are collectively calculated from the 16 Zones (x, y), but the variance of the horizontal sum and the variance of the vertical sum are separately calculated, and both of them are calculated. It is also effective to use the larger value for conditional branching. Further, in this example, the inside of the chip is divided into matrix areas, and the number of defects in each area is used to determine whether or not the optical / image processing conditions are appropriate. However, in addition to this example, for example, there is a description in the paper “Discussion on a method for identifying a point cloud distribution shape” by the present inventors at the Institute of Electronics, Information and Communication Engineers “Pattern Recognition and Media Understanding Study Group” in June 2001. A quantification method using a Voronoi diagram based on computational geometry may be applied to the defect coordinate distribution in the chip as in the present invention. Figure 8
As shown in FIG. 5, by using this method, a Voronoi diagram is created from the defect coordinates, and the variation in the area of each region of the Voronoi diagram is calculated, so that the variation in the defect density can be calculated in the same manner as described above. In any case, it suffices if the deviation of the defect coordinate distribution in the chip can be quantified.

On the other hand, as described above, it is effective to use only the defect coordinate data existing in a specific circuit block in the chip instead of using all the defect coordinate data of FIG. For example, when the sensitivities of detecting defects in the chips are obviously different, the circuit blocks in which the defects are to be detected are mainly determined in the integrated circuit. Next, using the defect coordinate data in the circuit block, the optical / image processing conditions are adjusted to an appropriate state by the method described above.

For example, FIG. 9 shows an example in which the in-chip distribution of the defect coordinate data shown in FIG. 5 and the circuit layout of the integrated circuit are superimposed. A thick frame 35 is an area of the logic circuit block defined as a specific area, and within the area, black circles 41, black circles 44, black circles 45, and black circles 47, that is, defect numbers 1 and 4 of the defect coordinate data of FIG. There are 5 and 7.

FIG. 10 shows that only a specific area is divided into four vertically.
This is an example of horizontal division into six. From this result, the number of defects is calculated for each area, the variance is further calculated, and warning processing is performed.

FIG. 11 is an example of a defect inspection apparatus for carrying out the present invention. The defect inspection device 70 includes a defect inspection unit 71, a control unit 72, a secondary storage device 73, and a main storage device 7.
4, a calculation unit 75, a user interface 76, and the like. The defect inspection unit 71 includes a stage that moves the wafer vertically and vertically to mechanically position the wafer, illumination that irradiates the wafer with a laser, a lens and a detector for imaging a defect on the wafer, and the like. The control unit 72 includes a defect inspection unit 71, a secondary storage device 73,
It controls the operations of the main memory device 74, the arithmetic unit 75, the user interface 76, and the like. The secondary storage device 73 is a storage medium such as a hard disk. The program and defect coordinate data of the present invention are stored in the secondary storage device 73. The main storage device 74 is a storage medium such as a random access memory. When executing the program of the present invention, the program stored in the secondary storage device 73 is read into the main storage device 74. In addition, the secondary storage device 7
The defect coordinate data stored in No. 3 is read out to the main storage device 74. The arithmetic unit 75 is an arithmetic processing device such as a microprocessor. Calculation is performed based on the program read to the main storage device 74. The user interface 76 is an output device such as a liquid crystal display or a printer, or an input device such as a keyboard or a mouse. The input device is used to start the program, and the output device is used to output the results of the warning processes 16 and 17.

FIG. 12 is an example of a defect inspection apparatus management system for carrying out the present invention. The program of the present invention may be executed inside the defect inspection apparatus as shown in FIG. 11, but as shown in FIG. 12, a computer different from the defect inspection apparatus,
It may be executed inside the device management unit 82. The defect inspection device 80 is connected to the local area network 81. The device management unit 82 is also connected to the local area network 81. The device management unit 82
Similar to the defect inspection apparatus 70 of FIG. 11, a control unit 72, a secondary storage device 73, a main storage device 74, a calculation unit 75, and a user interface 76 are provided. Further, a network interface 77 is provided for connecting to the local area network 81. The defect coordinate data of FIG. 3 is fetched from the defect inspection device 80 via the local area network 81 from the network interface 77 and stored in the secondary storage device 73. The program of the present invention is stored in the secondary storage device 73. This program is read into the main storage device 74 and executed. The execution result of this program is output using the user interface 76.

As described above, in this example, the procedure for determining whether or not the optical / image processing conditions are appropriate is shown by using the defect coordinate data detected from one wafer. However, the defect coordinate data detected from multiple wafers is
It is effective to input into this program to determine whether the optical / image processing conditions are appropriate. In particular, when the defect coordinate data detected from one wafer is small, using the data of a plurality of wafers is extremely effective.

[0031]

As described above, according to the present invention,
It is possible to determine whether or not the inspection conditions of the inspection device are appropriate by executing the inspection device for the product, which is manufactured by simultaneously forming a plurality of products such as semiconductor integrated circuits on one substrate, and a computer provided in the inspection system. It is possible to avoid inspecting under the inadequate inspection conditions of the inspection device, and it is possible to reliably perform quality control in the manufacture of semiconductor integrated circuits and the like.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of an inspection condition determining procedure according to the present invention.

FIG. 2 is a diagram showing an example of a problem that requires the present invention.

FIG. 3 is a diagram showing an example of defect coordinate data.

FIG. 4 is a diagram showing an example of a defect map.

FIG. 5 is a diagram showing an example of an in-chip coordinate distribution.

FIG. 6 is a diagram showing an example in which the in-chip coordinate distribution is divided into regions in a matrix.

FIG. 7 is a diagram showing an example of a defect density histogram.

FIG. 8 is a diagram showing an example in which a Voronoi diagram is created from the in-chip coordinate distribution and the region is divided.

FIG. 9 is a diagram showing an example of a specific area in a chip.

FIG. 10 is a diagram showing an example in which a specific area in a chip is divided into matrix areas.

FIG. 11 is a block diagram showing an embodiment of an inspection device according to the present invention.

FIG. 12 is a block diagram showing an embodiment of an inspection system according to the present invention.

FIG. 13 is a diagram showing an example of a threshold value according to the number of defects.

[Explanation of symbols]

11 ... Defect coordinate data input processing, 12 ... Conditional branching by number of defects vs. first threshold value, 13 ... Defect number calculation processing for each in-chip area, 14 ... Distributed calculation processing, 15 ... Dispersion vs. second threshold value Conditional branching, 16 ... Warning processing (sensitivity reduction required),
Reference numeral 17 ... Warning processing (sensitivity improvement required) 21-28 ... Defect coordinate spotting point, 31, 32 ... SRAM circuit block, 33 ... Microcomputer circuit block, 34 ... ROM circuit block, 35
... Logic circuit blocks, 41-48 ... Defect coordinate dot points, 51-60 ... Defect coordinate dot points, 61-63 ... Area frequency, 70, 80 ... Defect inspection apparatus, 71 ... Defect inspection unit, 72 ... Control section, 73 ... Secondary storage device, 74 ... Main storage device, 75 ... Computing unit, 76 ... User interface, 77 ... Network interface, 81 ... Local area network, 90 ... Distributed calculation result at the time of failure recipe, 91 ... Regression line, 92 … Threshold straight line.

Continued front page    (72) Inventor Naofumi Iwata             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Inside the Hitachi, Ltd. production technology laboratory (72) Inventor Kanako Harada             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Inside the Hitachi, Ltd. production technology laboratory (72) Inventor Yuji Takagi             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Inside the Hitachi, Ltd. production technology laboratory (72) Inventor Hisae Shibuya             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Inside the Hitachi, Ltd. production technology laboratory F-term (reference) 2G051 AA51 AB01 AB07 EA12 EA21                       EB02 EB03 EC02                 4M106 AA01 AA02 CA38 DB30                 5B057 AA03 BA30 CA12 CB12 CH01                       DA03 DA12 DA16

Claims (10)

[Claims] 1. A program executed to manage the inspection conditions of an inspection device for detecting the position of a foreign substance or pattern defect of an inspection target, wherein the inspection device detects the foreign substance or pattern defect of the inspection target. Coordinate input processing for inputting coordinate data of the processed data, and in-chip defect density distribution calculation processing for quantifying the variation of defect density distribution in the chip from the input coordinate data in the coordinate input processing; A defect density distribution calculation process, comparing a quantified value with a predetermined threshold value, and executing a quality determination process for determining quality of the inspection condition of the inspection apparatus. . 2. As the defect density distribution calculation process within a chip, a distribution of coordinate data within a chip is divided into a plurality of regions,
An inspection condition determination program characterized by counting the number of particles or pattern defects existing in each area and calculating the variation in the number of particles or pattern defects in each area. 3. A Voronoi diagram is created from an in-chip distribution of coordinate data as the in-chip defect density distribution calculation processing,
An inspection condition determination program, characterized in that it calculates an area variation for each divided area of a Voronoi diagram. 4. The inspection condition determination program according to claim 1, wherein, as the coordinate input processing, only coordinate data existing in a designated circuit area is input from coordinate data of a foreign substance or a pattern defect. 5. The inspection condition determination program according to claim 1, wherein in the coordinate input process, coordinate data of a plurality of inspection targets are input. 6. The inspection condition determination program according to claim 1, further comprising: a warning process that warns of a defect in the inspection condition based on the quality determination result determined by the quality determination process. 7. The inspection condition determination program according to claim 1, further comprising: a process of changing an inspection condition based on a quality determination result determined by the non-defective product determination process. 8. A threshold value to be compared with a value quantified in the in-chip defect density distribution calculation process in the pass / fail judgment process varies depending on the number of foreign particles or pattern defects of the inspection object. A characteristic inspection condition determination program. 9. An inspecting unit for detecting the position of a foreign substance or a pattern defect possessed by an inspection target, and a defect density in a chip from coordinate data of what is detected by the inspection unit as a foreign substance or a pattern defect possessing the inspection target. Is quantified and the quantified value is compared with a predetermined threshold value to determine whether the inspection conditions of the inspection device are good or bad. 10. An inspection device for detecting the position of a foreign substance or pattern defect of an inspection target, and coordinate data of what the inspection device detects as a foreign substance or pattern defect of the inspection target is input via a network. From the input unit to, and the coordinate data input by the input unit, quantify the variation of the defect density in the chip, and compare the quantified value with a predetermined threshold,
An inspection system, comprising: a calculation unit that determines pass / fail of an inspection condition of an inspection device; and an apparatus management unit that has an output unit that outputs a result of pass / fail determination of an inspection condition.