JP2003324453A - Multiplex transmission system and multiplex transmission apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To multiplex packet data to SONET/SDH frames in a multiplex transmission system and a multiplex transmission apparatus for various kinds of networks. <P>SOLUTION: In the multiplex transmission system, a plurality of nodes 1-1 to 1-4 are connected via a ring-shaped or mesh-shaped transmission line 3, packet data from a plurality of ports P1 and P2 of each node are multiplexed while converting its speed and the multiplexed data are received and demultiplexed in accordance with the port. The transmitting part of each of the nodes 1-1 to 1-4 is configured to add receiving time information to the packet data corresponding to the plurality of ports P1 and P2, write the data into a FiFo part for speed conversion, first read data of the earlier receiving time, delete the receiving time information added thereto and multiplex the data by adding a tag with which the ports P1 and P2 are identified. The receiving part is configured to identify the tag and demultiplex the data corresponding to the ports P1 and P2. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to SDH (Sync).
hornous Digital Hierarch
y) format, or SONET (Synchron)
The present invention relates to a multiplex transmission system and a multiplex transmission apparatus that multiplex and insert packet data into a payload in an ous optical network format and insert the packet data for transmission.

[0002]

2. Description of the Related Art SDH is used as a high-speed data transmission system.
Method or SONET method is standardized, for example,
SDH STM-1 (Synchronous T)
The transport module level 1) is 155.52 Mbps, and the STM-4 is 622.08 Mb.
The transmission rate is ps, and the SONET method OC-3 (O
optical Carrier level 3), O
These are transmission rates corresponding to C-12. Also STM
-1 or OC-3 has an overhead of 9 columns and 9 rows and 2
It has a frame structure made up of 61 columns and 9 rows of payloads, and the multiplexed data can be transmitted by inserting data in a standardized container or the like into the payloads.

Various network configurations such as ring networks and mesh networks are known. As a highly reliable network configuration, a ring in which a plurality of nodes are connected by a dual ring transmission line is known. Type network configuration has been put to practical use. Furthermore,
A composite ring network configuration in which a plurality of ring networks are connected to each other is also known. As a transmission method between the node and the terminal, the standardized IEEE80
3.2 MAC (Media Access Con)
Ethernet (trademark) having various transmission speeds using a control frame is known. For example, 1 Mbps,
Standardization has been made for transmission rates of 10 Mbps, 100 Mbps, and 1 Gbps, and further development of transmission rates of 10 Gbps is underway.

FIG. 17 is an explanatory diagram of a ring type network, in which 101-1 to 101-4 are nodes (POS), 1
02-1, 102-3, and 102-4 are terminals, 103 is a transmission line formed of an optical fiber, 104 is a physical layer unit, 105 is a router, and 106 is a server. The transmission path 103 is a ring-shaped physical line indicated by a dotted line, 107 is a layer 2 switch unit (L2SW), and is composed of an optical fiber.
For example, it has a transmission band of OC-12. Further, the PPP of the route indicated by the solid arrow is between the node 101-2 and the other nodes 101-1, 101-3, 101-4.
Point-to-point Indicates a logical line for communication according to the protocol, for example, for the case of OC-3 transmission band.

Between the terminal 102-1 and the node 101-1, between the terminal 102-3 and the node 101-3, and between the terminal 102-4 and the node 101-4, for example,
The connection is made by a transmission line such as LAN (Local Area Network) having a transmission speed of 100 Mbps standardized by IEEE802.3 such as 100 BASE-T, and between the server 106 and the node 101-2 is, for example, 10
It is possible to connect with a LAN having a transmission rate of 1 Gbps of 00BASE-X. Then, the terminals 102-1 and 1
When the 02-3 and 102-4 each perform data transmission at a transmission rate of 100 Mbps with the server 106 by PPP, OC-3 (s) of 156.22 Mbps (hereinafter, 156 Mbps) are transmitted by SONET / SDH frames. Using STM-1), 3 OCs
-3 transmission band is used. In this case, regarding one OC-3 transmission band, the 100 Mbps band out of the 156 Mbps band shown in the lower pipe is used, and the remaining 56 Mbps is used. The band is not used.

FIG. 18 is an explanatory diagram of a SONET / SDH frame format, showing a frame format in the case of OC-3 (STM-1), with an overhead of 9
The row has 9 columns and the payload has 9 rows and 261 columns. S
In the case of ONET, the overhead SOH is the section overhead (Section Over Hea).
d), PTR is a pointer, LOH is a line overhead (Line Over Head), and A
1, A2 are frame synchronization bytes, B1 and B2 are error monitoring bytes, D1 to D12 are data communication bytes, and E1 and E2.
Is an order wire byte, F1 is a network operation byte, J0 is a section trace byte, K1 and K2 are automatic switching bytes, Z1 and Z2 are spare bytes, and pointers PTR are H1, H2 and H3 bytes not shown. It is composed by. The other blank portions indicate empty bytes.

FIG. 19 is an explanatory view of the main part of the transmission part of the node, and the node (POS) 1 at the time of PPP transmission in FIG.
01-1 or 101-3 or 101-4, which corresponds to the configuration of the transmission unit, the physical layer unit 111 that receives and processes the data from the transmission path FE on the terminal side, and the FiFo (Fi
first in first out) section 112 and SO
A packet is inserted into the payload of the NET / SDH frame, the packet is converted into an SO-3 / SDH format OC-3 optical signal, and the inserting section 113 is sent to the transmission path 103 (see FIG. 17). The FiFo unit 112 has a memory configuration that performs speed conversion by writing data with a clock signal of 100 MHz and reading it with a clock signal of 156 MHz, for example.

FIG. 20 is an explanatory view of the main part of the receiving unit of the node, and the node (POS) 1 at the time of PPP transmission in FIG.
Which corresponds to the optical signal receiving function of 01-2 and inputs the optical signal of OC-3 from each node via the transmission line,
Extraction units 121-1 to 121-3 for extracting packets from the SONET / SDH frame payload, FiFo units 122-1 to 122-3 for speed conversion, and Layer 2
It has a switch section 123 and a physical layer 124, and this layer 2 switch section 123 corresponds to the layer 2 switch section 104 in FIG. In this case, the node 10 shown in FIG.
The optical signals from 1-1, 101-3, and 101-4 are respectively received and transferred to the server 106.
The iFo units 122-1 to 122-3 are, for example, 156M.
Data is written by the clock signal of Hz, 100 MH
The speed conversion is performed by reading the data with the clock signal of z.

[0009]

[Problems to be Solved by the Invention] Terminals 102-1 and 10-2
Due to the fact that the packet data transmission method on the transmission path on the 2-3, 102-4 side and the SONET / SDH transmission method on the transmission path 103 between the nodes 101-1 to 101-4 are not matched. As described above, the transmission band on the terminal side is 100 Mbps, and the transmission band on the transmission path 103 is O.
In the case of 156 Mbps of C-3 (STM-1), when the bandwidth of 100 Mbps is used, the remaining 56
The Mbps band becomes empty. That is, there is a problem that the transmission band of the transmission path 103 cannot be effectively used.

Further, in order to effectively use the transmission band of the transmission path 103, it is impossible to demultiplex the packets corresponding to the destinations simply by multiplexing the packets from a plurality of terminals. A method of multiplexing as a virtual container VC is applied to the SONET / SDH format payload. However, since each virtual container VC adds overhead, the reduction of transmission efficiency becomes a problem.

It is an object of the present invention to efficiently multiplex packet data from a plurality of terminals to effectively use the transmission band between nodes and to facilitate demultiplexing.

[0012]

A multiplex transmission system according to the present invention will be described with reference to FIGS. 1 and 2. A plurality of nodes 1-1 to 1-4 are connected via a transmission line 3, A multiplex transmission system in which packet data from a plurality of ports P1 and P2 of a node are speed-converted and multiplexed, and the multiplexed data is received and demultiplexed corresponding to the ports. -4 has a transmission unit for transmitting the data multiplexed on the transmission line 3 and a reception unit for demultiplexing the data received via the transmission line 3, and the transmission unit is provided from a plurality of ports P1, P2. Of the data read from the FiFo section 12-1 and 12-2 for speed conversion corresponding to the ports P1 and P2 for writing the reception time information to the packet data of No. Delete received time information And a multiplexing unit 13 for multiplexing by adding a tag capable and identifies the port P1, P2.

Further, the multiplexing unit 13 of the transmitting unit is a SONET / S
The payload of the DH frame has a structure in which data with a tag for identifying a port is multiplexed and inserted, and the reception time information has a multi-byte structure so that the beginning of the reception time information can be distinguished from the beginning of other bytes. A FiFo section 12-1, 12- is added by adding a head identification bit to the head of each byte.
2, the reception time information is read based on the leading identification bit, the reception time information of the packet data corresponding to the port is compared, and the FiFo unit 12
-1, 12-2 is configured to read data. Further, the FiFo units 12-1 and 12-2 have a control configuration that starts reading from a time at which the read address does not pass the write address of the data, based on the difference between the reception time information and the current time information. I have.

Further, the multiplex transmission apparatus of the present invention has a transmission section for transmitting the data multiplexed on the transmission path 3 and a reception section for demultiplexing the data received via the transmission path 3, and the transmission section Includes a multiplexing unit 13 that multiplexes data to which a tag that can identify a plurality of ports is added. The receiving unit detects a tag and identifies a port, and a selection signal generating unit that selects a selector. It is configured to control and input the data separated for each port to the FiFo unit for speed conversion.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory view of an embodiment of the present invention, in which 1-1 to 1-4 are nodes (POS), 2a,
2b is a terminal, 3 is a transmission line, 4 is a physical layer part, 5 is a router,
Reference numeral 6 indicates a server, and 7 indicates a layer 2 switch unit (L2SW). Further, the nodes 1-1, 1-3 and 1-4 are connected to the port P
1, two terminals 2a and 2b are connected to P2, and node 1-
2, the server 6 is connected via the layer 2 switch unit 7, the physical layer unit 4, and the router 5 to the other nodes 1-1, 1-3, and 1-4 with respect to the node 1-2. OC between
When data is transmitted by the PPP connection with the transmission rate of −3, the transmission path 3 has, for example, an OC-12 transmission band of (OC-3) × 4.

Further, when two terminals 2a and 2b are connected to the nodes 1-1, 1-3 and 1-4, respectively, assuming that the average transmission rate of each is 78 Mbps, by multiplexing, 156 Mbps is obtained. It becomes the transmission speed. That is,
The bandwidth of 156 Mbps, which is shown in a pipe shape below, is (78
Mbps) × 2 = 156 Mbps, which can be effectively used. Therefore, the ports P1 and P2 to which the terminals 2a and 2b are connected are multiplexed so that they can be identified. Also, in the multiplexing process, SONET /
By performing a multiplexing process on the SDH format payload, the time sequence can be maintained.

FIG. 2 is an explanatory view of a main part of a transmission unit of a node according to the embodiment of the present invention, in which 1 is a node (POS) and 4-
Numerals 1 and 4-2 are physical layers connecting the transmission line FE on the terminal side to the ports P1 and P2, and numerals 11-1 and 11-2 are conversion processing for performing processing such as reception time byte addition, preamble detection, and serial / parallel conversion. The parts 12-1 and 12-2 are Fi for speed conversion.
Fo (First in First out) section, 1
Reference numeral 3 denotes a multiplexing unit that adds the numbers of the ports P1 and P2 as tags and multiplexes, 14 an insertion unit that is inserted into the payload of the SONET / SDH frame, 15 a transmission interface unit that transmits at the transmission speed of OC-3, 16 Is a selection signal generation unit that controls the FiFo unit, and 17 is a clock unit that adds current time information to the conversion processing units 11-1 and 11-2.

The node 1 shown in FIG. 2 corresponds to the configuration of the nodes 1-1, 1-3, 1-4 in FIG. 1, and is, for example, 78 Mbps from two terminals via the transmission line FE. In the case where packets in the transmission band are input to ports P1 and P2, port numbers are added to the packets, the packets are multiplexed, the packets are inserted into the payload of the SONET / SDH frame in the band of 156 Mbps, and are transmitted as OC-3 from the transmission interface unit 15. Show.

The conversion processing units 11-1 and 11-2 detect the preamble of the packet input from the terminal to the physical layer units 4-1 and 4-2 via the transmission line FE, and the clock unit 17 detects the preamble. Time information is added as reception time information,
Serial / parallel conversion is performed and the result is input to the FiFo units 12-1 and 12-2. The selection signal generation unit 16 compares the reception time information, starts reading from the FiFo unit for the previously received packet, and inputs the packet to the multiplexing unit 13. Multiplexer 13
Adds a tag that can identify the ports P1 and P2 corresponding to either of the FiFo units 12-1 and 12-2, deletes the reception time information and multiplexes, and the insertion unit 14 uses SONET /
It is inserted into the payload of the SDH frame, and the transmission interface unit 15 converts it into an optical signal and sends it out to the transmission line at the transmission speed of OC-3.

FIG. 3 is an explanatory view of a main part of the receiving section of the node according to the embodiment of the present invention, which corresponds to the configuration of the receiving section of the node 1-2 of FIG. 1 and which has nodes 1-1 and 1-3. , 1-4 (Point-to-Point Protocol)
2 shows a configuration for data transmission by. Therefore, it includes three systems of reception interface units 21-1 to 21-3, extraction units 22-1 to 22-3, and separation units 23-1 to 23-3, each of which corresponds to two terminals. FiFo part 2
4-1 to 24-6 are included. Separating section 23-1
23-3 extracts the respective tags, identifies the port numbers corresponding to the terminals, distributes and inputs them to the FiFo units 24-1 to 24-6, converts the speed, inputs them to the layer 2 switch unit 7, and multiplexes them. High-speed LAN (Gb
Transfer via E). It should be noted that although the case of three systems of OC-3 is shown, when data transmission with four nodes in the band of OC-12 is performed, the configuration of four systems of OC-3 is used.

FIG. 4 is an explanatory view of the main part of the transmission unit of the node according to the embodiment of the present invention, which corresponds to the configuration of the transmission unit of the node 1-2 of FIG. 1 and the configuration of the reception unit shown in FIG. Correspondingly, 3
System transmission interface units 35-1 to 35-3, insertion units 34-1 to 34-3, and multiplexing units 33-1 to 33-3
And a terminal-compatible FiFo unit 32-1 to 32-
6 and conversion processing units 31-1 to 31-6. Reference numeral 36 denotes a selection signal generator having the same function as that of the selection signal generator 16 shown in FIG. 2, and reference numeral 37 denotes a clock unit having the same function as the clock unit 17 shown in FIG. In this case, this corresponds to the case where the function of the transmitting unit shown in FIG. 2 is provided in three systems, and in the case of data transmission to and from four nodes in the band of OC-12, the configuration of four systems of OC-3 is adopted. It will be.

FIG. 5 is an explanatory diagram of a packet data format. FIG. 5A shows a structure in which a tag (Tag) for identifying a port based on a port number or the like is added in a multiplexing unit, and SPD, PR (Preamble). , SFD (S
start frame delimiter), DA
(Destination Address; destination address), SA (Source Address; source address), length / type, Tag, data area, F
The case where it has a CS (Frame Check Sequence) configuration is shown. Further, (B) is the reception time information TI
The structure in which M is added is shown, and the reception time information TIM is added to the head of the structure excluding the tag in the frame structure shown in (A) in the conversion processing unit based on the current time information from the clock unit. Indicates. In addition, it is general that the SPD, PR, and SFD are collectively referred to as a preamble.

The tag Tag is x (= 1, 2, 3, ...)
When the tag Tag and the reception time information TIM each have a 1-byte structure, for example,
In the conversion processing units 11-1 and 11-2 shown in FIG. 2, the current time information from the clock unit 17 is added to the packet data input from the physical layer units 4-1 and 4-2, respectively.
As the IM, it is added to the beginning as shown in FIG. Then, for example, serial / parallel conversion is performed in 1-byte units, and F
Parallel writing is performed to the iFo units 12-1 and 12-2. The selection signal generation unit 16 compares the reception time information of the packet data written in the FiFo units 12-1 and 12-2, reads the reception time from the previous packet data, adds it to the multiplexing unit 13, and then receives it. The packet data with a later time is read and added to the multiplexing unit 13.

The multiplexing section 13 deletes the reception time information TIM, and a tag Tag for identifying which of the FiFo sections 12-1 and 12-2 is the data is shown in FIG.
Add as shown in. Then, at the insertion portion 14,
Inserted in the payload of SONET / SDH frame.
In this case, in the payload of OC-156 of 156 Mbps,
Packet data of 78 Mbps is multiplexed and inserted.

On the receiving side, for example, a receiving section corresponding to the OC-3 configuration of one system in FIG. 3 will be explained. In the extracting section 22-1, data is extracted from the payload of the SONET / SDH frame. The FiFo units 24-1 and 24-24 are extracted and based on the tag Tag in the separating unit 23-1.
Distribute into 2. That is, the tag Tag can separate the respective packet data corresponding to the two terminals.

FIG. 6 is an explanatory diagram of the FiFo section. In the conversion processing section 11-1, 11-2, 31-1 to 31-6, the reception time information TIM of 1 byte is converted into a packet of n byte. The data is added to the data, serial-parallel conversion is performed in byte units, and the FiFo units 12-1, 12-2, 32-1 to 32-
The state written in 6 is shown. Maximum packet data is 152
It can have a 6-byte structure. And the multiplexing unit 1
3, 33-1 to 33-3 read from the FiFo unit in the ascending order of the reception time information TIM, delete the reception time information TIM, add a tag Tag, and multiplex.

FIG. 7 is an explanatory diagram of the transmission control configuration according to the embodiment of the present invention. The same reference numerals as those in FIG. 2 indicate the same parts, and the insertion section 14 and the transmission interface section 15 in FIG. 2 are not shown. Omitted. In FIG. 7, 41-1 and 41-
Reference numeral 2 is a deletion unit that deletes the head identification bit and reception time information, 42-1 and 42-2 are insertion conversion units that insert the tag Tag and perform parallel-serial conversion, and 43 is a selector.
Further, the selection signal generation unit 16 has a configuration including a clock unit, and inputs current time information T1, T2 (T1 = T2) to the conversion processing units 11-1, 11-2, respectively. Also WE1,
WE2 is a write enable signal, RE1 and RE2 are read enable signals, EP1 and EP2 are empty signals, WCLK is a write clock signal, RCLK is a read clock signal, and SE is a selection signal.

In this embodiment, the conversion processing unit 1
To 1-1 and 11-2, packet data is input from a terminal (not shown) via the physical layer unit, and area signal 1 and area signal 2 indicating the physical layer unit are input. The conversion processing units 11-1 and 11-2 detect the preamble PR of the received packet data, and configure the reception time information into m bytes based on the current time information T1 and T2 from the clock unit of the selection signal generation unit 16. , And a head identification bit indicating the head of each byte is added, the data is converted into parallel data in 9-bit units, input to the FiFo units 12-1 and 12-2, and write enable signals WE1 and WE2 are added. FiFo part 1
The data is input to 2-1 and 12-2 to write parallel data. In this case, the head identification bit is set to "1" only for the head byte of the reception time information, and the heads of other bytes are set to "0". Therefore, the 8-bit unit packet data shown in FIG. 6 is converted into 9-bit unit parallel data.

The FiFo units 12-1 and 12-2 write 9-bit parallel data from the conversion processing units 11-1 and 11-2 in parallel according to the write clock signal WCLK by the write enable signals WE1 and WE2. And the read enable signal RE1, from the selection signal generation unit 16
The RE2 performs parallel reading according to the read clock signal RCLK to perform speed conversion. And the multiplexing unit 1
3 to the deletion units 41-1 and 41-2. In addition, the selection signal generation unit 16 reads out the reception time information written in the FiFo units 12-1 and 12-2 based on the head identification bit and compares the received time information with each other in order to read out the previously received packet data first. , Read enable signals RE1 and RE2 are added.

Further, the deletion units 41-1 and 41-2 of the multiplexing unit 13
Removes the head identification bit of the parallel data of 9-bit configuration read from the FiFo units 12-1 and 12-2 to form an 8-bit configuration, and deletes the reception time information. Further, the insertion conversion units 42-1 and 42-2 insert the tag Tag, perform parallel-serial conversion, and input to the selector 43. The selector 43 selects either one of the insertion conversion units 42-1 and 42-2 according to the selection signal SE from the selection signal generation unit 16, and the SON
It is multiplexed and inserted into the payload of the ET / SDH frame.

FIG. 8 is an explanatory diagram of the selection signal generator according to the embodiment of the present invention. The same reference numerals as those in FIGS. 2 and 7 denote the same parts, 51 is a signal generator, and 52-1, 52-2. Is a time holding unit, 53 is a time comparing unit, 54 is a selector (SE
L), 55 is a determination unit, 56 is a timer, and 57 is an AND circuit (&).

The timer 56 of the selection signal generation unit 16 corresponds to the clock unit 17 described above, counts a reference clock signal (not shown), and uses the count value as time information for the conversion processing units 11-1 and 11-2. In addition to the conversion processing unit 11-
1 and 11-2 are added to the packet data as reception time information. When both the FiFo sections 12-1 and 12-2 are in the empty state, the empty signals EP1 and EP1
Each of P2 becomes "1", the signal of "1" from the AND circuit 57 is applied to the reset terminal RST of the timer 56, the timer 56 is reset to the initial state, and the counting of the reference clock signal is started.

Further, the time holding units 52-1 and 52-2 have Fi
The reception time information of the packet data written in the Fo units 12-1 and 12-2 is read and temporarily held, and compared in the time comparison unit 53, and the comparison output signal is compared with the selector 54 and the signal generation unit 51. In addition, the selector 54 selects the reception time information having the earlier reception time when the reception time information is the same, according to a predetermined priority, and inputs the reception time information to the determination unit 55. The determination unit 55, based on the reception time information from the selector 54 and the current time information from the timer 56,
It is determined whether or not overtaking of reading occurs because the reading speed is higher than the writing speed in the FiFo units 12-1 and 12-2, and when it is determined that overtaking does not occur, the signal generating unit 51 is controlled. Add a signal. Thereby, the signal generator 51
Is the FiFo unit 12-1, 12-2 whose reception time is earlier.
Is selected to add either of the read enable signals RE1 and RE2, and a selection signal SE for controlling the selector 43 (see FIG. 7) is output.

FIG. 9 shows an example of the data accumulated in the FiFo section, and the conversion processing sections 11-1 and 11-2 (see FIGS. 7 and 8) perform parallel conversion in units of 8 bits, and The case where the head identification bit is added to form a 9-bit structure and the reception time information has an m-byte structure is shown. As for the start identification bit, only the start of the reception time information has the start identification bit set to “1” and the other start identification bits set to “0”.

Further, the maximum packet data is 1526 bytes, the reception time information is stored in the addresses 1 to m of the FiFo section, and the packet data is stored in m + 1 to m + n.
The reception time information of the next packet data is stored in + n + 1 to m + n + m. Then, the time holding unit 52-
1, 52-2 (see FIG. 8) can identify the head of the reception time information by the head identification bit of “1”, so m bytes are read from the FiFo units 12-1 and 12-2 and held, It is added to the comparison unit 53 and the selector 54.

FIG. 10 shows an outline of the writing operation to the FiFo section. The current time by the timer is 1000,10.
.., and the write clock signal WCLK to the FiFo section is for writing parallel data. The area signal is, for example, the physical layer 4-
This is for identifying the data area from 1, 4-2 (see FIG. 2) and shows either the area signal 1 or the area signal 2 in FIGS. 7 and 8.

The write enable signal WE is one of the write enable signals WE1 and WE2 shown in FIGS. Also, the received packet data is serial data SD, the same symbols as the symbols of the frame format shown in FIG. 5 indicate the same contents, and the conversion processing units 11-1 and 11
2 shows serial data input to any of the two. This 8
The parallel data PD converted in parallel bit by bit is shown in outline corresponding to the serial data SD. IPG represents an inter packet gap and is deleted as parallel data PD.

Further, the reception time information added to the write data WD for the FiFo section is 4 when m = 4 in FIG.
In the case of a byte structure, for example, when the current time information of the timer is "1000", this is added as reception time information before the preamble of the packet data as indicated by the arrow. Further, a leading identification bit of "1" is added to the beginning of the first byte of this reception time information, and a leading identification bit of "0" is added to the beginning of each of the other bytes. Therefore, FiF
The write data WD stored in the o part is m in FIG.
The reception time information with = 4 is added to the beginning.

FIG. 11 is an explanatory view of the reception time comparison processing, the same reference numerals as those in FIG. 8 indicate the same signals, and F1 and F2 indicate the data written in the FiFo units 12-1 and 12-2. For example, as shown in FIG. 9, packet data with reception time information added is stored. The holding time information indicates the receiving time information held in the time holding units 52-1 and 52-2.

From the conversion processing unit 11-1 (see FIG. 7) to Fi
The parallel data is written in the Fo unit 12-1, and the reception time information by the head identification bit of "1" is read by m = 4 bytes and held in the time holding unit 52-1. The case where “723” is held as the held reception time information in this case is shown. When parallel data is written from the conversion processing unit 11-2 to the FiFo unit 12-2, the signal generation unit 51 outputs m = 4.
Until the reception time information of the byte is read, the read enable signal RE2 is applied to the FiFo unit 12-2, and the reception time information by the leading identification bit of "1" is read by m = 4 bytes and held in the time holding unit 52-2. To do. In this case, "13
The case where the reception time information of "46" is held is shown.

Then, the time comparing unit 53 includes the time holding unit 5
The reception time information held in 2-1 and 52-2 is compared. In this case, since 723 <1346, the packet data accumulated in the FiFo unit 12-1 has arrived first. Therefore, the FiFo unit 12
The read enable signal RE1 is added to -1 and the selection signal SE for controlling the selector is set to "0" to select the FiFo unit 12-1 side. As a result, the FiFo unit 12-
The parallel data read from 1 is transferred to the multiplexer.

FIG. 12 is an explanatory diagram of the reading process, and FIG.
The same reference numerals as in FIG. The read timer is 5
In the case of being configured by a 63-ary counter, a case including a process of determining whether the difference between the reception time information and the current time information is “562” or more is shown. That is, the FiFo unit 12-1,
Since 12-2 (see FIGS. 7 and 8) has a function of performing speed conversion of low-speed data into high-speed data, reading may overtake writing. It is necessary to avoid such a situation. Therefore, as shown in FIG. 8, a determination unit 55 is provided to determine whether or not the reading is started based on the difference between the reception time information and the current time information.

For example, "508" is held as the reception time information in the time holding unit 52-1 and the time holding unit 52-2
Assuming that “750” is stored as the reception time information, the time comparison unit 53 selects F2 from the selected state of the FiFo unit 12-2, that is, F1 selection, that is, the relation of 508 <750. The FiFo unit 12-1 is selected, and the selector 54 selects the reception time information held in the time holding units 52-1 and 52-2 in response to the F1 selection and the F2 selection and determines the determination unit 55. To enter. In this case, when F1 is selected, the reception time information held in the time holding unit 52-1 is added to the determination unit 55.

The determination unit 55 determines the difference between the current time information from the timer 54 and the reception time information from the time holding unit 52-1 and determines whether or not the read will overtake. That is, if the reception time information is “508” and the current time information is “1067”, the difference is “55”.
9 ". However, since the condition is "562" or less, which is a condition that no overtaking occurs, the determination unit 55 presets the difference "559" to the read timer and starts counting, and the count content of the read timer is "56".
When it becomes "2", reading from the FiFo unit 12-1 is started. The read timer in this case counts the same clock signal as the timer 56 (see FIG. 8).
The determination unit 55 can be provided. Therefore, even if the data is received earlier, the reading can be started after the waiting shown as WAIT so that the reading does not pass.

FIG. 13 is an explanatory diagram of the reading process of the FiFo section, showing a case where the reading is selected by comparing the reception times of the FiFo sections 12-1 and 12-2, and arrow 1 indicates F.
It indicates that the iFo unit 12-2 is selected and read.
The arrow 0 indicates that the FiFo unit 12-1 is selected and read. In addition, like data 1-1 and 2-1,
When the reception times T0 are the same, for example, the case where the FiFo unit 12-1 is selected as the priority order is shown. When the reading of the data 1-1 is completed, the reading of the data 2-1 is started, and when the reading of the data 2-1 is completed, T6 <T18.
And T14 <T18, the data 1-2 is read, then the data 1-3 is read, and then T23> T18.
The data 2-2 is read according to the relationship. That is, by selecting and reading from the earliest receiving time based on the receiving time information, it is possible to maintain the time sequence of the data from the two terminals and perform multiplexing.

FIG. 14 is an explanatory diagram of the multiplexing process.
(A) shows the FiFo units 12-1 and 12-2 as F1 and F2.
, And SONET / S of 125 μs per frame
The read data RD when multiplexed in the DH frame is shown. Further, (B) shows the relationship between the writing speed and the reading speed. If the writing speed is 100 Mbps, the reading speed is 156 Mbps, and the maximum data amount is 1526 bytes, FiFO
The condition that the reading does not overtake the writing in the units 12-1 and 12-2 is the time Td = 45 μs from the writing start to the reading start.

Then, as indicated by F1 in FIG. 14A, packet data 1, 3, and 3 are stored in the FiFo section 12-1.
4, 6, 7, 11, ... Are input and accumulated, and F
2, the packet data 2, 5, 8, 9, 10, 12, ... Is input to and accumulated in the FiFo unit 12-2, and the packet data 2, 5, and 7 are the maximum data amount of 1526 bytes. Shows the case. Then, for the packet data 1 and 2 having the same reception time T0, for example, the selection signal for selecting the FiFo unit 12-1 side is “0” according to the priority order, and at that time, the current time information and the packet data 1 are received. When the difference from the time information is equal to or less than the waiting time Td, the read will pass, so the packet data 1 is read from the FiFo unit 12-1 after the waiting time Td, and the tag Tag0 is added to this packet data 1. Then, next, the selection signal becomes "1", the packet data 2 is read from the FiFo unit 12-2, and the tag Ta is added to this packet data 2.
Add g1.

The reception time information of the packet data 3 and 4 is T6 and T14, and the reception time information of the packet data 5 is T1.
In 8, the packet data 3 and 4 are received earlier, so the selection signal becomes “0” after reading the packet data 2,
When the packet data 3 is read from the FiFo unit 12-1, the tag Tag0 is added to this packet data 3, and the difference between the reception time information T14 of the next packet data 4 and the current time information is Td or less, the reception time information T14. At the present time when Td is added to the packet data 4, the reading of the packet data 4 is started, and the tag Tag0 is added to the read packet data 4.

In the same manner, the FiFo units 12-1, 1
2-2 is selected according to the selection signal, and the tag Tag is added to the read packet data to form the read data RD, which is inserted into the payload of the SONET / SDH frame and transmitted to the transmission path.

FIG. 15 is an explanatory view of the main part of the receiving part.
Is a separation unit, 72 is a PR (preamble) detection unit, 73 is a selection signal generation unit, 74 is a deletion unit, 75 is a selector, 76
Reference numerals -1, 76-2 indicate FiFo parts. The separating unit 71 corresponds to the configuration of the separating units 23-1 to 23-3 in FIG.
The FiFo units 76-1 and 76-2 are the FiF in FIG.
This corresponds to the configuration of the o parts 24-1 to 24-6.

Since the packet data including the preamble PR is multiplexed and transmitted, the multiplexed data is extracted from the SONET / SDH frame payload,
In the PR detector 72, the preamble PR is detected,
Based on the detection signal, the selection signal generation unit 73 detects the tag Tag added after the predetermined number of bytes of the preamble PR, and in the case of Tag0, controls the selector 75 to control Fi.
The Fo unit 76-1 side is selected, and in the case of Tag1, the selector 75 is controlled to select the FiFo unit 76-2 side. The deleting unit 74 includes a function of deleting the tag Tag and a function of the shift register, compensates the processing time required by the PR detecting unit 72 and the selection signal generating unit 73, and inputs the compensated time to the selector 75.

Further, the FiFo units 76-1 and 76-2 write the data selected by the selector 75 in accordance with the write clock signal WCLK and read the read clock signal RCL.
It is possible to read out according to K, perform speed conversion, and restore demultiplexed packet data. That is, demultiplexing can be performed using the tag Tag.

FIG. 16 is an explanatory diagram of the demultiplexing process.
15A is data to which the tag Tag is input, which is input to the separation unit 71 in FIG. 15, FIG. 15B is data that is input to the FiFo unit 76-1, and FIG. 15C is input to the FiFo unit 76-2. Show the data. Tag Tag0 data 1, 3, 4,
As shown in (b), 6, 7, and 11 are FiFo units 76.
It is input to -1, written according to the write clock signal WCLK, read according to the read clock signal RCLK, and subjected to speed conversion. Similarly, the data 2, 5, 8, 9, 10, 12 of the tag Tag1, as shown in (c),
It is input to the FiFo unit 76-2, written according to the write clock signal WCLK, and read into the read clock signal RCL.
It is read according to K and the speed is converted.

The above-described embodiment shows the case of multiplexing and demultiplexing into SONET / SDH frames corresponding to two ports to which two terminals are respectively connected, but three or more terminals are respectively connected. For 3 or more ports,
It is also possible to multiplex and demultiplex SONET / SDH frames, in which case the tags Tag0, Tag.
, Tag2, ..., And tags for port identification are added and multiplexed to enable demultiplexing corresponding to ports. Fi for speed conversion corresponding to port
Since the Fo unit is provided, when multiplexing is performed, the reception time information is compared with each other, and the data is read and multiplexed in ascending order of time.

[0055]

As described above, the present invention provides a multiplex transmission system and a multiplex transmission apparatus having various network configurations in which a plurality of nodes 1-1 to 1-4 are connected via a transmission line 3. Then, the transmission units of the nodes 1-1 to 1-4 are
SONET with a tag that can identify multiple ports
/ SDH frame is multiplexed in the payload, and the receiving unit can identify the tag and demultiplex corresponding to the port accordingly. In addition, when multiplexing, add the reception time information to the reception packet data corresponding to the port,
Since reading from the FiFo unit for speed conversion is performed by selecting from the earliest receiving time and reading and multiplexing, the time sequence for the receiving side can be maintained.
Therefore, there is an advantage that the multiplexing and demultiplexing can be facilitated and the multiplexed transmission can be effectively performed.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a main part of a transmission unit of a node according to the embodiment of this invention.

FIG. 3 is an explanatory diagram of a main part of a reception unit of a node according to the embodiment of this invention.

FIG. 4 is an explanatory diagram of a main part of a transmission unit of a node according to the embodiment of this invention.

FIG. 5 is an explanatory diagram of a packet data format.

FIG. 6 is an explanatory diagram of a FiFo unit.

FIG. 7 is an explanatory diagram of a transmission control configuration according to the embodiment of this invention.

FIG. 8 is an explanatory diagram of a selection signal generation unit according to the embodiment of this invention.

FIG. 9 is an explanatory diagram of a FiFo unit to which a leading identification bit is added.

FIG. 10 is an explanatory diagram of a write operation.

FIG. 11 is an explanatory diagram of a reception time comparison process.

FIG. 12 is an explanatory diagram of a reading process.

FIG. 13 is an explanatory diagram of a reading process of a FiFo unit.

FIG. 14 is an explanatory diagram of multiplexing processing.

FIG. 15 is an explanatory diagram of a main part of a receiving unit.

FIG. 16 is an explanatory diagram of demultiplexing processing.

FIG. 17 is an explanatory diagram of a ring network.

FIG. 18 is an explanatory diagram of a SONET / SDH frame format.

FIG. 19 is an explanatory diagram of a main part of a transmission unit of a node.

FIG. 20 is an explanatory diagram of a main part of a reception unit of a node.

[Explanation of symbols]

1-1 to 1-4 nodes 2a, 2b terminals 3 transmission lines 4 Physical layer 5 routers 6 servers 7 Layer 2 switch part 11-1, 11-2 conversion processing unit 12-1, 12-2 FiFo part 13 Multiplex section 14 Insert 15 Transmission interface section 16 Selection signal generator 17 Clock Department 21-1 to 21-3 Reception interface unit 22-1 to 22-3 Extractor 23-1 to 23-3 Separation unit 24-1 to 24-6 FiFo part

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroshi Fukaya             2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa             Issue Fujitsu Digital Technology Stock Association             In-house (72) Inventor Yutaka Hayama             2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa             Issue Fujitsu Digital Technology Stock Association             In-house (72) Inventor Satoru Aoki             2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa             Issue Fujitsu Digital Technology Stock Association             In-house F term (reference) 5K028 AA11 CC06 EE05 KK05 KK32                       MM08 RR03 SS26                 5K030 HA08 HB15 JA01 JL10                 5K031 CB19 DB11

Claims (5)

[Claims] 1. A plurality of nodes are connected via a transmission path, and packet data from a plurality of ports are speed-converted and multiplexed to be sent to the transmission path, and the multiplexed data is transmitted from the transmission path. In a multiplex transmission system for receiving and demultiplexing corresponding to the port, the node demultiplexes data transmitted through the transmission line and a transmission unit for transmitting data multiplexed over the transmission line. A reception unit, wherein the transmission unit adds a reception time information to packet data from a plurality of ports and writes the reception time information to each port, and a speed conversion FiFo unit corresponding to the port; A multiplexing transmission system, comprising: a multiplexing unit that deletes the reception time information of the data read from the FiFo unit and multiplexes by adding a tag that can identify the port. Mu. 2. The multiplexer of the transmitter is SONET.
2. The multiplex transmission system according to claim 1, wherein the payload of the / SDH frame has a configuration in which data with a tag for identifying the port is multiplexed and inserted. 3. The reception time information is composed of a plurality of bytes, and a head identification bit for distinguishing the head of the reception time information from the heads of other bytes is added to the head of each byte to set the F
Write to the iFo section, read the reception time information based on the leading identification bit, compare the reception time information of the packet data corresponding to the port, and read the data from the FiFo section in order from earliest reception time information. 3. The multiplex transmission system according to claim 1, which has a configuration. 4. The FiFo unit has a control configuration for starting reading from a time at which a read address does not overtake a write address of data based on a difference between the reception time information and the current time information. Claim 1 characterized by the above.
Alternatively, the multiplex transmission system according to 2 or 3. 5. A plurality of nodes are connected via a transmission line, and packet data from a plurality of ports are speed-converted and multiplexed to be sent to the transmission line, and the multiplexed data is transmitted from the transmission line. In a multiplex transmission device that receives and demultiplexes data corresponding to the ports, a transmission unit that sends out the data multiplexed on the transmission line and a reception unit that demultiplexes the data received via the transmission line. The transmitting unit includes a multiplexing unit that multiplexes data to which a tag that can identify a plurality of ports is added, the receiving unit includes a selection signal generating unit that detects a tag and identifies a port, and The selector is controlled by the selection signal generator, and the data separated for each port is converted into a FiF for speed conversion.
A multiplexing transmission apparatus having a configuration for inputting to an o section.