JP2003324405A - Multiplexer and demultiplexer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate the necessity to design multiplexers different in multiplexing level within a range where a multiplexing level is variable by varying the multiplexing level in a multiplexer serializing parallel digital transmitting signals. <P>SOLUTION: D-FF (FF cascade connected with two D latches) 216 and 220 are made into configuration (controlled D-FF) controllable to be function as D-FFs or as buffers. P-FF (FF cascade connected with three D latches) 217 and 221 are made into configuration (controlled P-FF) controllable to be functioned as P-FFs or to maintain a latched state. Selectors 218 and 222 are made into configuration (controlled selector) controllable to be functioned as selectors or as buffers with respect to an output from the D-FF 216. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexer for serializing parallel digital transmission signals and a demultiplexer for parallelizing serial digital transmission signals.

In an optical communication system using an optical fiber, an electric time division multiplexing technique (ETDM) is adopted as a technique for increasing the transmission capacity, and a transmitter transmits digital transmission signals of a plurality of channels by a time division multiplexing of a single channel. Requires a multiplexer to convert to a digital transmission signal,
The receiver requires a demultiplexer to convert the time division multiplexed digital transmission signal back to the original multi-channel digital transmission signal. The multiplexer and demultiplexer of the present invention are suitable for use in such an optical communication system.

[0003]

2. Description of the Related Art (First Conventional Example of Multiplexer ... FIG. 1)
3 to 17) FIG. 13 is a circuit diagram showing a main part of a first conventional example of a multiplexer. The first conventional example of this multiplexer is a 2: 1 multiplexer that converts a two-channel digital transmission signal input in parallel into a single-channel digital transmission signal that is time-division multiplexed.

In FIG. 13, 1 is a digital transmission signal input terminal for inputting a first channel digital transmission signal DATA0 (for example, 10 Gbps), and 2 is a second channel digital transmission signal DATA1 (for example, 10 Gbps). Is a digital transmission signal input terminal for inputting a clock CLK (for example, 10 GHz).

Reference numeral 4 is a digital transmission signal DA of the first channel.
A buffer provided corresponding to TA0, 5 is a buffer provided corresponding to the digital transmission signal DATA1 of the second channel, and 6 and 7 are buffers provided corresponding to the clock CLK.

Reference numeral 8 is composed of two D latches connected in series,
This is a so-called master / slave type D flip-flop (hereinafter, simply referred to as D flip-flop), and the first channel digital transmission signal DA output from the buffer 4.
It is provided corresponding to TA0.

9 is formed by connecting three D latches in series,
This is a so-called master-slave-master type D flip-flop (hereinafter referred to as P flip-flop), which is provided corresponding to the second channel digital transmission signal DATA1 output from the buffer 5.

Reference numeral 10 designates the digital transmission signal DATA0 of the first channel output from the D flip-flop 8 and the P flip-flop 9 using the clock CLK as a selection control signal.
Second channel digital transmission signal DAT output from
It is a selector which alternately selects A1 and outputs a digital transmission signal DATA01 obtained by time-division multiplexing the digital transmission signals DATA0 and DATA1 of the first and second channels.

Reference numeral 11 denotes a buffer provided corresponding to the time division multiplex digital transmission signal DATA01 output from the selector 10, and reference numeral 12 denotes a buffer provided corresponding to the time division multiplex digital transmission signal DATA01 output from the buffer 11. This is the digital transmission signal output terminal.

FIG. 14 is a circuit diagram showing a configuration example of the D flip-flop 8. In FIG. 14, GND is a ground power source, VS
S is a negative power source, D is a data input terminal, ND is a negative phase data input terminal, C is a clock input terminal, NC is a negative phase clock input terminal, 13 and 14 are cascaded D latches, Q is a data output terminal, NQ is a reverse phase data output terminal.

Further, in the D latch 13, 15 to 25
Are transistors, 26-28 are diodes, 29-33
Are resistors, 34 and 35 are inductors, and 36 and 37 are capacitors. In the D latch 14, 38 to 48 are transistors, 49 to 51 are diodes, 52 to 56 are resistors, 57 and 58 are inductors, and 59 and 60 are It is a capacitor. Note that VC1 and VC2 are bias voltages.

In this example, the first channel digital transmission signal DATA0 is applied to the data input terminal D, the first channel negative phase digital transmission signal / DATA0 is applied to the negative phase data input terminal ND, and the clock input is performed. The clock CLK is applied to the terminal C, and the negative phase clock input terminal NC
A reverse-phase clock / CLK is applied to.

FIG. 15 is a circuit diagram showing a configuration example of the P flip-flop 9. In FIG. 15, GND is a ground power source, VS
S is a negative power source, D is a data input terminal, ND is a negative phase data input terminal, C is a clock input terminal, NC is a negative phase clock input terminal, 61 to 63 are cascaded D latches, Q is a data output terminal, NQ is a reverse phase data output terminal.

Further, in the D latch 61, 64-74
Is a transistor, 75-77 is a diode, 78-82
Is a resistor, 83 and 84 are inductors, 85 and 86 are capacitors, and in the D latch 62, 87 to 97 are transistors, 98 to 100 are diodes, and 101 to 105.
Are resistors, 106 and 107 are inductors, and 108 and 109
Is a capacitor.

Further, in the D latch 63, 110 to 1
20 is a transistor, 121 to 123 are diodes, 1
24 to 128 are resistors, 129 and 130 are inductors, 1
Reference numerals 31 and 132 are capacitors. In addition, VC1, VC
2 is a bias voltage.

In this example, the second channel digital transmission signal DATA1 is applied to the data input terminal D, the second channel negative phase digital transmission signal / DATA1 is applied to the negative phase data input terminal ND, and the clock input is performed. The clock CLK is applied to the terminal C, and the negative phase clock input terminal NC
A reverse-phase clock / CLK is applied to.

FIG. 16 is a circuit diagram showing a configuration example of the selector 10. In FIG. 16, GND is a ground power supply, VSS is a negative power supply, D1 is a first data input terminal, ND1 is a first negative phase data input terminal, D2 is a second data input terminal, and ND2 is a second.
A reverse phase data input terminal, C is a clock input terminal, and NC is a reverse phase clock input terminal.

Further, 133 to 143 are transistors, 1
44 to 146 are diodes, 147 to 151 are resistors, 1
52 and 153 are inductors, 154 and 155 are capacitors, VC1 and VC2 are bias voltages, Q is a data output terminal, and NQ is a negative phase data output terminal.

In this example, D is applied to the first data input terminal D1.
The first-channel digital transmission signal DATA0 output from the flip-flop 8 is applied, and the first-channel negative-phase digital transmission signal / DATA0 output from the D flip-flop 8 is applied to the first anti-phase data input terminal ND1. To be done.

The second channel digital transmission signal DATA1 output from the P flip-flop 9 is applied to the second data input terminal D2, and the second anti-phase data input terminal ND2 is output from the P flip-flop 9. The second-phase inverted digital transmission signal / DATA1 is applied.

FIG. 17 is a timing chart showing the operation of the first conventional example of the multiplexer shown in FIG.
Are digital transmission signals DATA0 and S2 of the first channel output from the buffer 4, digital transmission signals DATA1 and S3 of the second channel output from the buffer 5, are clocks CLK output from the buffer 6, and S4 is a D flip-flop 8 The digital transmission signal DATA0, S5 of the first channel output from the second digital transmission signal DATA1 of the second channel output from the P flip-flop 9.
S6 is a clock CLK output from the buffer 7, S7
Indicates a time division multiplexed digital transmission signal DATA01 output from the selector 10.

That is, in the first conventional example of the multiplexer, the digital transmission signal DATA0 of the first channel among the digital transmission signals DATA0 and DATA1 of the first and second channels input in parallel is the falling edge of the clock CLK. At the same time, it is latched by the D flip-flop 8 and output from the D flip-flop 8.

The digital transmission signal D of the second channel
ATA1 is latched by the P flip-flop 9 at the falling edge of the clock CLK,
At the next rising timing, that is, the phase is delayed by 1/2 clock (180 °) with respect to the digital transmission signal DATA0 of the first channel output from the D flip-flop 8 and output from the P flip-flop 9. . This is the digital transmission signal DAT in the selector 10.
This is to increase the phase margin when selecting A0 and DATA1.

In the selector 10, the clock CLK
The digital transmission signal DATA0 of the first channel output from the D flip-flop 8 and the digital transmission signal DATA1 of the second channel output from the P flip-flop 9 are alternately selected depending on the voltage level of H level or L level. Then, a single-channel time-division multiplexed digital transmission signal DATA01 having a bit transfer frequency (20 Gbps) twice as high as that of the first and second channel digital transmission signals DATA0 and DATA1 (10 Gbps) input in parallel is output.

(Second Conventional Example of Multiplexer ... FIG. 1)
8) FIG. 18 is a circuit diagram showing a main part of a second conventional example of the multiplexer. The second conventional example of this multiplexer is
The 2: 1 multiplexer is configured in two stages, and the parallel input 4-channel digital transmission signal is converted into a single-channel digital transmission signal by time division multiplexing 4: 1.
It is a multiplexer.

In FIG. 18, 157 is a digital transmission signal input terminal for inputting the digital transmission signal DATA0 (for example, 10 Gbps) of the first channel, and 158 is a digital transmission signal DATA2 (for example, 10 Gbps) of the third channel.
digital transmission signal input terminal for inputting s), 15
Reference numeral 9 denotes a digital transmission signal input terminal for inputting the second-channel digital transmission signal DATA1 (for example, 10 Gbps), and 160 denotes a fourth-channel digital transmission signal DA.
It is a digital transmission signal input terminal for inputting TA3 (for example, 10 Gbps).

Reference numeral 161 denotes a frequency (for example, 10 GH) that is ¼ of the bit transfer frequency of the time division multiplexed digital transmission signal DATA 0123 (for example, 40 Gbps) to be output.
z) a clock input terminal for inputting a clock CLK / 4, 162 inputs a clock CLK / 2 having a frequency (for example, 20 GHz) that is half the bit transfer frequency of the time division multiplexed digital transmission signal DATA 0123 to be output. This is a clock input terminal for

Reference numeral 163 is a first-stage 2: 1 multiplexer provided corresponding to the digital transmission signals DATA0 and DATA2 of the first and third channels. 164 is shown in FIG.
3 is a D flip-flop having the same configuration as the D flip-flop 8 shown in FIG. 3 (FIG. 14), which is provided corresponding to the first channel digital transmission signal DATA0 input from the digital transmission signal input terminal 157. Is.

Reference numeral 165 denotes a P flip-flop having the same configuration as the P flip-flop 9 shown in FIG. 13 (FIG. 15), which corresponds to the third channel digital transmission signal DATA2 input from the digital transmission signal input terminal 158. It is provided by.

Reference numeral 166 is a selector having the same structure as the selector 10 shown in FIG.
D flip-flop 1 using LK / 4 as a selection control signal
First channel digital transmission signal D output from D.
ATA0 and the digital transmission signal DATA2 of the second channel output from the P flip-flop 165 are alternately selected, and the digital transmission signals DATA of the first and third channels are selected.
0 and DATA2 are time-division multiplexed to output a digital transmission signal DATA02. 166A
Is a buffer for adjusting the timing of the selection operation of the selector 166.

Reference numeral 167 is a first-stage 2: 1 multiplexer provided corresponding to the digital transmission signals DATA1 and DATA3 of the second and fourth channels. 168 is shown in FIG.
3 is a D flip-flop having the same configuration as the D flip-flop 8 shown in FIG. 3 (FIG. 14), which is provided corresponding to the second channel digital transmission signal DATA1 input from the digital transmission signal input terminal 159. Is.

Reference numeral 169 denotes a P flip-flop having the same configuration as the P flip-flop 9 shown in FIG. 13 (FIG. 15), which corresponds to the fourth channel digital transmission signal DATA3 input from the digital transmission signal input terminal 160. It is provided by.

Reference numeral 170 denotes a selector having the same structure as the selector 10 shown in FIG.
D flip-flop 1 using LK / 4 as a selection control signal
Digital transmission signal D of the second channel output from 68
ATA1 and the digital transmission signal DATA3 of the fourth channel output from the P flip-flop 169 are alternately selected, and the digital transmission signals DATA of the second and fourth channels are selected.
1 outputs the time-division multiplexed digital transmission signal DATA13 obtained by time-division multiplexing DATA3. Note that 170A is a buffer for adjusting the timing of the selection operation of the selector 170.

171 is a 2: 1 multiplexer 1 in the first stage
The second-stage 2: 1 multiplexer is provided corresponding to the time-division multiplexed digital transmission signals DATA02 and DATA13 output from the reference numerals 63 and 167.

Reference numeral 172 denotes a D flip-flop having the same structure as the D flip-flop 8 shown in FIG. 13 (FIG. 14), which is provided corresponding to the time division multiplexed digital transmission signal DATA02 output from the 2: 1 multiplexer 163. It is what has been.

Reference numeral 173 denotes a P flip-flop having the same configuration as the P flip-flop 9 shown in FIG. 13 (FIG. 15), which is provided corresponding to the time division multiplexed digital transmission signal DATA13 output from the 2: 1 multiplexer 167. It is what has been.

Reference numeral 174 is a selector having the same structure as that of the selector 10 shown in FIG. 13 (FIG. 16).
D flip-flop 1 using LK / 2 as a selection control signal
Time division multiplexed digital transmission signal DAT output from 72
A02 and the time division multiplex digital transmission signal DATA13 output from the P flip-flop 173 are alternately selected, and the digital transmission signals DATA0 of the first to fourth channels are selected.
.About.DATA3 are time-division multiplexed to output a digital transmission signal DATA0123. 174
A is a buffer for adjusting the timing of the selection operation of the selector 174.

175 is a time division multiplexed digital transmission signal DATA012 output from the 2: 1 multiplexer 171.
Digital transmission signal output terminal for outputting 3 to the outside,
176 and 177 are buffers provided corresponding to the time division multiplexed digital transmission signal DATA02 output from the 2: 1 multiplexer 163, and 178 is a monitor of the time division multiplexed digital transmission signal DATA02 output from the 2: 1 multiplexer 163. This is a digital transmission signal output terminal used when

(First Conventional Example of Demultiplexer ... FIG. 1)
9, FIG. 20) FIG. 19 is a circuit diagram showing a main part of a first conventional example of a demultiplexer. The first of this demultiplexer
The conventional example is a digital transmission signal DA of the first and second channels.
Digital transmission signal DATA obtained by time division multiplexing TA0 and DATA1 (for example, 10 Gbps) into a single channel.
It is a 1: 2 demultiplexer that converts 01 (for example, 20 Gbps) into original digital transmission signals DATA0 and DATA1 of the first and second channels.

In FIG. 19, 179 is a digital transmission signal input terminal for inputting the time division multiplexed digital transmission signal DATA01, 180 is a clock input terminal for inputting the clock CLK (10 GHz), and 181 is a digital transmission signal input terminal. A buffer provided corresponding to the time division multiplexed digital transmission signal DATA01 input from 179, and a buffer 182 provided corresponding to the clock CLK input from the clock input terminal 180.

Reference numeral 183 denotes a P flip-flop having the same configuration as the P flip-flop 9 shown in FIG. 13 (FIG. 15), and the digital signal of the first channel included in the time division multiplexed digital transmission signal DATA01 output from the buffer 181. A clock CLK for fetching the transmission signal DATA0
Of the digital transmission signal DATA0 of the first channel is output at the rising timing of the clock CLK.

Reference numeral 184 denotes a D flip-flop having the same structure as the D flip-flop 8 shown in FIG. 13 (FIG. 14), and the digital signal of the second channel included in the time division multiplexed digital transmission signal DATA01 output from the buffer 182. A clock CLK for capturing the transmission signal DATA1
Of the digital transmission signal DATA1 of the second channel is also output at the rising timing of the clock CLK.

185 is a buffer provided corresponding to the first channel digital transmission signal DATA0 output from the P flip-flop 183, and 186 is the second channel digital transmission signal DATA1 output from the D flip-flop 184. It is a buffer provided correspondingly.

Reference numeral 187 denotes a digital transmission signal output terminal provided in correspondence with the first channel digital transmission signal DATA0 output from the buffer 185, and 188 denotes a second channel digital transmission signal DATA1 output from the buffer 186. It is a digital transmission signal output terminal provided correspondingly.

FIG. 20 is a timing chart showing the operation of the first conventional example of the demultiplexer shown in FIG.
8 is a time division multiplexed digital transmission signal DATA01 output from the buffer 181, S9 is a clock CLK output from the buffer 182, and S10 is a P flip-flop 1.
First channel digital transmission signal D output from 83
ATA0 and S11 represent the second-channel digital transmission signal DATA1 output from the D flip-flop 184.

That is, the first conventional example of the demultiplexer is
The time division multiplexed digital transmission signal DATA01 is branched to P
The first signal is input to the flip-flop 183 and the D flip-flop 184 and is included in the time division multiplexed digital transmission signal DATA01 at the falling timing of the clock CLK.
The digital transmission signal DATA0 of the channel is taken into the P flip-flop 183, and the time division multiplexed digital transmission signal DATA0 is acquired at the rising timing of the clock CLK.
Digital transmission signal DATA of the second channel included in 1
By incorporating 1 into the D flip-flop 184,
The first based on the time division multiplexed digital transmission signal DATA01,
Second channel digital transmission signals DATA0, DATA
It is to distribute to one.

(Second Conventional Example of Demultiplexer ... FIG. 2)
1) FIG. 21 is a circuit diagram showing a main part of a second conventional example of a demultiplexer. In the second conventional example of this demultiplexer, the 1: 2 demultiplexer has a two-stage configuration, and digital transmission signals DATA0 to DATA3 of the first to fourth channels are used.
Digital transmission signal DATA 0123 (for example, 10 Gbps) which is time-division multiplexed into a single channel (for example,
It is a 1: 4 demultiplexer for converting 40 Gbps) into the original digital transmission signals DATA0 to DATA3 of the first to fourth channels.

In FIG. 21, reference numeral 189 is a digital transmission signal input terminal for inputting the time division multiplex digital transmission signal DATA0123, and 190 is the time division multiplex digital transmission signal D.
A clock input terminal for inputting a clock CLK / 2 (for example, 20 GHz) having a frequency half the bit transfer frequency of ATA0123, 191 is a quarter of the bit transfer frequency of the time division multiplexed digital transmission signal DATA0123.
Frequency CLK / 4 (eg 10 GHz)
Is a clock input terminal for inputting.

Reference numeral 192 denotes a digital transmission signal input terminal 189.
Time division multiplexed digital transmission signal DATA0 input from
The first-stage 1: 2 demultiplexer provided corresponding to the H.123. 193 is P shown in FIG. 13 (FIG. 15)
This is a P flip-flop having the same configuration as the flip-flop 9, and is a time division multiplexed digital transmission signal DATA 0123 input from the digital transmission signal input terminal 189.
The time-division multiplexed digital transmission signal DATA02 included in the above is fetched at the falling timing of the clock CLK / 2.

Reference numeral 194 denotes a D flip-flop having the same structure as the D flip-flop 8 shown in FIG. 13 (FIG. 14), and when it is included in the time division multiplexed digital transmission signal DATA 0123 input from the digital transmission signal input terminal 189. The division multiplexed digital transmission signal DATA13 is taken in at the rising timing of the clock CLK / 2.

Reference numeral 195 denotes a second-stage 1: 2 demultiplexer provided corresponding to the time division multiplexed digital transmission signal DATA02 output from the P flip-flop 193 of the 1: 2 demultiplexer 192.

Reference numeral 196 denotes a P flip-flop having the same structure as the P flip-flop 9 shown in FIG. 13 (FIG. 15), and the first channel included in the time division multiplexed digital transmission signal DATA02 output from the P flip-flop 193. The digital transmission signal DATA0 is captured at the falling edge of the clock CLK / 4.

Reference numeral 197 denotes a D flip-flop having the same configuration as the D flip-flop 8 shown in FIG. 13 (FIG. 14), and the third channel included in the time division multiplexed digital transmission signal DATA02 output from the P flip-flop 193. The digital transmission signal DATA2 is captured at the rising edge of the clock CLK / 4.

Reference numeral 198 denotes a second stage 1: 2 demultiplexer provided corresponding to the time division multiplexed digital transmission signal DATA13 output from the D flip-flop 194 of the 1: 2 demultiplexer 192.

Reference numeral 199 is a P flip-flop having the same configuration as the P flip-flop 9 shown in FIG. 13 (FIG. 15), and the second channel included in the time division multiplexed digital transmission signal DATA13 output from the D flip-flop 194. The digital transmission signal DATA1 is captured at the falling edge of the clock CLK / 4.

Reference numeral 200 denotes a D flip-flop having the same configuration as the D flip-flop 8 shown in FIG. 13 (FIG. 14), and the fourth channel included in the time division multiplexed digital transmission signal DATA13 output from the D flip-flop 194. The digital transmission signal DATA3 is captured at the rising timing of the clock CLK / 4.

Reference numeral 201 denotes a digital transmission signal output terminal provided corresponding to the digital transmission signal DATA0 of the first channel output from the P flip-flop 196, and 2
Reference numeral 02 denotes a digital transmission signal output terminal provided corresponding to the third-channel digital transmission signal DATA2 output from the D flip-flop 197, and 203 denotes the second-channel digital transmission signal DATA1 output from the P flip-flop 199. Corresponding to the digital transmission signal output terminal, 204 is the D flip-flop 20
Digital transmission signal DA of the fourth channel output from 0
It is a digital transmission signal output terminal provided corresponding to TA3.

205 and 206 are buffers provided corresponding to the time division multiplexed digital transmission signal DATA02 output from the P flip-flop 193 of the 1: 2 demultiplexer 192, and 207 is the P flip-flop 193.
Time-division multiplexed digital transmission signal DATA0 output from
2 is a digital transmission signal output terminal used when 2 is monitored.

[0059]

In the past, in the conventional case, 2:
When one multiplexer is required, for example, the configuration as shown in FIG. 13 is required, and when 4: 1 multiplexer is required, for example, the configuration as shown in FIG. 18 is required. That is, when a multiplexer having a different multiplicity is required, it is necessary to design a multiplexer according to the required multiplicity.

Further, for example, in the second conventional example of the multiplexer shown in FIG. 18, when it is desired to monitor the signal waveform of the output node of the first-stage 2: 1 multiplexer 163, the first-stage 2: 1 multiplexer 163 is used. A layout is required in which the wiring connected to the output node of 1 is branched and the output of the 2: 1 multiplexer 163 in the first stage is transmitted to the digital transmission signal output terminal 178 via the buffers 176 and 177. However, in this case, the branch may disturb the output signal waveform of the 2: 1 multiplexer 163, affecting the original operation of the 4: 1 multiplexer, and increase the number of digital transmission signal output terminals. There are layout disadvantages.

In the prior art, when a 1: 2 demultiplexer is required, for example, it is constructed as shown in FIG. 19, and when a 1: 4 demultiplexer is required, it is shown in FIG. 21, for example. Had to be configured. That is, when a demultiplexer corresponding to time-division multiplexed digital transmission signals having different multiplicities is required, it is necessary to design the demultiplexer according to the multiplicity of the time-division multiplexed digital signals.

Further, for example, in the second conventional example of the demultiplexer shown in FIG. 21, when it is desired to monitor the signal waveform of the output node of the P flip-flop 193 of the first-stage 1: 2 demultiplexer 192, the P flip-flop is used. The wiring connected to the output node of the flip-flop 193, and outputs the output of the P flip-flop 193 to the buffers 205 and 206.
A layout is required so that the signal is transmitted to the digital transmission signal output terminal 207 via. However, in this case, the branch may disturb the output signal waveform of the 1: 2 demultiplexer 192, which may affect the operation of the original 1: 4 demultiplexer, and the number of digital transmission signal output terminals may be reduced. There is a layout-like disadvantage that it increases.

In view of the above points, the present invention is at least
The first object is to provide a multiplexer that does not need to design multiplexers having different multiplicities within a range in which the multiplicity is variable and the multiplicity is variable.
A second object is to provide a demultiplexer in which the degree of distribution is variable and it is not necessary to design demultiplexers having different degrees of distribution within a range in which the degree of distribution is variable.

[0064]

SUMMARY OF THE INVENTION The multiplexer of the present invention is a multiplexer in which 2: 1 multiplexers are connected in multiple stages and functions as a 2: 1 multiplexer for the first and second digital transmission signals. Alternatively, it includes a 2: 1 multiplexer controllable to act as a buffer for the first digital transmission signal.

According to the multiplexer of the present invention, the controllable 2: 1 multiplexer functions as a 2: 1 multiplexer for the first and second digital transmission signals or is buffered for the first digital transmission signals. The multiplicity can be changed by controlling so as to function as.

The demultiplexer of the present invention is a demultiplexer in which 1: 2 demultiplexers are connected in multiple stages, and is a fifth digital transmission signal obtained by time-division multiplexing the third and fourth digital transmission signals. To the 1: 2 demultiplexer or controllable to act as a buffer for the fifth digital transmission signal.
It includes two demultiplexers.

According to the demultiplexer of the invention, the controllable 1: 2 demultiplexer functions as a 1: 2 demultiplexer for the fifth digital transmission signal or is buffered for the fifth digital transmission signal. The degree of distribution can be changed by controlling so as to function as.

[0068]

DETAILED DESCRIPTION OF THE INVENTION Referring to FIGS.
An embodiment of the multiplexer and demultiplexer of the present invention will be described.

(One Embodiment of the Multiplexer of the Present Invention)
1 to 9) FIG. 1 is a circuit diagram showing a main part of an embodiment of the multiplexer of the present invention. One embodiment of the multiplexer of the present invention is a multiplexer in which a 2: 1 multiplexer has two stages, and
It can function as a 4: 1 multiplexer or a 2: 1 multiplexer.

In FIG. 1, 208 to 211 are digital transmission signal input terminals. The digital transmission signal input terminal 208 inputs the digital transmission signal DATA0 of the first channel whether the embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer or a 2: 1 multiplexer. Used to

The digital transmission signal input terminal 209 is used to input the digital transmission signal DATA2 of the third channel when one embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer. Is not used when one embodiment of the MUX is used as a 2: 1 multiplexer.

The digital transmission signal input terminal 210 is used for digital transmission of the second channel regardless of whether the embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer or a 2: 1 multiplexer. Used to input the signal DATA1.

The digital transmission signal input terminal 211 is used to input the digital transmission signal DATA3 of the fourth channel when one embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer. Is not used when one embodiment of the MUX is used as a 2: 1 multiplexer.

Reference numerals 212 and 213 are clock input terminals. The clock input terminal 212 is a time division multiplexed digital transmission signal DATA012 to be output from one embodiment of the multiplexer of the present invention when the one embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer.
A clock CL having a frequency of 1/4 of the bit transfer frequency of 3
It is used to input K / 4 and is unused when one embodiment of the inventive multiplexer is used as a 2: 1 multiplexer.

The clock input terminal 213 is an embodiment of the multiplexer of the present invention, whether the embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer or a 2: 1 multiplexer. It is used to input a clock CLK / 2 having a frequency that is 1/2 the bit transfer frequency of the time division multiplexed digital transmission signal DATA0123 or DATA01 to be output from.

Reference numeral 214 is a multiplicity control signal input terminal for controlling the multiplicity control signal. When one embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer, the multiplicity control signal is set to H level, and when one embodiment of the multiplexer of the present invention is used as a 2: 1 multiplexer. Is set to the multiplicity control signal = L level.

215 is the multiplexer of the present invention, which is 4: 1.
When used as a multiplexer, it functions as a 2: 1 multiplexer, and the multiplexer of the present invention is 2: 1.
When used as a 1-multiplexer, it is the first 2: 1 multiplexer in the first stage, which functions as a buffer for the digital transmission signal DATA0 of the first channel input from the digital transmission signal input terminal 208.

Reference numeral 216 is a controlled D flip-flop which is controllable to function as a D flip-flop or a buffer, and one embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer. In this case, it functions as a D flip-flop that uses the clock CLK / 4 as a synchronization signal for the digital transmission signal DATA0 of the first channel input from the digital transmission signal input terminal 208, and implements the multiplexer of the present invention. When the form is used as a 2: 1 multiplexer, it is controlled to function as a buffer for the digital transmission signal DATA0 of the first channel input from the digital transmission signal input terminal 208.

Reference numeral 217 is a controlled P flip-flop which functions as a P flip-flop or which is controllable so as to be fixed in a latch state. One embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer. Digital transmission signal input terminal 2
09 digital transmission signal D of the third channel
It functions as a P flip-flop that uses the clock CLK / 4 as a synchronization signal for ATA2, and when one embodiment of the multiplexer of the present invention is used as a 2: 1 multiplexer, it is controlled so as to be fixed in a latch state. To be done.

Reference numeral 218 denotes a controlled selector which is controllable to function as a selector or a buffer, and when one embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer, The first control signal is output from the controlled D flip-flop 216 during the L level period and the H level period of the clock CLK / 4 using the clock CLK / 4 as a selection control signal.
The channel digital transmission signal DATA0 and the third channel digital transmission signal DATA2 output from the controlled P flip-flop 217 are alternately selected,
Digital transmission signals DATA0, D of the first and third channels
Digital transmission signal DA obtained by time-division multiplexing ATA2
Outputting TA02, if one embodiment of the inventive multiplexer is used as a 2: 1 multiplexer,
It is controlled so as to function as a buffer for the digital transmission signal DATA0 of the first channel output from the controlled D flip-flop 216. In addition, 21
Reference numeral 8A is a buffer for adjusting the timing of the selection operation of the controlled selector 218.

The multiplexer 219 of the present invention is 4: 1.
When used as a multiplexer, it functions as a 2: 1 multiplexer, and the multiplexer of the present invention is 2: 1.
When used as one multiplexer, it is a second 2: 1 multiplexer of the first stage which functions as a buffer for the digital transmission signal DATA1 of the second channel input from the digital transmission signal input terminal 210.

Reference numeral 220 denotes a controlled D flip-flop that is controllable to function as a D flip-flop or as a buffer, and when one embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer. To the digital transmission signal input terminal 2
2nd channel digital transmission signal D inputted from 10
It functions as a D flip-flop that uses the clock CLK / 4 as a synchronization signal for ATA1, and when one embodiment of the multiplexer of the present invention is used as a 2: 1 multiplexer, it is input from the digital transmission signal input terminal 210. The digital transmission signal DATA1 of the second channel is controlled to function as a buffer.

Reference numeral 221 denotes a controlled P flip-flop which functions as a P flip-flop or can be controlled so as to be fixed in a latch state. One embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer. Digital transmission signal input terminal 2
Digital transmission signal D of the fourth channel input from 11
It functions as a P flip-flop that uses the clock CLK / 4 as a synchronization signal for the ATA3, and when one embodiment of the multiplexer of the present invention is used as a 2: 1 multiplexer, it is controlled so as to be fixed in a latch state. To be done.

Reference numeral 222 denotes a controlled selector which is controllable to function as a selector or a buffer, and when one embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer, A second control signal is output from the controlled D flip-flop 220 during the L level period and the H level period of the clock CLK / 4 using the clock CLK / 4 as a selection control signal.
The channel digital transmission signal DATA1 and the fourth channel digital transmission signal DATA3 output from the controlled P flip-flop 221 are alternately selected,
Digital transmission signals DATA1 and D of the second and fourth channels
Digital transmission signal DA obtained by time-division multiplexing ATA3
Outputting TA13, if one embodiment of the inventive multiplexer is used as a 2: 1 multiplexer,
The digital transmission signal DATA1 of the second channel output from the controlled D flip-flop 220 is controlled to function as a buffer. 22
2A is a buffer for adjusting the timing of the selection operation of the controlled selector 222.

223 is a 2: 1 multiplexer 2 in the first stage
It is a second-stage 2: 1 multiplexer provided corresponding to the outputs of 15 and 219. 224 is shown in FIG.
4) A D flip-flop having a configuration similar to that of the D flip-flop 8 shown in 4), and when one embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer, output from the 2: 1 multiplexer 215. The time-division multiplexed digital transmission signal DATA02 is fetched by using the clock CLK / 2 as a synchronizing signal, and is output from the 2: 1 multiplexer 215 when one embodiment of the multiplexer of the present invention is used as the 2: 1 multiplexer. Digital transmission signal DATA0 of the first channel
Is taken in using the clock CLK / 2 as a synchronization signal.

Reference numeral 225 is a P flip-flop having the same configuration as the P flip-flop 9 shown in FIG. 13 (FIG. 15), and one embodiment of the multiplexer of the present invention is 4: 1.
When used as a multiplexer, the time-division multiplexed digital transmission signal DATA 13 output from the 2: 1 multiplexer 219 is fetched by using the clock CLK / 2 as a synchronization signal, and one embodiment of the multiplexer of the present invention is 2: 1. When used as a multiplexer, the second channel digital transmission signal DATA1 output from the 2: 1 multiplexer 219 is taken in by using the clock CLK / 2 as a synchronization signal.

Reference numeral 226 is a selector having the same structure as the selector 10 shown in FIG. 13 (FIG. 16). Selector 2
26 is a 4: 1 embodiment of the multiplexer of the present invention.
When used as a multiplexer, clock C
In the L level period and the H level period of LK / 2, the time division multiplex digital transmission signal DATA02 output from the D flip-flop 224 and the time division multiplex digital transmission signal DATA13 output from the P flip-flop 225 are alternately selected. , Digital transmission signals D of the first to fourth channels
It outputs a digital transmission signal DATA0123 obtained by time division multiplexing ATA0 to DATA3.

Further, the selector 226 outputs from the D flip-flop 224 during the L level period and the H level period of the clock CLK / 2 when the embodiment of the multiplexer of the present invention is used as the 2: 1 multiplexer. 1st channel digital transmission signals DATA0 and P0
The digital transmission signal DATA1 output from the flip-flop 225 is alternately selected, and the digital transmission signal DATA01 obtained by time-division multiplexing the digital transmission signals DATA0 and DATA1 of the first and second channels is output. 226A is a buffer for adjusting the timing of the selection operation of the selector 226.

227 is a time division multiplexed digital transmission signal DATA012 output from the 2: 1 multiplexer 223.
3 or DATA01, output terminals 228 are provided for the controlled D flip-flop 216, the controlled P flip-flop 217, the controlled selector 218, based on the multiplicity control signal.
The control circuit controls the controlled D flip-flop 220, the controlled P flip-flop 221, and the controlled selector 222.

FIG. 2 is a circuit diagram showing a configuration example of the controlled D flip-flop 216.
The flip-flop 220 has the same structure. In FIG.
D is a data input terminal, ND is a negative phase data input terminal, Cin
Is a clock input terminal, NCin is a reverse phase clock input terminal,
Cnt is a control signal input terminal and NCnt is a reverse phase control signal input terminal.

In the case of this example, the first channel digital transmission signal DATA0 is applied to the data input terminal D, and the first channel negative phase digital transmission signal / DATA0 is applied to the negative phase data input terminal ND. Input terminal Cin
Is applied with the clock CLK / 4, and the anti-phase clock / CLK / 4 is applied to the anti-phase clock input terminal Cin.

When one embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer, the control signal input terminal Cnt is set to H level and the negative phase control signal input terminal NCnt is set to L level. When one embodiment is used as a 2: 1 multiplexer, the control signal input terminal Cnt is set to L level and the negative phase control signal input terminal NCnt is set to H level.

Numerals 229 and 230 are cascaded D latches, 231, 232 are clock switches for controlling the D latches 229 and 230, Q is a data output terminal, NQ is a negative phase data output terminal, and clock switches 231 and 23 are provided.
2 is a clock when the control signal input terminal Cnt is at H level and the anti-phase control signal input terminal NCnt is at L level (when one embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer). CL
K / 4 and negative phase clock / CLK / 4 are D latch 22
9 and 230 to cause the D latches 229 and 230 to function as D latches.

On the other hand, the control signal input terminal Cnt is at L level, and the reverse phase control signal input terminal NCnt is
Is set to the H level (when one embodiment of the multiplexer of the present invention is used as a 2: 1 multiplexer), the clock switch 231 operates the D latch 229.
To the D-latch 230 by supplying an H-level signal and an L-level signal, respectively, instead of the clock CLK / 4 and the anti-phase clock / CLK / 4, and causing the D-latch 229 to function as a buffer.
Instead of the K / 4 and the negative phase clock / CLK / 4, the L level signal and the H level signal are supplied, respectively, and the D latch 230 functions as a buffer.

FIG. 3 is a circuit diagram showing an example of the configuration of the D latch 229, and the D latch 230 has the same configuration. Figure 3
Among them, GND is a ground power supply, VSS is a negative power supply, D is a data input terminal, ND is a negative phase data input terminal, C is a clock input terminal, NC is a negative phase clock input terminal, and VC1 and VC2 are bias voltages 233 to 243. Is a transistor, 244
~ 246 are diodes, 247-251 are resistors, 25
Reference numerals 2 and 253 are inductors, 254 and 255 are capacitors, Q is a data output terminal, and NQ is a reverse phase data output terminal.

FIG. 4 is a circuit diagram showing a configuration example of the clock switch 231. In FIG. 4, GND is a ground power source, VSS
Is a negative power supply, Cin is a clock input terminal, NCin is a negative phase clock input terminal, Cnt is a control signal input terminal, NC
nt is a reverse phase control signal input terminal, VC1 and VC2 are bias voltages, and 256 to 266 are transistors, 267
~ 269 are diodes, 270-277 are resistors, 28
Reference numerals 0 and 281 are capacitors, Cout is an output terminal, and NCout is a negative phase output terminal.

In the case of this example, the clock CLK / 4 is applied to the clock input terminal Cin, and the negative phase clock input terminal N
A negative phase clock / CLK / 4 is applied to Cin, an output terminal Cout is connected to a clock input terminal Cin of the D latch 229, and a negative phase output terminal NCout is connected to a negative phase clock input terminal NCin of the D latch 229. .

Here, when the control signal input terminal Cnt is at H level and the anti-phase control signal input terminal NCnt is at L level (when one embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer). , Transistor 260 = ON, transistor 261 =
When turned off, the transistors 256 and 257 are in the active state and the transistors 258 and 259 are in the inactive state.
As a result, the clock switch 231 receives the clock CLK /
4 and the negative phase clock / CLK / 4, the clock CLK / 4 is output to the output terminal Cout, and the negative phase clock / CLK / is output to the negative phase output terminal NCout.
4 is output. In this case, the D latch 229 operates as a latch.

On the other hand, the control signal input terminal Cnt is at L level, and the reverse phase control signal input terminal NCnt is
Is set to the H level (when one embodiment of the multiplexer of the present invention is used as a 2: 1 multiplexer), transistor 260 = OFF, transistor 261 = ON, and transistors 256, 257 = inactive state. , The transistors 258 and 259 are activated. As a result, the clock switch 231 causes the clock CL
K / 4 and the reverse phase clock / CLK / 4 are not taken in.

In this case, the potentials of the nodes NA and NB are set so that the H level and the L level are output to the output terminal Cout and the negative phase output terminal NCout, respectively. As a result, in the D latch 229, the transistor 237 = ON and the transistor 238 = OFF are fixed, that is, the transistors 233 and 234 are fixed to the active state, and the transistors 235 and 236 are fixed to the inactive state.
The latch 229 will function as a buffer.

FIG. 5 is a circuit diagram showing a configuration example of the clock switch 232. In FIG. 5, GND is a ground power source, VSS
Is a negative power supply, Cin is a clock input terminal, NCin is a negative phase clock input terminal, Cnt is a control signal input terminal, NC
nt is a reverse phase control signal input terminal, VC1 and VC2 are bias voltages, 288 to 298 are transistors, and 299.
~ 301 is a diode, 302-309 is a resistor, 31
2, 313 are capacitors, Cout is an output terminal, and NCout is a negative phase output terminal.

In the case of this example, the clock CLK / 4 is applied to the clock input terminal Cin, and the negative phase clock input terminal N
The negative phase clock / CLK / 4 is applied to Cin, the output terminal Cout is connected to the clock input terminal Cin of the D latch 230, and the negative phase output terminal NCout is connected to the negative phase clock input terminal NCin of the D latch 230. .

Here, when the control signal input terminal Cnt is at H level and the anti-phase control signal input terminal NCnt is at L level (when one embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer). , Transistor 292 = ON, transistor 293 =
The transistor is turned off, and the transistors 288 and 289 are activated and the transistors 290 and 291 are deactivated. As a result, the clock switch 232 causes the clock CL
It functions as a buffer for the K / 4 and the negative phase clock / CLK / 4, the clock CLK / 4 is output to the output terminal Cout, and the negative phase clock / CL is output to the negative phase output terminal NCout.
K / 4 is output. In this case, the D latch 230 will operate as a latch.

On the other hand, the control signal input terminal Cnt is at L level, and the reverse phase control signal input terminal NCnt is
Is set to the H level (when one embodiment of the multiplexer of the present invention is used as a 2: 1 multiplexer), transistor 292 = OFF, transistor 293 = ON, and transistors 288 and 289 = inactive state. , The transistors 290 and 291 are activated. As a result, the clock switch 232 causes the clock CL
K / 4 and the reverse phase clock / CLK / 4 are not taken in. In this case, the potentials of the nodes NA and NB are set so that the L level and the H level are output to the output terminal Cout and the negative phase output terminal NCout, respectively. As a result, the D latch 230 is fixed in the latched state.

FIG. 6 is a circuit diagram showing a configuration example of the controlled P flip-flop 217.
The flip-flop 221 has the same structure. In FIG.
D is a data input terminal, ND is a negative phase data input terminal, Cin
Is a clock input terminal, NCin is a reverse phase clock input terminal,
Cnt is a control signal input terminal and NCnt is a reverse phase control signal input terminal.

In the case of this example, the digital transmission signal DATA2 of the third channel is applied to the data input terminal D only when one embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer, and the negative phase data input terminal is applied. The negative phase digital transmission signal / DATA2 of the third channel is applied to the ND only when one embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer, and the clock CLK / 4 is applied to the clock input terminal Cin. The reverse phase clock / CLK / 4 is applied to the reverse phase clock input terminal NCin.

When one embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer, the control signal input terminal Cnt is set to H level and the negative phase control signal input terminal NCnt is set to L level. When one embodiment is used as a 2: 1 multiplexer, the control signal input terminal Cnt is set to L level and the negative phase control signal input terminal NCnt is set to H level.

Reference numerals 282 to 284 are D latches connected in cascade, and the D latches 282 to 284 are constructed similarly to the D latch 229 shown in FIG. 2 (FIG. 3). 285 to 287 are clock switches for controlling the D latches 282 to 284, and the clock switches 285 and 287 are shown in FIG. 2 (FIG. 5).
2 and the clock switch 286 is configured similarly to the clock switch 231 shown in FIG. 2 (FIG. 4). Q is the data output terminal,
NQ is a reverse phase data output terminal, and the clock switch 2
85 to 287 are provided when the control signal input terminal Cnt is at H level and the negative phase control signal input terminal NCnt is at L level (when one embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer). , The clock CLK / 4 and the negative phase clock / CLK / 4 are supplied to the D latches 282 to 284, and the D latches 282 to 284 are supplied.
To function as a D latch.

On the other hand, the control signal input terminal Cnt is at L level, and the reverse phase control signal input terminal NCnt is
Is set to the H level (when one embodiment of the multiplexer of the present invention is used as a 2: 1 multiplexer), the clock switches 285 and 287 cause the D latches 282 and 284 to output the clock CLK / 4 and the reverse phase. Instead of the clock / CLK / 4, the L level signal and the H level signal are respectively supplied to fix the D latches 282 and 284 in the latched state, and the clock switch 286 causes the D latch 283 to output the clock CLK / 4 and the anti-phase clock. / CL
Instead of K / 4, an H level signal and an L level signal are supplied to fix the D latch 283 in the latched state.

FIG. 7 is a circuit diagram showing an example of the structure of the controlled selector 218, and the controlled selector 222 has the same structure. In FIG. 7, D0 is a first data input terminal, ND0 is a first negative phase data input terminal, D1 is a second data input terminal, ND1 is a second negative phase data input terminal,
Q is the data output terminal, NQ is the negative phase data output terminal, Cin
Is a clock input terminal, NCin is a reverse phase clock input terminal,
Cnt is a control signal input terminal, NCnt is a reverse phase control signal input terminal, 314 is a selector having the same configuration as the selector 10 shown in FIG. 13 (FIG. 16), and 315 is a clock switch 232 shown in FIG. 2 (FIG. 5). It is a clock switch having a similar configuration.

In the case of this example, the first data input terminal D0 is connected to the data output terminal Q of the controlled D flip-flop 216, and the first negative phase data input terminal is the negative phase data output terminal of the controlled D flip-flop 216. N
Q, the second data input terminal D1 is connected to the data output terminal Q of the controlled P flip-flop 217, and the second negative phase data input terminal ND1 is connected to the negative phase data output terminal NQ of the controlled P flip-flop 217. The clock CLK / is connected to the clock input terminal Cin.
4 is applied, and / clock CLK / 4 is applied to the negative phase clock input terminal NCin.

Therefore, the control signal input terminal C
When nt is at H level and the anti-phase control signal input terminal NCnt is at L level (when one embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer)
Therefore, the clock switch 315 supplies the clock CLK / 4 and the negative phase clock / CLK / 4 to the selector 314. As a result, the selector 314 alternately selects the digital transmission signal DATA0 of the first channel output from the controlled D flip-flop 216 and the digital transmission signal DATA2 of the third channel output from the controlled P flip-flop 217, First,
Digital transmission signals DATA0 and DATA of the third channel
Digital transmission signal DATA0 obtained by time-division multiplexing 2
2 will be output.

On the other hand, the control signal input terminal Cnt is at L level, and the reverse phase control signal input terminal NCnt.
Is set to the L level (when one embodiment of the multiplexer of the present invention is used as a 2: 1 multiplexer), the clock switch 315 operates the selector 314.
To the clock CLK / 4 and anti-phase clock / CL
Instead of K / 4, an L level signal and an H level signal will be supplied. As a result, the selector 314 functions as a buffer for the first channel digital transmission signal DATA0 output from the controlled D flip-flop 216.

FIG. 8 is a circuit diagram for explaining the operation when one embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer. When the embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer, that is, the digital transmission signals DATA0 to D of the first to fourth channels are input to the digital transmission signal input terminals 208 to 211.
When each ATA3 (for example, 10 Gbps) is applied, the multiplicity control signal is set to H level, and the clock CLK / 4 (for example, 10 GH) is applied to the clock input terminal 212.
z) is applied and the clock C is applied to the clock input terminal 213.
LK / 2 (for example, 20 GHz) is applied.

In this case, the control circuit 228 controls the control signal input terminals Cnt of the controlled D flip-flops 216 and 220, the controlled P flip-flops 217 and 221 and the controlled selectors 218 and 222 to the H level and the reverse phase control signal. Input terminal NC
Set nt to L level.

As a result, the controlled D flip-flop 216 functions as a D flip-flop, the controlled P flip-flop 217 functions as a P flip-flop, and the controlled selector 218 functions as a selector. That is, in this case, the 2: 1 multiplexer 215 functions as a 2: 1 multiplexer,
The output node of the 2: 1 multiplexer 215 has a first,
Digital transmission signals DATA0 and DATA of the third channel
Digital transmission signal DATA0 obtained by time-division multiplexing 2
2 (for example, 20 Gbps) is output.

The controlled D flip-flop 220 functions as a D flip-flop, the controlled P flip-flop 221 functions as a P flip-flop, and the controlled selector 222 functions as a selector. That is, in this case, the 2: 1 multiplexer 219 functions as a 2: 1 multiplexer, and 2:
The output node of the 1-multiplexer 219 has the second and fourth
Digital transmission signal DATA13 obtained by time-division multiplexing channel digital transmission signals DATA1 and DATA3
(For example, 20 Gbps) is output.

Therefore, the 2: 1 multiplexer 223
Functions as a 2: 1 multiplexer for the time division multiplexed digital transmission signal DATA02 output from the 2: 1 multiplexer 215 and the time division multiplexed digital transmission signal DATA13 output from the 2: 1 multiplexer 219. 4-channel digital transmission signal DATA0
The digital transmission signal DATA0123 (for example, 40 Gbps) obtained by time-division multiplexing DATA3 is output.

FIG. 9 is a circuit diagram for explaining the operation when one embodiment of the multiplexer of the present invention is used as a 2: 1 multiplexer. When one embodiment of the multiplexer of the present invention is used as a 2: 1 multiplexer, that is, the digital transmission signals DATA0, D of the first and second channels are input to the digital transmission signal input terminals 208, 210.
When ATA1 (for example, 10 Gbps) is applied, the multiplicity control signal is set to L level, and the clock CLK / 2 (for example, 10 GH) is applied to the clock input terminal 213.
z) is applied.

In this case, the control circuit 228 controls the control signal input terminals Cnt of the controlled D flip-flops 216 and 220, the controlled P flip-flops 217 and 221 and the controlled selectors 218 and 222 to the L level and the reverse phase control signal. Input terminal NC
Set nt to H level.

As a result, the controlled D flip-flop 216 functions as a buffer and the controlled P flip-flop
The flip-flop 217 is fixed in the latched state, and the controlled selector 218 functions as a buffer for the output of the controlled D flip-flop 216. That is, in this case, the 2: 1 multiplexer 215 functions as a buffer, and the output node of the 2: 1 multiplexer 215 has a digital transmission signal DAT of the first channel.
A0 is output.

Further, the controlled D flip-flop 220 functions as a buffer, the controlled P flip-flop 221 is fixed in a latched state, and the controlled selector 222 functions as a buffer for the output of the controlled D flip-flop 220. To do.
That is, in this case, the 2: 1 multiplexer 219 functions as a buffer, and the output node of the 2: 1 multiplexer 219 has the second channel digital transmission signal DATA1.
Is output.

Therefore, the 2: 1 multiplexer 223
Functions as a 2: 1 multiplexer for the first-channel digital transmission signal DATA0 output from the 2: 1 multiplexer 215 and the second-channel digital transmission signal DATA1 output from the 2: 1 multiplexer 219. , Second channel digital transmission signal DAT
A digital transmission signal DATA01 (for example, 20 Gbps) obtained by time-division multiplexing A0 and DATA1 is output.

As described above, according to one embodiment of the multiplexer of the present invention, the multiplicity can be set to 4: 1 or 2: 1 without changing the circuit configuration, so that 4: 4 is possible.
It is not necessary to design two types of multiplexers, 1 multiplexer and 2: 1 multiplexer.

When the embodiment of the multiplexer of the present invention is used as a 4: 1 multiplexer, if the clock input terminal 213 is fixed at H level, the output of the 2: 1 multiplexer 215 is output as a digital transmission signal. It can be output to the terminal 227 for monitoring.

Therefore, the 2: 1 multiplexer 215
Since it is not necessary to provide a branch in the wiring connected to the output node of, the disturbance of the signal waveform due to the branch of the wiring can be avoided and the disadvantage of layout that the number of digital transmission signal output terminals increases can be avoided. it can.

In the embodiment of the multiplexer of the present invention, the case where the 2: 1 multiplexer has a two-stage configuration has been described. However, the present invention also applies when the 2: 1 multiplexer has a three-stage configuration or more. Can be applied. When the 2: 1 multiplexer has an n-stage configuration, the first to (n-1) th 2: 1 multiplexers are controlled D flip-flops, controlled P flip-flops, and controlled selectors. In the case of the above configuration, the multiplicity can be 2 ⁿ : 1 or 2 ^{n -1} or ... 2: 1.

(One Embodiment of the Demultiplexer of the Present Invention ... FIGS. 10 to 12) FIG. 10 is a circuit diagram showing a main part of one embodiment of the demultiplexer of the present invention. One embodiment of the demultiplexer of the present invention is a demultiplexer in which a 1: 2 demultiplexer is configured in two stages, and can function as a 1: 4 demultiplexer or a 1: 2 demultiplexer according to a distribution control signal. It is a thing.

In FIG. 10, reference numeral 316 is a digital transmission signal input terminal, and when one embodiment of the demultiplexer of the present invention is used as a 1: 4 demultiplexer, digital transmission signals of the first to fourth channels. DATA0-DA
Digital transmission signal DAT obtained by time division multiplexing TA3
When A0123 is input and one embodiment of the demultiplexer of the present invention is used as a 1: 2 demultiplexer, the digital transmission signals DATA of the first and second channels are input.
0 and DATA1 are used for inputting a digital transmission signal DATA01 obtained by time-division multiplexing.

Reference numerals 317 and 318 are clock input terminals. The clock input terminal 317 is a time division multiplexed digital transmission signal D in the case where one embodiment of the demultiplexer of the present invention is used as a 1: 4 demultiplexer.
When a clock CLK / 2 having a frequency half that of the bit transfer frequency of ATA0123 is input and one embodiment of the demultiplexer of the present invention is used as a 1: 2 demultiplexer, the time division multiplexed digital transmission signal DATA0.
A clock CL having a frequency half that of the bit transfer frequency of 1
Used to enter K / 2.

Clock input terminal 318 is a time division multiplexed digital transmission signal D when one embodiment of the demultiplexer of the present invention is used as a 1: 4 demultiplexer.
When the clock CLK / 4 having a frequency 1/4 of the bit transfer frequency of ATA0123 is input, and one embodiment of the demultiplexer of the present invention is used as a 1: 2 demultiplexer, it is not used.

319 uses one embodiment of the demultiplexer of the present invention as a 1: 4 demultiplexer,
A distribution degree control signal input terminal for inputting a distribution degree control signal for setting whether to use as a 1: 2 demultiplexer, and one embodiment of the demultiplexer of the present invention is used as a 1: 4 demultiplexer. In this case, the distribution control signal is at the H level, and when one embodiment of the demultiplexer of the present invention is used as a 1: 2 demultiplexer, the distribution control signal is at the L level.

Reference numeral 320 is a first-stage 1: 2 demultiplexer. Reference numeral 321 denotes a P flip-flop having a configuration similar to that of the P flip-flop 9 shown in FIG. 13 (FIG. 15), and when one embodiment of the demultiplexer of the present invention is used as a 1: 4 demultiplexer, it is digital. The clock CLK / 2 is used to capture the digital transmission signal DATA02 obtained by time division multiplexing the digital transmission signals DATA0 and DATA2 of the first and third channels included in the time division multiplexed digital transmission signal DATA0123 input from the transmission signal input terminal 316. The demultiplexer of the present invention has a timing of 1: 2.
When used as a demultiplexer, the first channel digital transmission signal DATA0 included in the time division multiplexed digital transmission signal DATA01 input from the digital transmission signal input terminal 316 is taken in by the clock CLK.
It is performed at the timing of the falling edge of / 2.

Reference numeral 322 is a D flip-flop having the same structure as the D flip-flop 8 shown in FIG. 13 (FIG. 14), and one embodiment of the demultiplexer of the present invention is 1:
When used as a 4-demultiplexer, the second and fourth signals contained in the time division multiplexed digital transmission signal DATA 0123 input from the digital transmission signal input terminal 316 are included.
The digital transmission signal DATA13 obtained by time-division-multiplexing the channel digital transmission signals DATA1 and DATA3 is taken in at the rising timing of the clock CLK / 2, and one embodiment of the demultiplexer of the present invention is used as a 1: 2 demultiplexer. In this case, the digital transmission signal DATA1 of the second channel included in the time division multiplexed digital transmission signal DATA01 input from the digital transmission signal input terminal 316 is taken in at the rising timing of the clock CLK / 2. .

Reference numeral 323 is a second-stage 1: 2 demultiplexer provided corresponding to the output of the P flip-flop 321 of the 1: 2 demultiplexer 320. Reference numeral 324 denotes a controlled P flip-flop having the same configuration as the controlled P flip-flop 217 shown in FIG. 1 (FIG. 6), in the case where one embodiment of the demultiplexer of the present invention is used as a 1: 4 demultiplexer. The digital transmission signal DATA0 of the first channel included in the time division multiplexed digital transmission signal DATA02 output from the P flip-flop 321 is taken in by using the clock CLK / 4 as a synchronization signal, and one embodiment of the demultiplexer of the present invention is implemented. When the form is used as a 1: 2 demultiplexer, it is controllable so as to function as a buffer for the digital transmission signal DATA0 of the first channel output from the P flip-flop 321.

Reference numeral 325 is a controlled D flip-flop having the same structure as the controlled D flip-flop 216 shown in FIG. 1 (FIG. 2), and one embodiment of the demultiplexer of the present invention is used as a 1: 4 demultiplexer. In such a case, the digital transmission signal DATA2 of the third channel included in the time division multiplexed digital transmission signal DATA02 output from the P flip-flop 321 is fetched by using the clock CLK / 4 as a synchronization signal,
When one embodiment of the demultiplexer of the present invention is used as a 1: 2 demultiplexer, it is controlled so that it is locked in the latched state.

Reference numeral 326 is a second-stage 1: 2 demultiplexer provided corresponding to the output of the D flip-flop 322 of the 1: 2 demultiplexer 320. Reference numeral 327 is a controlled P flip-flop having the same configuration as the controlled P flip-flop 217 shown in FIG. 1 (FIG. 6), and when one embodiment of the demultiplexer of the present invention is used as a 1: 4 demultiplexer. The clock CLK / is used to capture the second digital transmission signal DATA1 included in the time division multiplexed digital transmission signal DATA13 output from the D flip-flop 322.
4 as a synchronizing signal, and when one embodiment of the demultiplexer of the present invention is used as a 1: 2 demultiplexer, it buffers the second channel digital transmission signal DATA1 output from the D flip-flop 322. It can be controlled to function as.

Reference numeral 328 is a controlled D flip-flop having the same structure as the controlled D flip-flop 216 shown in FIG. 1 (FIG. 2), and one embodiment of the demultiplexer of the present invention is used as a 1: 4 demultiplexer. In this case, the digital transmission signal DATA1 of the second channel included in the time division multiplexed digital transmission signal DATA13 output from the D flip-flop 322 is captured by using the clock CLK / 4 as a synchronization signal,
When one embodiment of the demultiplexer of the present invention is used as a 1: 2 demultiplexer, it is controlled so that it is locked in the latched state.

Reference numerals 329 to 332 are digital transmission signal output terminals. The digital transmission signal output terminal 329 is a controlled P flip-flop 324 regardless of whether the embodiment of the demultiplexer of the present invention is used as a 1: 4 demultiplexer or a 1: 2 demultiplexer. It is used to output the digital transmission signal DATA0 of the first channel output from the outside.

The digital transmission signal output terminal 330 is the digital transmission signal of the third channel output from the controlled D flip-flop 325 when one embodiment of the demultiplexer of the present invention is used as a 1: 4 demultiplexer. It is used to output the signal DATA2 to the outside, and one embodiment of the demultiplexer of the present invention is 1:
When used as a 2-demultiplexer, it is not used.

The digital transmission signal output terminal 331 is controlled by the control signal P whether the embodiment of the demultiplexer of the present invention is used as a 1: 4 demultiplexer or a 1: 2 demultiplexer. It is used to output the second channel digital transmission signal DATA1 output from the flip-flop 327 to the outside.

The digital transmission signal output terminal 332 is the digital transmission signal of the fourth channel output from the controlled D flip-flop 328 when one embodiment of the demultiplexer of the present invention is used as a 1: 4 demultiplexer. It is used to output the signal DATA3 to the outside, and one embodiment of the demultiplexer of the present invention is 1:
When used as a 2-demultiplexer, it is not used.

Reference numeral 333 denotes a controlled P flip-flop 324 and a controlled D flip-flop based on the distribution control signal.
Flip-flop 325, controlled P flip-flop 327 and controlled D flip-flop 3
28 is a control circuit for controlling 28.

FIG. 11 is a circuit diagram for explaining the operation when one embodiment of the demultiplexer of the present invention is used as a 1: 4 demultiplexer. When one embodiment of the demultiplexer of the present invention is used as a 1: 4 demultiplexer, that is, digital transmission signal input terminal 316
First to fourth digital transmission signals DATA0 to DATA0
A digital transmission signal DATA0123 (for example, 40 Gbps) obtained by time division multiplexing DATA3 (for example, 10 Gbps)
s) is applied, the distribution control signal = H level, and the clock input terminal 317 receives the clock CLK / 2.
(For example, 20 GHz) is applied, and clock input terminal 3
18 has a clock CLK / 4 (for example, 10 GHz)
Is applied.

In this way, the 1: 2 demultiplexer 320 makes the time division multiplexed digital transmission signal DATA01.
23, and the time division multiplexed digital transmission signal DATA02 (for example, 20 Gbps) is output to the output node of the P flip-flop 321 and the D flip-flop 32 is output.
The output node of 2 has a time division multiplexed digital transmission signal DAT.
A13 (for example, 20 Gbps) is output.

Further, in the case of this example, by setting the distribution control signal = H level, the control circuit 333 causes the control signal input terminal Cin of the controlled P flip-flops 324, 327 and the controlled D flip-flops 325, 328. Is set to H level, the reverse phase control signal input terminal NCin is set to L level, the controlled P flip-flops 324 and 327 are caused to function as P flip-flops, and the controlled D flip-flop 32 is
5, 328 will function as a D flip-flop.

As a result, the 1: 2 demultiplexer 323 is provided.
Functions as a 1: 2 demultiplexer, distributes the time division multiplexed digital transmission signal DATA02 output from the P flip-flop 321, and outputs the digital transmission signal DATA0 of the first channel to the digital transmission signal output terminal 329.
(For example, 10 Gbps) is output, and the digital transmission signal D of the third channel is output to the digital transmission signal output terminal 330.
ATA2 (for example, 10 Gbps) is output.

Also, the 1: 2 demultiplexer 326 is
It functions as a 1: 2 demultiplexer, distributes the time division multiplexed digital transmission signal DATA 13 output from the D flip-flop 322, and outputs the digital transmission signal output terminal 33.
The digital transmission signal DATA1 (for example, 10 Gbps) of the second channel is output to the terminal 1, and the digital transmission signal DAT of the fourth channel to the digital transmission signal output terminal 332.
A3 (for example, 10 Gbps) is output.

FIG. 12 is a circuit diagram for explaining the operation when one embodiment of the demultiplexer of the present invention is used as a 1: 2 demultiplexer. When one embodiment of the demultiplexer of the present invention is used as a 1: 2 demultiplexer, that is, digital transmission signal input terminal 316
First and second channel digital transmission signals DATA0,
A digital transmission signal DATA01 (for example, 20 Gbps, which is time-division multiplexed with DATA1 (for example, 10 Gbps))
s) is applied, the distribution control signal = L level, and the clock input terminal 317 receives the clock CLK / 2.
(For example, 10 GHz) is applied.

In this way, the 1: 2 demultiplexer 320 outputs the time division multiplexed digital transmission signal DATA01.
The digital transmission signal DATA0 of the first channel (for example,
10 Gbps) is output, and the digital transmission signal DAT of the second channel is output to the output node of the D flip-flop 322.
A1 (for example, 10 Gbps) is output.

Further, in the case of this example, by setting the distribution control signal = L level, the control circuit 333 causes the control signal input terminal Cin of the controlled P flip-flops 324, 327 and the controlled D flip-flops 325, 328. Is set to L level, the negative phase control signal input terminal NCin is set to H level, the controlled P flip-flops 324 and 327 function as buffers, and the controlled D flip-flops 325 and 328 are set.
Will be fixed in the latched state.

As a result, the digital transmission signal output terminal 32
The first channel digital transmission signal DATA0 (for example, 10 Gbps) is output to 9 and the second channel digital transmission signal DAT is output to the digital transmission signal output terminal 331.
A1 (for example, 10 Gbps) is output.

As described above, according to one embodiment of the demultiplexer of the present invention, since the distribution degree can be set to 1: 4 or 1: 2, the 1: 4 demultiplexer and the 1: 2 demultiplexer can be used.
There is no need to design two types of demultiplexers.

When the embodiment of the demultiplexer of the present invention is used as a 1: 4 demultiplexer, when the distribution control signal is at L level, it is 1:
P flip-flop 321 of the 2 demultiplexer 320
Can be output to the digital transmission signal output terminal 329 for monitoring.

Therefore, it is not necessary to provide a branch in the wiring connected to the output node of the P flip-flop 321, the disturbance of the signal waveform due to the branch of the wiring can be avoided, and the number of digital transmission signal output terminals is increased. Layout disadvantages can be avoided.

In the embodiment of the demultiplexer of the present invention, the case where the 1: 2 demultiplexer has a two-stage configuration has been described, but the demultiplexer of the present invention has a 1: 2 demultiplexer having three or more stages. It can also be applied to the case of configuration. In the case where the 1: 2 demultiplexer has an n-stage configuration, if the second and subsequent 1: 2 multiplexers are composed of a controlled P flip-flop and a controlled D flip-flop, the distribution degree is 1: 2 ⁿ or 1: 2 ^n-1 or ... 1: 2
Can be

[0157]

As described above, according to the multiplexer of the present invention, the controllable 2: 1 multiplexer functions as the 2: 1 multiplexer for the first and second digital transmission signals, or the first: The multiplicity can be changed by controlling the digital transmission signal so as to function as a buffer, and it is not necessary to design multiplexers having different multiplicities within a range in which the multiplicity is variable.

Further, according to the demultiplexer of the present invention, the controllable 1: 2 demultiplexer functions as a 1: 2 demultiplexer for the fifth digital transmission signal, or for the fifth digital transmission signal. The distribution degree can be changed by controlling so as to function as a buffer, and it is not necessary to design demultiplexers having different distribution degrees within a range in which the distribution degree is variable.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main part of an embodiment of a multiplexer of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a controlled D flip-flop included in the multiplexer of the present invention.

FIG. 3 is a circuit diagram showing a configuration example of a D latch forming a controlled D flip-flop included in the multiplexer of the present invention.

FIG. 4 is a circuit diagram showing a configuration example of a clock switch that constitutes a controlled D flip-flop included in the multiplexer of the present invention.

FIG. 5 is a circuit diagram showing a configuration example of a clock switch that constitutes a controlled P flip-flop included in the multiplexer of the present invention.

FIG. 6 is a circuit diagram showing a configuration example of a controlled P flip-flop included in the multiplexer of the present invention.

FIG. 7 is a circuit diagram showing a configuration example of a controlled selector included in the multiplexer of the present invention.

FIG. 8 illustrates one embodiment of a multiplexer of the present invention, 4: 1.
FIG. 9 is a circuit diagram for explaining an operation when used as a multiplexer.

FIG. 9 is a 2: 1 embodiment of a multiplexer of the present invention.
FIG. 9 is a circuit diagram for explaining an operation when used as a multiplexer.

FIG. 10 is a circuit diagram showing a main part of an embodiment of a demultiplexer of the present invention.

FIG. 11 is a circuit diagram for explaining an operation when an embodiment of the demultiplexer of the present invention is used as a 1: 4 demultiplexer.

FIG. 12 is a circuit diagram for explaining an operation when one embodiment of the demultiplexer of the present invention is used as a 1: 2 demultiplexer.

FIG. 13 is a circuit diagram showing a main part of a first conventional example of a multiplexer.

14 is a circuit diagram showing a configuration example of a D flip-flop included in the first conventional example of the multiplexer shown in FIG.

15 is a circuit diagram showing a configuration example of a P flip-flop included in the first conventional example of the multiplexer shown in FIG.

16 is a circuit diagram showing a configuration example of a selector included in the first conventional example of the multiplexer shown in FIG.

17 is a timing chart showing an operation of the first conventional example of the multiplexer shown in FIG.

FIG. 18 is a circuit diagram showing a second conventional example of a multiplexer.

FIG. 19 is a circuit diagram showing a main part of a first conventional example of a demultiplexer.

20 is a timing chart showing an operation of the first conventional example of the demultiplexer shown in FIG.

FIG. 21 is a circuit diagram showing a main part of a second conventional example of a demultiplexer.

[Explanation of symbols]

DATA ... Digital transmission signal CLK ... clock

Claims (5)

[Claims] 1. A multiplexer comprising a plurality of 2: 1 multiplexers connected in multiple stages, which functions as a 2: 1 multiplexer for the first and second digital transmission signals or for the first digital transmission signals. A multiplexer comprising a 2: 1 multiplexer controllable to function as a buffer. 2. The controllable 2: 1 multiplexer includes a first flip-flop controllable to function as a flip-flop or a buffer for the first digital transmission signal; A second flip-flop that can be controlled so as to function as a flip-flop or be fixed in a latch state for two digital transmission signals; and the first and second flip-flops that output from the first and second flip-flops. And a selector controllable to function as a selector for alternately selecting two digital transmission signals or to function as a buffer for the first digital transmission signal output from the first flip-flop, When the first and second flip-flops function as flip-flops, the first and second flip-flops are provided. 2. The multiplexer according to claim 1, wherein the first and second digital transmission signals output from the converter have a phase difference of 180 °. 3. A demultiplexer in which 1: 2 demultiplexers are connected in multiple stages, and 1: 2 with respect to a fifth digital transmission signal obtained by time-division-multiplexing third and fourth digital transmission signals. 1: 2 controllable to act as a demultiplexer or as a buffer for the fifth digital transmission signal
A demultiplexer including a demultiplexer. 4. The controllable 1: 2 demultiplexer functions as a flip-flop with respect to the third digital transmission signal included in the fifth digital transmission signal, or the fifth digital transmission signal. A third flip-flop that can be controlled to function as a buffer, and that functions as a flip-flop with respect to the fourth digital transmission signal included in the fifth digital transmission signal or is fixed in a latched state. And a third flip-flop that can be controlled so that the third and fourth flip-flops output the third and fourth flip-flops when functioning as flip-flops. 4. The demultiplexer according to claim 3, wherein the fourth digital transmission signals have the same phase. 5. A latch comprising: a latch controllable to function as a latch or a buffer; and a control circuit controlling the latch so that the latch functions as a latch or a buffer.